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Cypress CY24271 - page 1
CY24272 Rambus ® XDR™ Clock Generator with Zero SDA Hold T ime Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-42414 Rev . ** Revised November 9, 2007 Features ■ Meets Rambus ® Extended Data Rate (XDR™) clocking requirements ■ 25 ps typical c ycle-to-cycle jitter ...
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Cypress CY24271 - page 2
CY24272 Document Number: 001-42414 Rev . ** Page 2 of 13 Pinout s T able 2. Pin Definition - 28 Pin TSSOP Pin No. Name IO Descriptio n 1 VDDP PWR 2.5V power supply fo r phased lock loop (PLL) 2 VSSP GND Ground 3 ISET I Set clock driver cur rent (external resistor) 4 VSS GND Ground 5 REFCLK I Reference clock input (connect to clock source) 6 REFCLKB ...
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Cypress CY24271 - page 3
CY24272 Document Number: 001-42414 Rev . ** Page 3 of 13 PLL Multiplier Ta b l e 3 shows the frequency multi pliers in the PLL, selectable by programming the SMBus registers MUL T0, MUL T1, and MUL T2. Default multiplier a t power up is 4 . T able 3. PLL Multipl ier Selection Input Clock Signal The XCG receives either a differ enti al (REFCLK/ REFC ...
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Cypress CY24271 - page 4
CY24272 Document Number: 001-42414 Rev . ** Page 4 of 13 Device ID and SMBus Device Address The device ID (ID0 and ID1) is a part of the SMBus device 8-bit address. The least significa nt bi t of the ad dress designates a write or read operation. Ta b l e 4 o n page 3 shows the addresses for four CY24272 devices on the same SMBus. SMBus Protocol Th ...
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Cypress CY24271 - page 5
CY24272 Document Number: 001-42414 Rev . ** Page 5 of 13 Note 5. RW = Read and W rite, RO = Read On ly , POD = Power on def ault . See T able 3 on page 3 f or PLL mul tip liers a nd T able 5 on p ag e 4 f or cl ock out put select ions. T able 6. Command Code 80h [5] Bit Register POD Ty p e Descr iption 7 Reserved 0 R W Reserved (no internal functio ...
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Cypress CY24271 - page 6
CY24272 Document Number: 001-42414 Rev . ** Page 6 of 13 Figure 2. Differential and Single-Ended Clock Inpu t s Absolute Maximum Conditions Parameter Description Condition Min Max Unit V DD Clock Buffer Supply V oltage –0.5 4.6 V V DDC Core Supply V ol tage –0.5 4.6 V V DDP PLL Supply V oltage –0.5 4.6 V V IN Input V oltage (SCL and SDA) Rela ...
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Cypress CY24271 - page 7
CY24272 Document Number: 001-42414 Rev . ** Page 7 of 13 DC Operating Conditions Parameter Description Condition Min Max Unit V DDP Supply V oltage for PLL 2.5V ± 5% 2.375 2.625 V V DDC Supply V oltage for Core 2.5V ± 5% 2.375 2.625 V V DD Supply V oltage for Clock Buf fers 2.5V ± 5% 2.375 2.625 V V IHCLK Input High V oltage, REFCLK/REFCLKB 0.6 ...
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Cypress CY24271 - page 8
CY24272 Document Number: 001-42414 Rev . ** Page 8 of 13 AC Operating Conditions The AC operating cond itions follo w . [6] Parameter Description Condition Mi n Max Unit t CYCLE,IN REFCLK, REFCLKB input cycle time REFSEL = 0, /BYP ASS = High 9 1 1 ns REFSEL = 1, /BYP ASS = High 7 8 ns /BYP ASS = Low 4 – n s t JIT ,IN(cc) Input Cycle to Cycle Jitt ...
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Cypress CY24271 - page 9
CY24272 Document Number: 001-42414 Rev . ** Page 9 of 13 AC Electrical Specification The AC Electrical specifications follow . [6] Parameter Description Min Ty p Max Unit t CYCLE Clock Cycle time [19] 1.25 3.34 ns t JIT(cc) Jitter over 1-6 clock cycles at 400–635 MHz [20] –2 5 4 0 p s Jitter over 1-6 clock cycles at 638–667 MHz – 25 30 ps L ...
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Cypress CY24271 - page 10
CY24272 Document Number: 001-42414 Rev . ** Page 10 of 13 T est and Measurement Setup Figure 3. Clock Ou tput s Signal W aveforms A physical signal that appears at th e pins of a device is deemed valid or invalid depe nding on its voltage and timing relations with other signals. Input and ou tput voltage waveforms are defined as shown in Figure 4 o ...
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Cypress CY24271 - page 11
CY24272 Document Number: 001-42414 Rev . ** Page 1 1 of 13 Figure 4. Input and Output Waveforms Figure 5. Cros sing Point V olta ge Figure 6. Cycle-to-cycle Jitter Figure 7. Cyc le-to-cycle Duty-cycle Error V H t R t F 80% 20% V L V (t) Vx.nom CLK CLKB Vx+ Vx- CLK CLKB t CYCLE,i t CYCLE,i+1 t J = t CYCLE ,i - t CYCLE,i+1 over 10,000 consec utive cy ...
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Cypress CY24271 - page 12
CY24272 Document Number: 001-42414 Rev . ** Page 12 of 13 Package Drawing and Dimension Figure 8. 28-Pin Thin Shrunk Small Outline Package (4.40-mm Body) ZZ28 Ordering Information Part Number Package T ype Produc t Flow Pb-Free CY24272ZXC 28-pin TSSOP Commercial, 0°C to 70°C CY24272ZXCT 28-pin TSSOP – T ape and Reel Commercial, 0°C to 70°C PI ...
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Cypress CY24271 - page 13
Document Number: 001-42414 Rev . ** Revi sed November 9, 2007 Page 13 of 13 PSoC Designer™, Programmable System-on-Chip ™, an d PS oC Exp re ss™ are tra demarks a nd PSo C® is a registe red t rade mark of Cypress S emi con ductor Corp. A ll o the r tr a dem a rks o r re gi ster e d trademar ks refere nced herei n are prop erty of the respe c ...
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