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Cypress 001-07160 - page 1
18-Mbit DDR II SRAM 2-W ord Burst Architecture CY7C1318CV18 CY7C1320CV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1 709 • 408-943-2600 Document Number: 001-07160 Rev . *F Revised August 24, 2009 Features ■ 18-Mbit Density (1M x 18, 512K x 36) ■ 267 MHz Clock for high Bandwidth ■ 2-word Burst fo r red ...
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Cypress 001-07160 - page 2
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 2 of 26 Logic Block Diagram (CY7C1318CV18) Logic Block Diagram (CY7C1320CV18) Wri te Reg Write Reg CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 18 36 18 BWS [1:0] V REF Write Add. Decode 18 20 C C 18 LD Control ...
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Cypress 001-07160 - page 3
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 3 of 26 Pin Configuration The pin configuration for CY7C1318CV18 and CY7C 1320CV18 follow . [1] 165-Ball FBGA (13 x 15 x 1 .4 mm) Pinout CY7C1318CV18 (1M x 18) 123456789 10 11 A CQ NC/72M A R/W BWS 1 K NC/14 4M LD A NC/36M CQ B NC DQ9 NC A NC/288M K BWS 0 AN C N C D Q 8 C NC NC NC V ...
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Cypress 001-07160 - page 4
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 4 of 26 Pin Definitions Pin Name I/O Pin Description DQ [x:0] Input Output- Synchronous Dat a Input Output S ignals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins dri ve out t he requested data during a read opera tion. V alid dat ...
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Cypress 001-07160 - page 5
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 5 of 26 DOFF Input DLL T urn Off − Active LOW . Connecting this pin to gro und turns off the DLL inside the device . The timing in the DLL tu rned off operation is diff erent from th at listed in this da ta sheet. For normal operation, this pin can be connected to a pull up throug ...
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Cypress 001-07160 - page 6
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 6 of 26 Functional Overview The CY7C1318CV18, and CY7C1 320CV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface , which operates with a read latency of o ne and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to V SS the device beha ...
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Cypress 001-07160 - page 7
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 7 of 26 Programmable Impedan ce An external resistor , RQ, must be connected between the Z Q pin on the SRAM and V SS to e nable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of th e intended line impedance d riven by the SRAM. The allowable ra ...
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Cypress 001-07160 - page 8
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 8 of 26 T ruth T able The truth table for the CY7C1318CV18, and CY7C1320CV1 8 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ DQ Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. L-H L L D(A1) at K(t + 1) ↑ D(A2) at K (t + 1) ↑ Re ...
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Cypress 001-07160 - page 9
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 9 of 26 Write Cycle Descriptions The write cycle description t able for CY7C1 320CV18 follows. [2, 8] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments LLLL L – H – D u r i n g t h e d a t a p o r t i o n o f a w r i t e s e quence, all fou r bytes (D [35:0] ) are written into the device. LL ...
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Cypress 001-07160 - page 10
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 10 of 26 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149.1 -2001. The T AP operates using JEDEC standard 1.8V I/O logic leve ls. Disabling t ...
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Cypress 001-07160 - page 11
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 1 1 of 26 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also places the instruction re gister between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the Shift-DR state. The IDCODE ...
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Cypress 001-07160 - page 12
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 12 of 26 T AP Controller St ate Diag ram The state diagram for the T AP controller follows. [9] TEST -LOGIC RESET TEST -LOGIC / IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR-S ...
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Cypress 001-07160 - page 13
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 13 of 26 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1 , 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 μ A1 . 6 V V OL1 Output LO ...
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Cypress 001-07160 - page 14
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 14 of 26 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Setup to TCK Clock Rise 5 ns t ...
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Cypress 001-07160 - page 15
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 15 of 26 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1318CV18 CY7C1320CV18 Revision Number (31:2 9) 0 00 000 V ersion nu mber . Cy p r e ss D e vi c e ID ( 2 8: 1 2 ) 1 10101000100101 01 1 1010100010100101 D ef i n e s t h e ty p e of S R AM . Cy ...
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Cypress 001-07160 - page 16
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 16 of 26 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6 P2 9 9 G 5 7 5 B8 5 3 K 2 6N 30 1 1F 58 5A 86 3J 3 7P 31 1 1G 59 4A 87 2K 4 7 N3 2 9 F 6 0 5 C8 8 1 K 5 7R 33 10F 61 4B 89 2L 6 8R 34 1 1E 62 3A 90 3L 7 8P 35 10E 63 1H 9 ...
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Cypress 001-07160 - page 17
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 17 of 26 Power Up Sequence in DDR II SRAM DDR II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operation s. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (all other inputs can be HIGH or LOW). ❐ Apply V DD before V DDQ ...
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Cypress 001-07160 - page 18
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 18 of 26 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature .................. ............... –65°C to +150°C Ambient T emp erature with Powe r Applied.. –55°C to +125°C Supply V ...
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Cypress 001-07160 - page 19
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 19 of 26 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs S tatic 267 MHz (x18) 315 mA (x36) 330 250 MHz (x18) 300 (x36) 320 200 MHz (x18) 290 (x36) 300 167 MHz (x18) 285 (x36) 295 AC Electrical Characte ...
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Cypress 001-07160 - page 20
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 20 of 26 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consorti um Parameter Description 267 MHz 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [22] 1–1–1–1– m s t CYC t KHKH K Clock an ...
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Cypress 001-07160 - page 21
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 21 of 26 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V ali d – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.45 – –0.45 – –0.45 – –0.50 – ns t CCQO t CHCQV C/C ...
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Cypress 001-07160 - page 22
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 22 of 26 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [26, 27, 28] READ READ READ NOP NOP WRITE WRITE NOP 1 23 4 56 7 8 9 1 0 Q40 t KHCH t CO t t HC t t HA t SD t HD t KHCH t SD t HD DON’ T CARE UNDEFINED t CLZ t DOH t CHZ SC t KH t KHKH t KL t CY C A0 D20 D21 D30 D ...
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Cypress 001-07160 - page 23
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 23 of 26 Ordering Information The table below contains only the parts that are currently available. If you don’t se e what you are looking for , please contact your local sales representative. For more information, visit the Cypress website at www .cypress.com and refer to the pro ...
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Cypress 001-07160 - page 24
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 24 of 26 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 51-85180-*B A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.08 M C B A 0.15(4X) 0.35±0.06 SEA TING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 ...
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Cypress 001-07160 - page 25
CY7C1318CV18 CY7C1320CV18 Document Number: 001-07160 Rev . *F Page 25 of 26 Document History Page Document Title: CY7C1318CV18/CY7C1320CV18, 18 -Mbit DDR II SRAM 2-Word Burst Architecture Document Number: 001-07160 Rev . ECN No. Submission Date Orig. o f Change Description of Chan ge ** 433284 See ECN NXR New data sheet *A 462615 See ECN NXR Change ...
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Cypress 001-07160 - page 26
Document Number: 001-07160 Rev . *F Revised August 24, 2009 Page 26 of 26 QDR RAMs an d Quad Data R ate RAMs comprise a new family o f products deve loped by Cypress, I DT , NEC, Renesas, and Samsung. All pr oduct and comp any names m entioned in this document are the tr ademark s of their re specti ve holders . CY7C1318CV18 CY7C1320CV18 © Cypress ...
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