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Manual Samsung S3C84E5

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  • Samsung S3C84E5 - page 1

    USER'S MANUAL ERRATA This document contains the corrections of errors, typos and omissions in the following document. Samsung 8 - bit CMOS S3C84E5/C84E9/P84E9 Microprocessor User's Manual Document Number: 21 .1 - S3 - C84E5/C84E9/P84E9 - 082005 Publicat ion: August 2005 ...

  • Samsung S3C84E5 - page 2

    S3C84E5/C84E9/P84E9 USER’S MA NUA L ERRA TA 1 ERRATA ( VER 1.1) Samsung 8-bit CMOS S3C84E5/C84E9/P 84E9 Microprocessor User’s Manual Document Number: 21.1- S3-C84E5/C84E9/P84E9-082005 Publication: August 2005 1. Features (PAGE 1-2) Built-in RESET circuit (LVR) • Low-Voltage reset (LVR value: 2.9 V) Operating Voltage Range • V LVR to 5.5V 2. ...

  • Samsung S3C84E5 - page 3

    USER’S MANUA L ERRA TA S3C84E5/C84E9/P84E9 2 3. Low Voltage Reset (PAGE 16-2) + - V REF BGR V DD V REF V IN VDD Longger than 1us N.F Internal System RESET W hen the V DD level is lower than 2.9V Comparator NOTES: 1. The target of voltage detection level is 2.9 V at VDD = 5 V 2. BGR is Band Gap voltage R eference Longger than 1us N.F nRESET W atch ...

  • Samsung S3C84E5 - page 4

    S3C84E5/C84E9/P84E9 USER’S MANUA L ERRA TA 3 4. Table 17-3. D.C. Electrical Characteristics (PAGE 17-3) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Ty p. Max Unit Input high voltage V IH1 V DD = V LVR to 5.5 V All port and nRESET 0.8 V DD – V DD V V IH2 V DD = V LVR (to 5.5 V X IN and XT IN V DD – 0 ...

  • Samsung S3C84E5 - page 5

    USER’S MANUA L ERRA TA S3C84E5/C84E9/P84E9 4 5. Table 17-3. D.C. Electri cal Characteristics (PAGE 17-4) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Typ. Max Unit Pull-up resistor R P1 V DD = 5 V; V IN = 0 V , T A = 25 ° C All I/O pins except nRESET 10 50 100 k Ω V DD = 3 V; V IN = 0 V, T A = 25 ° C ...

  • Samsung S3C84E5 - page 6

    S3C84E5/C84E9/P84E9 USER’S MANUA L ERRA TA 5 6. Table 17-4. A.C. Electri cal Characteristics (PAGE 17-5) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) 7. Table 17-5. Main Oscillator Frequency (PAGE 17-6) (T A = – 25 ° C + 85 ° C, V DD = V LVR to 5.5 V) Oscillator Clock Circuit Test Condition Min Typ. Max Unit Main crystal or ceramic ...

  • Samsung S3C84E5 - page 7

    USER’S MANUA L ERRA TA S3C84E5/C84E9/P84E9 6 10. Table 17-8. Subsystem Oscillator (c ry stal) Stabilization Time (PAGE 17-7) (T A = 25 ° C) Oscillator Test Condition Min Typ. Max Unit Normal mode V DD = 4.5 V to 5.5 V – 800 1600 ms V DD = V LVR to 3.3 V – 10 s Strong mode V DD = 4.5 V to 5.5 V – 400 800 ms V DD = V LVR to 3.3 V – 150 300 ...

  • Samsung S3C84E5 - page 8

    S3C84E5/C84E9/P84E9 USER’S MANUA L ERRA TA 7 13. Table 17-11. A/D Converter Elect rical Characteristics (PAGE 17-11) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V, V SS = 0 V) 14. Table 17-12. LVR (Low Voltage Rese t) Circuit Characteristics (PAGE 17-12) (T A = 25 ° C) Parameter Symbol Test Condition Min Typ Max Unit LVR voltage level V ...

  • Samsung S3C84E5 - page 9

    S3C84E5/C84E9/P84E9 8 - BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1 .1 ...

  • Samsung S3C84E5 - page 10

    Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibi lity, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make chan ...

  • Samsung S3C84E5 - page 11

    S3C84E5/C84E9/P84E9 MICROCONTROLLER iii Preface The S3C84E5/C84E9/P84E9 Microcontroller User's Manual is designed for application designers and programmers who are using the S3C84E5/C84E9/P84E9 microcontr oller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains ...

  • Samsung S3C84E5 - page 12

    S3C84E5/C84E9/P84E9 MICROCONTROLLER v Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8 - SERIES Microcontrollers ............................................................................................................. 1 - 1 S3C84E5/C84E9/P84E9 Microcontroller ....................................................... ...

  • Samsung S3C84E5 - page 13

    vi S3C84E5/C84E9/P84E9 MICROCONTROLLER Table of Contents (Continued) Chapter 4 Control Registers Overview ............................................................................................................................................. 4 - 1 Chapter 5 Interrupt Structure Overview ......................................................... ...

  • Samsung S3C84E5 - page 14

    S3C84E5/C84E9/P84E9 MICROCONTROLLER vii Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview ............................................................................................................................................. 7 - 1 System Cl ock Circuit ............................................... ...

  • Samsung S3C84E5 - page 15

    viii S3C84E5/C84E9/P84E9 MICROCONTROLLER Table of Contents (Continued) Chapter 11 8 - bit Timer A/B 8 - Bit Timer A ....................................................................................................................................... 11 - 1 Overview .................................................................................. ...

  • Samsung S3C84E5 - page 16

    S3C84E5/C84E9/P84E9 MICROCONTROLLER ix Table of Contents (Continued) Chapter 15 8 - bit Analog - to - Digital Converter Overview ............................................................................................................................................. 15 - 1 Function Description ................................................... ...

  • Samsung S3C84E5 - page 17

    S3C84E5/C84E9/P84E9 MICROCONTROLLER xi List of Figures Figure Title Page Number Number 1 - 1 S3C84E5/C84E9/P84E9 Block Diagram ................................................................ 1 - 3 1 - 2 S3C84E5/C84E9/P84E9 Pin Assignment (44 - pin QFP) ........................................... 1 - 4 1 - 3 S3C84E5/C84E9/P84E9 Pin Assignment (42 - ...

  • Samsung S3C84E5 - page 18

    xii S3C84E5/C84E9/P84E9 MICROCONTROLLER List of Figures (Continued) Figure Title Page Number Number 5 - 1 S3C8 - Series Interrupt Types ................................................................................. 5 - 2 5 - 2 S3C84E5/C84E9/P84E9 Interrupt Structure ........................................................... 5 - 4 5 - 3 ROM Vect ...

  • Samsung S3C84E5 - page 19

    S3C84E5/C84E9/P84E9 MICROCONTROLLER xiii List of Figures (Concluded) Page Title Page Number Number 12 - 1 Timer 1(0,1) Cont rol Register (T1CON0, T1CON1) ................................................... 12 - 4 12 - 2 Timer A, Timer 1(0,1) Pending Register (TINTPND) ................................................. 12 - 5 12 - 3 Timer 1(0,1) Func ...

  • Samsung S3C84E5 - page 20

    S3C84E5/C84E9/P84E9 MICROCONTROLLER xv List of Tables Table Title Page Number Number 1 - 1 S3C84E5/C84E9/P84E9 Pin Descriptions .............................................................. 1 - 6 2 - 1 S3C84E5/C84E9/P84E9 Register Type Summary .................................................. 2 - 3 4 - 1 Set 1 Registers .......................... ...

  • Samsung S3C84E5 - page 21

    xvi S3C84E5/C84E9/P84E9 MICROCONTROLLER List of Tables (Continued) Table Title Page Number Number 19 - 1 Descriptions of Pins Used to Read/Writ e the OTP .................................................. 19 - 3 19 - 2 Comparison of S3P84E9 and S3C84E5/C84E9 Features ......................................... 19 - 3 19 - 3 Operating Mode Selection C ...

  • Samsung S3C84E5 - page 22

    S3C84E5/C84E9/P84E9 MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapter 2: Address Spaces Using the Page Pointer for RAM clear (Page 0, Page 1) .......................................................................... 2 - 6 Setting the Register Pointers ..................................................................... ...

  • Samsung S3C84E5 - page 23

    S3C84E5/C84E9/P84E9 MICROCONTROLLER xix List of Register Desc riptions Register Full Register Name Page Identifier Number ADCON A/D Converter Control Register F7H Set 1, Bank 0 ................................................. 4 - 5 BTCON Basic Timer Control Register H Set 1 .................................................................... 4 - 6 ...

  • Samsung S3C84E5 - page 24

    S3C84E5/C84E9/P84E9 MICROCONTROLLER xxi List of Instruction Descriptions Instruction Full Register Name P age Mnemonic Number ADC Add with Carry .................................................................................................... 6 - 14 ADD Add ......................................................................................... ...

  • Samsung S3C84E5 - page 25

    xxii S3C84E5/C84E9/P84E9 MICROCONTROLLER List of Instruction Descriptions (Continued) Instruction Full Register Name Page Mnemonic Nu mber LDC/LDE Load Memory ...................................................................................................... 6 - 52 LDC/LDE Load Memory ............................................................. ...

  • Samsung S3C84E5 - page 26

    S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8-series of 8-bit single-chip CMOS microc ontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programm able ROM sizes. The major CPU features are: — Efficient register-oriented architecture ? ...

  • Samsung S3C84E5 - page 27

    PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-2 FEATURES CPU • SAM88RC CPU core Memory • 528-bytes internal register file • 16K/32Kbytes internal program memory (S3C84E5/C84E9:Mask ROM) (S3P84E9:OTP) Oscillation Sources • Main clock oscillator (Crystal, Ceramic) • CPU clock divider (1/1, 1/2, 1/8, 1/16) • 32,768Hz Sub oscillator for watch tim ...

  • Samsung S3C84E5 - page 28

    S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM ADC0~ ADC7/ P3. 0~P3. 7 I/O P o rt a n d In te rru p t C o n tro l SAM 88RC CPU 16K/32K-Byt e ROM 528-Byt e RAM OSC/nRESET 8-Bi t Basic Ti m er 8- Bi t Ti mer / Count er A, B 16-Bi t Ti mer / Count er 10, 11 Por t 0 Por t 1 Por t 2 P2.0~P2.7/ IN T0 ~IN T7 Xi n, XTi n Xout , XTout nRESET P1. 0 / ...

  • Samsung S3C84E5 - page 29

    PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-4 PIN ASSIGNMENT TBPWM/ P4. 3 INT10/ P4.2 VDD VSS Xout Xin TEST S3C84E5 S3C84E9 S3P84E9 Top View (44-QFP) 1 2 3 4 5 6 7 8 9 10 11 P4.4 P0.2/T1CAP1 P0.3/T1CK1 P0.4/T1OUT 1 P0.5/T1CAP0 P0.6/TACK P0.7/TACAP P1.0/TAOUT P1.1/T1CK0 44 43 42 41 40 39 38 37 36 35 34 P4.5 AVref 12 13 14 15 16 17 18 19 20 21 22 33 32 3 ...

  • Samsung S3C84E5 - page 30

    S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-5 PIN ASSIGNMENT TACAP/P0.7 TACK/P0.6 T1CAP0/P0.5 T1OUT1/P0.4 T1CK1/P0.3 T1CAP1/P0.2 XTout/ P0.1 XTin/ P0.0 TBPWM/P4.3 INT10/P4. 2 VDD VSS Xout Xin TEST INT9/P4.1 INT8/P4.0 nRESET INT0/P2.0 INT1/P2 .1 INT2/P2.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 P1.0/T AOUT P1.1/T 1CK0 P1.2/T 1OUT0 P1.3/B ZO ...

  • Samsung S3C84E5 - page 31

    PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-6 PIN DESCRIPTIONS Table 1-1. S3C84E5/C84E 9/P84E9 Pin Descriptions Pin Name Pin Type Pin Description Circuit Type Pin Number Share Pins P0.0–P0.7 I/O Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up resistor. Alternately, can be used a ...

  • Samsung S3C84E5 - page 32

    S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-7 Table 1-1. S3C84E5/C84E9/P84E 9 Pin Descriptions (Continued) Pin Name Pin Type Pin Description Circuit Type Pin Number Share Pins INT0–INT10 I Input pins for external interrupt. Alternatively used as general-purpose digital input/output port 2,4. D-1 13-20, 4 10-11 (19-26) (10,16-17) P2.0–P2.7 P4.0–P4. ...

  • Samsung S3C84E5 - page 33

    PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-8 PIN CIRCUITS Schmitt Trigger In V DD Pull-Up Resistor Figure 1-4. Pin Circuit Type B (nRESET) P-Channel N-Channel V DD Out Output Disable Data Figure 1-5. Pin Circuit Type C ...

  • Samsung S3C84E5 - page 34

    S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-9 I/O Output Disa ble Data Pin Circuit Type C Pull-up Enable V DD Figure 1-6. Pin Circuit Type D (P0.2-P0.7, P1, P4.3–P4.5) I/O Output Disa ble Data Pin Circuit Typ e C Pull-up Enable V DD Nois e Filter Ext.INT Input Normal V DD Figure 1-7. Pin Circuit Type D-1 (P2, and P4.0–P4.2) ...

  • Samsung S3C84E5 - page 35

    PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-10 V DD Pull-up Resistor (Typical Value: 47k Ω ) V DD Pull-up Enable Data Normal Input Output DIsable In/Out Analog Input Figure 1-8. Pin Circuit Type E (P3) V DD I/O Digital Input P-CH V DD Pull-up enable Output Disable (Input Mode) N-CH Alternative I/O Enable XTin, XTout Oscillation circuit Output Data Fi ...

  • Samsung S3C84E5 - page 36

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 1 2 ADDRESS SPACES OVERVIEW The S3C84E5/C84E9/P84E9 microcontroller has two types of address space: — Internal program memory (ROM) — Internal register file (RAM) A 16 - bit address bus supports program memory operations. A separate 8 - bit register bus carries addresses and data between the CPU and the re ...

  • Samsung S3C84E5 - page 37

    ADDRESS SPACES S3C8 4E5/C84E9/P84E9 2 - 2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S 3C84E5/84E9 has 16Kbytes and 32Kbytes of internal mask programmable program memory. The program memory address range is therefore 0H – 3FFFH and 0H - 7FFFH (see Figure 2 - 1). The first 256 bytes of the ROM (0H - 0FFH) are ...

  • Samsung S3C84E5 - page 38

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 3 REGISTER ARCHITECTUR E In the S3C84E5/C84E9/P84E9 implementation, the upper 64 - byte area of register files is expanded two 64 - byte areas, called set 1 and set 2 . The upper 32 - byte area of set 1 is further expanded two 32 - byte register banks (bank 0 and bank 1), and the lower 32 - byte area is a sing ...

  • Samsung S3C84E5 - page 39

    ADDRESS SPACES S3C8 4E5/C84E9/P84E9 2 - 4 Bank 1 FFH E0H 32 Bytes E0H DFH D0H CFH C0H 64 Bytes System and Peripheral Control Registers (Register Addressing Mode) System and Peripheral Control Registers (Register Addressing Mode) General Purpose Register (Register Addressing Mode) Set1 Bank 0 Page 0 Page 0 Page 0 Page 0 Page 0 Page 0 Page 0 Page 1 P ...

  • Samsung S3C84E5 - page 40

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 5 REGISTER PAGE POINTE R (PP) The S3C8 - series architecture supports the logical expansion of the physical 512 - byte internal register file (using an 8 - bit data bus) into as many as 2 separately addressa ble register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C84E ...

  • Samsung S3C84E5 - page 41

    ADDRESS SPACES S3C8 4E5/C84E9/P84E9 2 - 6 F PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1) LD PP,#00H ; Destination ← 0, Source ← 0 SRP #0C0H LD R0,#0FFH ; Page 0 RAM clear starts RAMCL0: CLR @R0 DJNZ R0,RAMCL0 CLR @R0 ; R0 = 00H LD PP,#10H ; Destination ← 1, Source ← 0 LD R0,#0FFH ; Page 1 RAM clear starts RAMCL1 ...

  • Samsung S3C84E5 - page 42

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 7 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H – FFH. The upper 32 - byte area of this 64 - byte space (E0H – FFH) is expanded two 32 - byte register banks, bank 0 and bank 1 . The set register bank ins tructions, SB0 or SB1, are used to address one bank or ...

  • Samsung S3C84E5 - page 43

    ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 8 PRIME REGISTER SPACE The lower 192 bytes (00H – BFH) of the S3C84E5/C84E9/P84E9's two 256 - byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is i ...

  • Samsung S3C84E5 - page 44

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 9 WORKING REGISTERS Instructions can access specif ic 8 - bit registers or 16 - bit register pairs using either 4 - bit or 8 - bit address fields. When 4 - bit working register addressing is used, the 256 - byte register file can be seen by the programmer as one that consists of 32 8 - byte register groups or ...

  • Samsung S3C84E5 - page 45

    ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 10 USING THE REGISTER P OINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1 , are used to select two movable 8 - byte working register slices in the register file. After a reset, RP# point to the working register common area: RP0 points to addresses C0H – C7H, and RP1 points to ...

  • Samsung S3C84E5 - page 46

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 11 16-byte Non- contiguous working register block Register File Contains 32 8-Byte Slices 8-Byte Slice 0H (R8) 7H (R15) F0H (R0) F7H (R7) RP1 RP0 1 1 1 1 0 X X X 0 0 0 0 0 X X X 8-Byte Slice Figure 2 - 7. Non - Contiguous 16 - Byte Working Register Block F PROGRAMMING TIP — Using the RPs to Calculate the Sum ...

  • Samsung S3C84E5 - page 47

    ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 12 REGISTER ADDRESSING The S3C8 - series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or ...

  • Samsung S3C84E5 - page 48

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 13 RP1 RP0 Register Pointers 00H All Addressing Modes Page 0-1 Indirect Register, Indexed Addressing Modes Page 0-1 Register Addressing Only Can be pointed by Register Pointer FFH E0H BFH Control Registers System Registers Special-Purpose Registers D0H C0H Bank 1 Bank 0 NOTE: In the S3C84E5/C84E9/P84E9 microco ...

  • Samsung S3C84E5 - page 49

    ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 14 COMMON WORKING REGIS TER AREA (C0H – CFH) After a reset, register pointers RP0 and RP1 automatically select two 8 - byte register slices in set 1, locations C0H – CFH, as the active 16 - byte wor king register block: RP0 → C0H – C7H RP1 → C8H – CFH This 16 - byte address range is called common ...

  • Samsung S3C84E5 - page 50

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 15 F PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access wo rking registers in the common area, locations C0H – CFH, using working register addressing mode only. Examples 1: 1. LD 0C2H,40H ; Invalid addressing mode! Use working register addressing ...

  • Samsung S3C84E5 - page 51

    ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 16 Together they create an 8-bit register address Register pointer provides five high-order bits Address OPCODE Selects RP0 or RP1 RP1 RP0 4-bit address provides three low-order bits Figure 2 - 11. 4 - Bit Working Register Addressing Register address (76H) RP0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 R6 0 1 1 0 1 1 1 ...

  • Samsung S3C84E5 - page 52

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 17 8 - BIT WORKING REGIST ER ADDRESSING You can also use 8 - bit working register addressing to access registers in a selected working register area. To initiate 8 - bit working regi ster addressing, the upper four bits of the instruction address must contain the value "1100B." This 4 - bit value (11 ...

  • Samsung S3C84E5 - page 53

    ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 18 8-bit address form instruction 'LD R11, R2' RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address (0ABH) RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2 - 14. 8 - Bit Working Register Addressing Example ...

  • Samsung S3C84E5 - page 54

    S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 19 SYSTEM AND USER STACK The S3C8 - series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C84E5/C84E9/P84E architecture supports stack operations in th e internal register file. Stack Operati ...

  • Samsung S3C84E5 - page 55

    ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 20 F PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH ; SPL ← FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine) • • • PUSH ...

  • Samsung S3C84E5 - page 56

    S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operate d on. Addressing mode is the method used to determine the location of the data operand. The operands ...

  • Samsung S3C84E5 - page 57

    ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 2 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figur e 3 - 1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 - byte working register space in the ...

  • Samsung S3C84E5 - page 58

    S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 3 INDIRECT REGISTER AD DRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a registe r in the register file, to program memory (ROM), or to an ext ...

  • Samsung S3C84E5 - page 59

    ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 4 INDIRECT REGISTER AD DRESSING MODE (C ontinued ) dst OPCODE PAIR Points to Register Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16-Bit Address Points to Program Memory Figur ...

  • Samsung S3C84E5 - page 60

    S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 5 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE ADDRESS 4-bit Working Register Address Point to the Working Register (1 of 8) Sample Instruction: OR R3, @R6 Program Memory Register File src 3 LSBs Value used in Instruction OPERAND Selected RP points to start fo working register block RP0 or RP1 ...

  • Samsung S3C84E5 - page 61

    ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 6 INDIRECT REGISTER AD DRESSING MODE (C ontinued ) dst OPCODE 4-bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program memory access LDE R3,@RR14 ; External data memory access LDE @RR4, R8 ; External data memory access Program Memory Register File src Value used in Instruction OPERAND Examp ...

  • Samsung S3C84E5 - page 62

    S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 7 INDEXED ADDRESSING M ODE (X) Inde xed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3 - 7). You can use Indexed addressing mode to access locations in the internal register file or in ex ternal memory. ...

  • Samsung S3C84E5 - page 63

    ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 8 INDEXED ADDRESSING M ODE (C ontinued ) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair (1 of 4) LSB Selects 16-Bit address added to offset RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block dst/src OPCODE Program Memory x OFFSET 4-b ...

  • Samsung S3C84E5 - page 64

    S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 9 INDEXED ADDRESSING M ODE (C ontinued ) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair LSB Selects 16-Bit address added to offset RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Sample Instructions: LDC R4, #1000H[RR2] ; The value ...

  • Samsung S3C84E5 - page 65

    ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16 - bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16 - bit destination address that is loaded into the PC whenever a JP or CALL i nstruction is executed. ...

  • Samsung S3C84E5 - page 66

    S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 11 DIRECT ADDRESS MODE (C ontinued ) OPCODE Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3 - 11. Direct Addressing for Call and J ...

  • Samsung S3C84E5 - page 67

    ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 12 INDIRECT ADDRESS MOD E (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memor y. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect ...

  • Samsung S3C84E5 - page 68

    S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 13 RELATIVE ADDRESS MOD E (RA) In Relative Address (RA) mode, a twos - complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition ...

  • Samsung S3C84E5 - page 69

    ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate ad dressing mode is useful for loading constant values into r ...

  • Samsung S3C84E5 - page 70

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 1 4 CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual. The locations and read/writ ...

  • Samsung S3C84E5 - page 71

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 2 Table 4 - 2. Set 1, Bank 0 Registers Register Name Mnemonic Decimal Hex R/W Port 0 data register P0 224 E0H R/W Port 1 data register P1 225 E1H R/W Port 2 data register P2 226 E2H R/W Port 3 data register P3 227 E3H R/W Port 4 data register P4 228 E4 H R/W STOP control register STPCON 229 E5H R/W Port 0 ...

  • Samsung S3C84E5 - page 72

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 3 Table 4 - 3. Set 1, Bank 1 Registers Register Name Mnemonic Decimal Hex R/W Timer A, Timer 1 interrupt pending register TINTPND 224 E0H R/W Timer A control register TACON 225 E1H R/W Timer A data register TADATA 226 E2H R/W Timer A counter register TACNT 227 E3H R Timer 1(0) data register (High Byte) T1DAT ...

  • Samsung S3C84E5 - page 73

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 4 FLAGS - System Flags Register .7 Carry Flag (C) .6 Zero Flag (Z) .5 Bit Identifier RESET Value Read/Write Bit Addressing Mode R = Read-only W = Write-only R/W = Read/write '-' = Not used Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) RESET value notation: &apos ...

  • Samsung S3C84E5 - page 74

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 5 ADCON — A/D Converter Control Register F7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 R ead/Write – R/W R/W R/W R R/W R/W R/W Addressing Mode Register addressing mode only .7 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0) .6 – .4 A/D Input Pin Selectio ...

  • Samsung S3C84E5 - page 75

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 6 BTCON — Basic Timer Control Register D3 H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register address ing mode only .7 – .4 Watchdog Timer Function Disable Code (for System Reset) 1 0 1 0 Disable watchdog timer f ...

  • Samsung S3C84E5 - page 76

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 7 CLKCON — System Clock Control Register D4H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – R/W R/W – – – Addressing Mode Register addressing mode only .7 – .5 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0) .4 – .3 CPU Clock (System Cloc ...

  • Samsung S3C84E5 - page 77

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 8 FLAGS — System Flags Register D5H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .7 Carry Flag (C) 0 Operation does not generate a carry or underflow condition 1 Operation generates a carry ...

  • Samsung S3C84E5 - page 78

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 9 IMR — Interrupt Mask Register DDH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Interrupt Level 7 (IRQ7) Enab le Bit 0 Disable (mask) 1 Enable (un - mask) .6 Interrupt Level 6 (IRQ6) Ena ...

  • Samsung S3C84E5 - page 79

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 10 IPH — Instr uction Pointer (High Byte) DAH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .0 Instruction Pointer Address (High Byte) The high - byte instruction pointer value is th ...

  • Samsung S3C84E5 - page 80

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 11 IPR — Interrupt Priority Register FFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C 0 0 0 Group priority undef ...

  • Samsung S3C84E5 - page 81

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 12 IRQ — Interrupt Request Register DCH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Interrupt L evel 7 (IRQ7) Request Pending Bit 0 Not pending 1 Pending .6 Interrupt Level 6 (IRQ6) Request Pending Bi ...

  • Samsung S3C84E5 - page 82

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 13 OSCCON — Oscillator Control Register FBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – R/W R/W R/W – R/W Addressing Mode Register addressing mode only .7 – .5 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0) .4 Sub - system Oscillato ...

  • Samsung S3C84E5 - page 83

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 14 P0CONH — Port 0 Control Register (High Byte) E6H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 P0.7/TACAP Configuration Bits 0 0 Input mode with pull - up; TACAP input ...

  • Samsung S3C84E5 - page 84

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 15 P0CONL — Port 0 Control Register (Low Byte) E7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 1 .0 Reset Value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 P0.3/T1CK1 Configuration Bits 0 0 Input mode with pull - up; T1CK1 input 0 1 ...

  • Samsung S3C84E5 - page 85

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 16 P1CONH — Port 1 Control Re gister (High Byte) E8H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .4 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0) .3 – .2 P1.5 ...

  • Samsung S3C84E5 - page 86

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 17 P1CONL — Port 1 Control Register (Low Byte) E9H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 P1.3/BZOUT Configuration Bits 0 0 Input mode with pull - up 0 1 Input mode 1 ...

  • Samsung S3C84E5 - page 87

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 18 P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 . 3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 P2.7/INT7 0 0 Input mode with pull - up; falling edge interrupt (INT7) 0 ...

  • Samsung S3C84E5 - page 88

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 19 P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 P2.3/INT3 0 0 Input mode with pull - up; falling edge interrupt (INT3) 0 1 I ...

  • Samsung S3C84E5 - page 89

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 20 P2INT — Port 2 Interrupt Control Register ECH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P2.7 External Interrupt (INT7) Enable Bit 0 Disable interrupt 1 Enable interrupt .6 ...

  • Samsung S3C84E5 - page 90

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 21 P2INTPND — Port 2 Interrupt Pending Register EDH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Wr ite R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P2.7/PND7 Interrupt Pending Bit 0 Interrupt request is not pending, pending bit c ...

  • Samsung S3C84E5 - page 91

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 22 P3CONH — Port 3 Control Register (High Byte) EEH Set 1, Bank 0 Bit Identifi er .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 P3.7/ADC7 0 0 Input mode with pull - up 0 1 Input mode 1 0 Push - pull o ...

  • Samsung S3C84E5 - page 92

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 23 P3CONL — Port 3 Control Register (Low Byte) EFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 P3.3/ADC3 0 0 Input mode with pull - up 0 1 Input mode 1 0 Push - pull outpu ...

  • Samsung S3C84E5 - page 93

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 24 P4CONH — Port 4 Control Register (High Byte) F0H Set 1, Ba nk 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .4 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0) .3 – .2 P4.5 ...

  • Samsung S3C84E5 - page 94

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 25 P4CONL — Port 4 Control Register (Low Byte) F1H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 P4.3/TBPWM 0 0 Input mode with pull - up 0 1 Input mode 1 0 Push - pull outp ...

  • Samsung S3C84E5 - page 95

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 26 P4INT — Port 4 Interrupt Control Register F2H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – – – R/W R/W R/W Addressing Mode Register addressing mode only .7 – .3 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0) .2 P4.2 External I ...

  • Samsung S3C84E5 - page 96

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 27 P4INTPND — Port 4 Interrupt Pending Register F3H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write – – – – – R/W R/W R/W Addressing Mode Register addressing mode only .7 – .3 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0) .2 P4.2/PND10 In ...

  • Samsung S3C84E5 - page 97

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 28 PP — Register Page Pointer DFH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register add ressing mode only .7 – .4 Destination Register Page Selection Bits 0 0 0 0 Destination: page 0 0 0 0 1 Destination: page 1 O ...

  • Samsung S3C84E5 - page 98

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 29 RP0 — Register Pointer 0 D6H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 1 1 0 0 0 – – – Read/Write R/W R/W R/W R/W R/W – – – Addressing Mode Register addressing only .7 – .3 Register Pointer 0 Address Value Register pointer 0 can independently point to one o f the 256 - byte ...

  • Samsung S3C84E5 - page 99

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 30 SPH — Stack Pointer (High Byte) D8H Se t 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .0 Stack Pointer Address (High Byte) The high - byte stack pointer value is the upper e ight bit ...

  • Samsung S3C84E5 - page 100

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 31 STPCON — Stop Control Register E5H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instr ...

  • Samsung S3C84E5 - page 101

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 32 SYM — System Mode Register DEH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 x x x 0 0 Read/Write – – – R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .5 Not used, But you must keep always 0 .4 – .2 Fast Interrupt Level Selection Bits 0 0 0 IRQ0 0 0 1 ...

  • Samsung S3C84E5 - page 102

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 33 T1CON0 — Timer 1(0) Control Register E8H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .5 Timer 1(0) Input Clock Selection Bits 0 0 0 fxx/1024 0 0 1 fxx/256 0 1 0 fxx/64 0 1 ...

  • Samsung S3C84E5 - page 103

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 34 T1CON1 — Timer 1(1) Control Register E9H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressin g Mode Register addressing mode only .7 – .5 Timer 1(1) Input Clock Selection Bits 0 0 0 fxx/1024 0 0 1 fxx/256 0 1 0 fxx/64 ...

  • Samsung S3C84E5 - page 104

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 35 TACON — Timer A Control Register E1H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 Timer A Input Clock Selection Bits 0 0 fxx/1024 0 1 fxx/256 1 0 fxx/64 1 1 External clo ...

  • Samsung S3C84E5 - page 105

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 36 TBCON — Timer B Control Register D0H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 . 0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 Timer B Input Clock Selection Bits 0 0 fxx/4 0 1 fxx/8 1 0 fxx/64 1 1 fxx/256 .5 – .4 Time ...

  • Samsung S3C84E5 - page 106

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 37 TINTPND — Timer A, Timer 1 Inte rrupt Pending Register E0H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 Not used for the S3C84E5/C84E9/P84E9 (must keep alw ays 0) .5 Tim ...

  • Samsung S3C84E5 - page 107

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 38 UARTCON — UART Control Register F6H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 – .6 Op erating Mode and Baud Rate Selection Bits 0 0 Mode 0: Shift Register [fxx/(16 × (16 - bit BRDATA + 1))] 0 1 Mode 1: 8 - bit UART ...

  • Samsung S3C84E5 - page 108

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 39 NOTES: 1. In mode 2, if the MCE (UARTCON.5) bit is set to "1", then the receive interrupt will not be activated if the received 9th data bit is "0". In mode 1, if MCE = "1”, then the receive interrupt will not be activated if a valid stop bit was not received. In mode 0, the MCE ...

  • Samsung S3C84E5 - page 109

    CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 40 UARTPND — UART Pending and parity contr ol F4H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – R/W R/W – – R/W R/W .7 – .6 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0) .5 UAR T Parity Enable/Disable (PEN) 0 Disable 1 Enable .4 UART ...

  • Samsung S3C84E5 - page 110

    S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 41 WTCON — Watch Timer Control Register FAH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .7 Watch Timer Clock Selection Bit 0 Main system clock divided by 256 (fxx/256) 1 Sub system ...

  • Samsung S3C84E5 - page 111

    S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 1 5 INTERRUPT STRUCTURE OVERVIEW The S3C8 - series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector prio ...

  • Samsung S3C84E5 - page 112

    INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 2 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt s ...

  • Samsung S3C84E5 - page 113

    S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 3 S3C84E5/C84E9/P84E9 INTERRUPT STRUCTURE The S3C84E5/C84E9/P84E9 microcontroller supports twenty - one interrupt s ources. All of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device - specific interrupt structure, as shown ...

  • Samsung S3C84E5 - page 114

    INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 4 Vectors Sources Levels Reset(Clear) Timer A match/capture IRQ1 Timer A overflow H/W, S/W H/W, S/W C0H C2H C4H C6H C8H CAH IRQ2 Timer 1(0) match/capture Timer 1(0) overflow Timer 1(1) match/capture Timer 1(1) overflow H/W, S/W H/W, S/W H/W, S/W H/W, S/W Timer B underflow BEH IRQ0 H/W IRQ3 Watch timer S/W ...

  • Samsung S3C84E5 - page 115

    S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 5 INTERRUPT VECTOR ADD RESSES All interrupt vector addresses for the S3C84E5/C84E9/P84E9 interrupt structure are stored in the vector address area of the internal 16/32 - Kbyte ROM, 0H – 3FFFH/0H – 7FFFH (see Figure 5 - 3). You can allocate unused locations in the vector address area as normal progra ...

  • Samsung S3C84E5 - page 116

    INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 6 Table 5 - 1. Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Value Hex Value Interrupt Level Priority in Level H/W S/W 256 100H Basic timer (WDT) overflow nRESET – √ 230 E6H UART transmit IRQ7 1 √ 228 E4H UART receive 0 √ 226 E2H P4.2 external interrupt IRQ6 2 √ 2 ...

  • Samsung S3C84E5 - page 117

    S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 7 ENABLE/DISABLE INTER RUPT INSTRUCTIONS (E I, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. NOTE The system initialization routine executed after a reset must always c ...

  • Samsung S3C84E5 - page 118

    INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 8 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system - level control points in the int errupt structure are: — Global interrupt enable and disable (by EI and DI instructions or by direct manipul ...

  • Samsung S3C84E5 - page 119

    S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 9 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5 - 3). Table 5 - 3. Interrupt Source Control and Data Registers Interrupt Source Interrupt ...

  • Samsung S3C84E5 - page 120

    INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 10 SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing (see Figure 5 - 5). A reset clears SYM.0 to "0". The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 v ...

  • Samsung S3C84E5 - page 121

    S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 11 INTERRUPT MASK REGIS TER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. E a ...

  • Samsung S3C84E5 - page 122

    INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 12 INTERRUPT PRIORITY R EGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required ...

  • Samsung S3C84E5 - page 123

    S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 13 Group A 0 = IRQ0 > IRQ1 1 = IRQ1 > IRQ0 Subgroup B 0 = IRQ3 > IRQ4 1 = IRQ4 > IRQ3 Group C 0 = IRQ5 > (IRQ6, IRQ7) 1 = (IRQ6, IRQ7) > IRQ5 Subgroup C 0 = IRQ6 > IRQ7 1 = IRQ7 > IRQ6 Group B 0 = IRQ2 > (IRQ3, IRQ4) 1 = (IRQ3, IRQ4) > IRQ2 Interrupt Priority Register (IPR) ...

  • Samsung S3C84E5 - page 124

    INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 14 INTERRUPT REQUEST RE GISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of t he same number: bit 0 to IRQ0, bit 1 to IRQ1 ...

  • Samsung S3C84E5 - page 125

    S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 15 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. Pending Bits Cleared Automatica ...

  • Samsung S3C84E5 - page 126

    INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 16 INTERRUPT SOURCE POL LING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3. The CPU checks the int ...

  • Samsung S3C84E5 - page 127

    S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 17 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H – FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low - byte val ...

  • Samsung S3C84E5 - page 128

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 1 6 INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3C8 - series microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instru ction set include: — A full complement of 8 - b ...

  • Samsung S3C84E5 - page 129

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 2 Table 6 - 1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDB dst,src Load bit LDE dst,src Load external data memory LDC dst,src Load program memory LDED dst,src Load externa l data memory and decrement LDCD dst,src Load program memory and decremen ...

  • Samsung S3C84E5 - page 130

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 3 Table 6 - 1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC dst,src Add with carry ADD dst,src Add CP dst,src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst,src Divide INC dst Increment INCW dst Increment word MULT dst,src Mul ...

  • Samsung S3C84E5 - page 131

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 4 Table 6 - 1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL dst Call procedure CPIJ E dst,src Compare, increment and jump on equal CPIJNE dst,src Compare ...

  • Samsung S3C84E5 - page 132

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 5 Table 6 - 1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complem ...

  • Samsung S3C84E5 - page 133

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 6 FLAGS REGISTER (FLAG S) The flags register FLAGS contains eight bits which describe the current status of CPU operations. Four of these bits, FLAGS.7 – FLAGS.4, can be tested and used with conditional jump instructions. Two other flag bits, FLAGS.3 and FLAGS.2, are used for BCD arithmetic. The FL AGS reg ...

  • Samsung S3C84E5 - page 134

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry - out from or a borrow to the bit 7 position (MSB). After rotate and shift operations have been perfo rmed, it contains the last value shifted out of the specified registe ...

  • Samsung S3C84E5 - page 135

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 8 INSTRUCTION SET NOTA TION Table 6 - 2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal - adjust flag H Half - carry flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined ...

  • Samsung S3C84E5 - page 136

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 9 Table 6 - 4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6 - 6. r Working register only Rn (n = 0 – 15) rb Bit (b) of working register Rn.b (n = 0 – 15, b = 0 – 7) r0 Bit 0 (LSB) of working register Rn (n = 0 – 15) ...

  • Samsung S3C84E5 - page 137

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 10 Table 6 - 5. OPCODE Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0 – Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.b, R2 P 2 INC R1 INC IR1 SUB r1,r2 SUB r1,Ir2 SUB R2,R1 S ...

  • Samsung S3C84E5 - page 138

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 11 Table 6 - 5. OPCODE Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC r1 NEXT P 1 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 ↓ ↓ ↓ ↓ ↓ ↓ ↓ STOP B 8 DI B 9 EI L A RET ...

  • Samsung S3C84E5 - page 139

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 12 CONDITION CODES The opcode of a conditional jump always contains a 4 - bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two op ...

  • Samsung S3C84E5 - page 140

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 13 INSTRUCTION DESCRIPT IONS This Chapter contains detailed information and programming examples for each instruction in the S3C8 - series instruction set. Information is arranged in a consistent format for improved readability and for quick reference. The following information is included in each instruction ...

  • Samsung S3C84E5 - page 141

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 14 ADC — Add with Carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the carry flag setting, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's - complement addition is performed. In multiple - p ...

  • Samsung S3C84E5 - page 142

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 15 ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaf fected. Two's - complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of ...

  • Samsung S3C84E5 - page 143

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 16 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation causes a "1" bit to be stored whenever the corresponding bits in the two operands are both logic ones; oth ...

  • Samsung S3C84E5 - page 144

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 17 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or the source). The resultant bit is stored in the specified bit of the ...

  • Samsung S3C84E5 - page 145

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Flags: ...

  • Samsung S3C84E5 - page 146

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 19 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bit in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undef ...

  • Samsung S3C84E5 - page 147

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 20 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 0 2 4 77 rb NOTE : In the secon d byte ...

  • Samsung S3C84E5 - page 148

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 1 2 4 77 rb NOTE: In the second byte of the ...

  • Samsung S3C84E5 - page 149

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 22 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the dest ...

  • Samsung S3C84E5 - page 150

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statem ent whose address i ...

  • Samsung S3C84E5 - page 151

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "1", t he relative address is added to the program counter and control passes to the statement whose address i ...

  • Samsung S3C84E5 - page 152

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive - ORed with bit zero (LSB) of the destination (or the source). The result bit is stored in the specified bit of ...

  • Samsung S3C84E5 - page 153

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 26 CALL — Call Procedure CALL dst Operation: SP ← SP –1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ← dst The contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destin ...

  • Samsung S3C84E5 - page 154

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 27 CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero. If C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Format: By ...

  • Samsung S3C84E5 - page 155

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 28 CLR — Clear CLR dst Operation : dst ← "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 B0 R 4 B1 IR Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR 00H → ...

  • Samsung S3C84E5 - page 156

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 29 COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement). All "1s" are changed to "0s", and vice - versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result b ...

  • Samsung S3C84E5 - page 157

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 30 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleare ...

  • Samsung S3C84E5 - page 158

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 31 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and cont ...

  • Samsung S3C84E5 - page 159

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 32 CPIJNE — Compare, Increment, and Jump on Non - Equal CPIJNE dst,src,RA Operation: If dst – src ¡ "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program co ...

  • Samsung S3C84E5 - page 160

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 33 DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4 - bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed (The operation is undefined if t ...

  • Samsung S3C84E5 - page 161

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 34 DA — Decimal Adjust DA (Continued) Example: Given: The working register R0 contains the value 15 (BCD), the working register R1 contains 27 (BCD), and the address 27H contains 46 (BCD): ADD R1,R0 ; C ← "0", H ← "0", Bits 4 – 7 = 3, bits 0 – 3 = C, R1 ← 3CH DA R1 ; R1 ← 3C ...

  • Samsung S3C84E5 - page 162

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 35 DEC — Decrement DEC dst Operation: dst ← dst –1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D ...

  • Samsung S3C84E5 - page 163

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16 - bit value that is decremented b y one. Flags: C: Unaffected. Z: Set if the result is "0"; cl ...

  • Samsung S3C84E5 - page 164

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while inter ...

  • Samsung S3C84E5 - page 165

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 38 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper ha ...

  • Samsung S3C84E5 - page 166

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 39 DJNZ — Decrement and Jump if Non - Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control pass ...

  • Samsung S3C84E5 - page 167

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 The EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have the highest priority). If an interrupt's pending bit was set while interrupt processing wa ...

  • Samsung S3C84E5 - page 168

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded - code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. ...

  • Samsung S3C84E5 - page 169

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded - code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded in ...

  • Samsung S3C84E5 - page 170

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 43 IDLE — Idle Operation IDLE Operation: (See description) The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: Byt es Cycles Opcode (Hex ...

  • Samsung S3C84E5 - page 171

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 44 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwis ...

  • Samsung S3C84E5 - page 172

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 45 INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16 - bit value that is incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. ...

  • Samsung S3C84E5 - page 173

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 46 IRET — Interrupt Return IRET IRET (Normal) RET (Fast) Operation: FLAGS ← @SP PC ↔ IP SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also ...

  • Samsung S3C84E5 - page 174

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 47 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true, otherwise, the instruction following the JP instruction is exe ...

  • Samsung S3C84E5 - page 175

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 48 JR — Jump Relative JR cc,dst Operat ion: If cc is true, PC ← PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter, otherwise, the instruction followin ...

  • Samsung S3C84E5 - page 176

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 49 LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src dst | opc src 2 4 rC r IM 4 r8 r R src | opc dst 2 4 r9 R r r = 0 to F opc d ...

  • Samsung S3C84E5 - page 177

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 50 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD R0,#10H → R0 = 10H LD R0,01H → R0 = 20H, register 01H = 20H LD 01H,R0 → Register 01H = 01H, R0 = 01H LD R1,@R0 → R1 = 20H, R0 = 01H LD ...

  • Samsung S3C84E5 - page 178

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 51 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The ...

  • Samsung S3C84E5 - page 179

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 52 LDC/LDE — Load Memory LDC dst,src LDE dst,src Operation: dst ← src This instruction l oads a byte from program or data memory into a working register or vice - versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr" or "rr& ...

  • Samsung S3C84E5 - page 180

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 53 LDC/LDE — Load Memory LDC/LDE (Continued) E xamples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC R0,@RR2 ; R0 ← contents of progr ...

  • Samsung S3C84E5 - page 181

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 54 LDCD/LDED — Load Memory and Decrement LDCD dst,src LDED dst,src Operation: dst ← src rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The ...

  • Samsung S3C84E5 - page 182

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 55 LDCI/LDEI — Load Memory and Increment LDCI dst,src LDEI dst,src Operation: dst ← src rr ← rr + 1 These instructions are used f or user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The co ...

  • Samsung S3C84E5 - page 183

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 56 LDCPD/LDEPD — Load Memory with Pre - Decrement LDCPD dst,src LDEPD dst,src Operation: rr ← rr – 1 dst ← src These instructions are used for block transfers of data from program or data memory to the register file. The addre ss of the memory location is specified by a working register pair and is f ...

  • Samsung S3C84E5 - page 184

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 57 LDCPI/LDEPI — Load Memo ry with Pre - Increment LDCPI dst,src LDEPI dst,src Operation: rr ← rr + 1 dst ← src These instructions are used for block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair and is firs ...

  • Samsung S3C84E5 - page 185

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 58 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst 3 8 C4 RR RR 8 C5 RR IR opc dst src 4 8 C6 RR I ...

  • Samsung S3C84E5 - page 186

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 59 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8 - bit d estination operand (the even numbered register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operand ...

  • Samsung S3C84E5 - page 187

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 60 NEXT — Next NEXT Operation: PC ← @IP IP ← IP + 2 The NEXT instruction is useful when implementing threaded - code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: No flags a ...

  • Samsung S3C84E5 - page 188

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 61 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to affect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 FF Example: When the instru ...

  • Samsung S3C84E5 - page 189

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 62 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever ei ther of the correspondin ...

  • Samsung S3C84E5 - page 190

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 63 POP — Pop from Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode d st opc dst 2 8 50 R 8 51 ...

  • Samsung S3C84E5 - page 191

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 64 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction is used for user - defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is th ...

  • Samsung S3C84E5 - page 192

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 65 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instruction is used for user - defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is ...

  • Samsung S3C84E5 - page 193

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 66 PUSH — Push to Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No fla ...

  • Samsung S3C84E5 - page 194

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 67 PU SHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instruction is used to address user - defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack ...

  • Samsung S3C84E5 - page 195

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 68 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instruction is used fo r user - defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented ...

  • Samsung S3C84E5 - page 196

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 69 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcod e (Hex) opc 1 4 CF Example: Given: C = "1" or "0": The instruction R ...

  • Samsung S3C84E5 - page 197

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 70 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next st ...

  • Samsung S3C84E5 - page 198

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 71 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0 –6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag, as shown in the figure b ...

  • Samsung S3C84E5 - page 199

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 72 RLC — Rotate Left through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0 –6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C), and the initial value of the carry fla ...

  • Samsung S3C84E5 - page 200

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 73 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0 –6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 0 C Flags: C: Set if th ...

  • Samsung S3C84E5 - page 201

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 74 RRC — Rotate Right through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1), n = 0 –6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag, and the initial value of the car ...

  • Samsung S3C84E5 - page 202

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 75 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0 ) to logic zero, selecting the bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 4F Exampl ...

  • Samsung S3C84E5 - page 203

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 76 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting the bank 1 register addressing in the set 1 area of the register file. NOTE: B ank 1 is not implemented in some KS88 - series microcontrollers. Flags: No f ...

  • Samsung S3C84E5 - page 204

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 77 SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by add ...

  • Samsung S3C84E5 - page 205

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 78 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags ar e affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to “1”. ...

  • Samsung S3C84E5 - page 206

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 79 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1), n = 0 –6 An arithmetic shift - right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is ...

  • Samsung S3C84E5 - page 207

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 80 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 the n: RP0 (3 – 7) ← src (3 – 7) If src (1) = 0 and src (0) = 1 then: RP1 (3 – 7) ← src (3 – 7) If src (1) = 0 and src (0) = 0 then: RP0 (4 – 7) ← src (4 – 7), RP0 (3) ← 0 RP1 (4 ...

  • Samsung S3C84E5 - page 208

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 81 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on - chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can ...

  • Samsung S3C84E5 - page 209

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 82 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source oper and to the desti ...

  • Samsung S3C84E5 - page 210

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 83 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and the upper four bits of the destination operand are swapped. 7 0 4 3 Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared oth ...

  • Samsung S3C84E5 - page 211

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 84 TCM — Test Complement under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested a re specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM stateme ...

  • Samsung S3C84E5 - page 212

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 85 TM — Test under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination ...

  • Samsung S3C84E5 - page 213

    INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 86 WFI — Wate for Interrupt WFI Operation: The CPU is effectively halted before an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrup t. Flags: No flags are affected. Format: Bytes Cycle ...

  • Samsung S3C84E5 - page 214

    S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 87 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logically exclusive - ORed with the destination operand and the result is stored in the destination. The exclusive - OR operation results i n a "1" bit being stored whenever the corresponding bits in the ...

  • Samsung S3C84E5 - page 215

    S3C84E5/C84E9/P84E9 CLOCK CIRCUIT 7 - 1 7 CLOCK CI RCUIT OVERVIEW The clock frequency generated for the Main clock of S3C84E5/C84E9/P84E9 by an external crystal can range from 1 MHz to 12 MHz. The maximum CPU clock frequency is 12 MHz. The X IN and X OUT pins connect the external oscillator or clo ck source to the on - chip clock circuit. Also the ...

  • Samsung S3C84E5 - page 216

    CLOCK CIRCUIT S3C84 E5/C84E9/P84E9 7 - 2 CLOCK STATUS DURING POWER - DOWN MODES The t wo power - down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with RC delay noise filter), a ...

  • Samsung S3C84E5 - page 217

    S3C84E5/C84E9/P84E9 (REV.0) CLOCK CIRCU IT 7 - 3 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and has the following functions: — Oscillator frequency divide - by value After the main oscillator is activated, and the fxx/16 (the slowest clock speed) ...

  • Samsung S3C84E5 - page 218

    CLOCK CIRCUIT S3C84 E5/C84E9/P84E9 7 - 4 Oscillator Control Register (OSCCON) FBH, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used (must keep always 0) System clock selection bit: 0 = Main oscillator select 1 = Subsystem oscillator select Not used (must keep always 0) Subsystem oscillator control bit: 0 = Subsystem oscillator RUN 1 = Su ...

  • Samsung S3C84E5 - page 219

    S3C84E5/C84E9/P84E9 RESET and POWER - DOWN 8 - 1 8 RESET and POWER - DOWN SYSTEM RESET OVERVIEW During a power - on Reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C84E5/C84E9 ...

  • Samsung S3C84E5 - page 220

    RESET and POWER - DOWN S3C84E5 /C84E9/P84E9 8 - 2 HARDWARE RESET VALUE S Table 8 - 1, 8 - 2, and 8 - 3 list the re set values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows th ...

  • Samsung S3C84E5 - page 221

    S3C84E5/C84E9/P84E9 RESET and POWER - DOWN 8 - 3 Table 8 - 2. S3C84E5/C84E9/P84E9 Set 1, Bank 0 Register Values After RESET Register Name Mnemonic Address Bit Values After RESET Dec Hex 7 6 5 4 3 2 1 0 Port 0 data register P0 224 E0H 0 0 0 0 0 0 0 0 Port 1 data register P1 225 E1H 0 0 0 0 0 0 0 0 Port 2 data register P2 226 E2H 0 0 0 0 0 0 0 0 Port ...

  • Samsung S3C84E5 - page 222

    RESET and POWER - DOWN S3C84E5 /C84E9/P84E9 8 - 4 Table 8 - 3. S3C84E5/C84E9/P84E9 Set 1, Bank 1 Register Values After RESET Register Name Mnemonic Address Bit Values After RESET Dec Hex 7 6 5 4 3 2 1 0 Timer A, 1 interrupt pending register TINTPND 224 E0H 0 0 0 0 0 0 0 0 Timer A control register TACON 225 E1H 0 0 0 0 0 0 0 0 Timer A data regi ster ...

  • Samsung S3C84E5 - page 223

    S3C84E5/C84E9/P84E9 RESET and POWER - DOWN 8 - 5 POWER - DOWN MODES STOP MODE Stop mode is invok ed by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on - chip main oscillator stops and the supply current is reduced to less than 3 µA except for the current consumption of LVR (L ...

  • Samsung S3C84E5 - page 224

    RESET and POWER - DOWN S3C84E5 /C84E9/P84E9 8 - 6 How to Enter into Stop Mode There are two steps to enter into Stop mode: 1. Handling OSCCON register. 2. Handling STPCON register then writing Stop instruction (keep the order). IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some pe ...

  • Samsung S3C84E5 - page 225

    S3C84E5/C84E9/P84E9 I/O PORTS 9 - 1 9 I/O PORTS OVERVIEW The S3C84E5/C84E9/P84E9 microcontroller has seven bit - programmable I/O ports, P0 – P4. This gives a total of 36 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly w riting or reading port registers. No special I/O ins ...

  • Samsung S3C84E5 - page 226

    I/O PORTS S3C84E5/C 84E9/P84E9 9 - 2 PORT DATA REGISTERS Table 9 - 2 gives yo u an overview of the register locations of all seven S3C84E5/C84E9/P84E9 I/O port data registers. Data registers for ports 0, 1, 2, 3 and 4 have the general format shown in Table 9 - 2. Table 9 - 2. Port Data Register Summary Register Name Mnemonic Decimal Hex Location R/ ...

  • Samsung S3C84E5 - page 227

    S3C84E5/C84E9/P84E9 I/O PORTS 9 - 3 PORT 0 Port 0 is an 8 - bit I/O port that you can use two ways: — General - purpose digital I/O — Alternative function: TACAP, TACK, T1CAP0, T1OUT1, T1CK1, T1CAP1, XT IN , XT OUT Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location E0H in set 1, bank 0. Port 0 Control Reg ...

  • Samsung S3C84E5 - page 228

    I/O PORTS S3C84E5/C 84E9/P84E9 9 - 4 Port 0 Control Register, Low Byte (P0CONL) E7H, Set1, Bank0, R/W, Reset value="0FH" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.6] P0.3/T1CK1 Configuration Bits 0 0 = Input mode with pull-up; T1CK1 input 0 1 = Input mode; T1CK1 input 1 X = Push-pull output mode [.5-.4] P0.2/T1CAP1 Configuration Bits 0 0 = Inp ...

  • Samsung S3C84E5 - page 229

    S3C84E5/C84E9/P84E9 I/O PORTS 9 - 5 PORT 1 Port 1 is a 6 - bit I/O port with individually configurable pins that you can use two ways: — General - purpose digital I/O — Alternative function: TAOUT, T1OUT0, T1CK0, BZOUT, TXD, RXD Port 1 is accessed directly by writing or reading the port 1 data register, P1 at location E1H in set 1, bank 0. Port ...

  • Samsung S3C84E5 - page 230

    I/O PORTS S3C84E5/C 84E9/P84E9 9 - 6 Port 1 Control Register, Low Byte (P1CONL) E9H, Set1, Bank0, R/W, Reset value="00H" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.6] P1.3/BZOUT Configuration Bits 0 0 = Input mode with pull-up 0 1 = Input mode 1 0 = Push-pull output mode 1 1 = Alternative function mode: BZOUT output [.5-.4] P1.2/T1OUT0 Configur ...

  • Samsung S3C84E5 - page 231

    S3C84E5/C84E9/P84E9 I/O PORTS 9 - 7 PORT 2 Port 2 is an 8 - bit I/O port with in dividually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E2H in set 1, bank 0. P2.0 – P2.7 can serve as digital inputs, outputs (push pull) or you can configure the following alternative functions: ...

  • Samsung S3C84E5 - page 232

    I/O PORTS S3C84E5/C 84E9/P84E9 9 - 8 Port 2 Control Register, High Byte (P2CONH) EAH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.6] P2.7/INT7 Configuration Bits 0 0 = Input mode with pull-up; falling edge interrupt (INT7) 0 1 = Input mode; falling edge interrupt (INT7) 1 0 = Input mode; rising edge interrupt ( ...

  • Samsung S3C84E5 - page 233

    S3C84E5/C84E9/P84E9 I/O PORTS 9 - 9 Port 2 Control Register, Low Byte (P2CONL) EBH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.6] P2.3/INT3 Configuration Bits 0 0 = Input mode with pull-up; falling edge interrupt (INT3) 0 1 = Input mode; falling edge interrupt (INT3) 1 0 = Input mode; rising edge interrupt (IN ...

  • Samsung S3C84E5 - page 234

    I/O PORTS S3C84E5/C 84E9/P84E9 9 - 10 Port 2 Interrupt Pending Register (P2INTPND) EDH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7] P2.7/PND7, Interrupt Pending Bit 0 = No interrupt pending (when read) / Pending bit clear (when write) 1 = Interrupt is pending (when read) / No effect (when write) [.6] P2.6/PND6, ...

  • Samsung S3C84E5 - page 235

    S3C84E5/C84E9/P84E9 I/O PORTS 9 - 11 Port 2 Interrupt Control Register (P2INT) ECH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7] P2.7 External Interrupt (INT7) Enable Bit 0 = Disable interrupt 1 = Enable interrupt [.6] P2.6 External Interrupt (INT6) Enable Bit 0 = Disable interrupt 1 = Enable interrupt [.5] P2.5 ...

  • Samsung S3C84E5 - page 236

    I/O PORTS S3C84E5/C 84E9/P84E9 9 - 12 PORT 3 Port 3 is an 8 - bit I/O port that can be used for general - purpose digital I/O. The pins are accessed directly by writing or reading the port 3 data register, P3 at location E3H in set 1, bank 0. P3.0 – P3.7 can serve as inputs, outputs (push pull) or you can configure the following alternative funct ...

  • Samsung S3C84E5 - page 237

    S3C84E5/C84E9/P84E9 I/O PORTS 9 - 13 Port 3 Control Register, Low Byte (P3CONL) EFH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.6] P3.3/ADC3 Configuration Bits 0 0 = Input mode with pull-up 0 1 = Input mode 1 0 = Push-pull output mode 1 1 = Alternative function mode: ADC3 input [.5-.4] P3.2/ADC2 Configuration ...

  • Samsung S3C84E5 - page 238

    I/O PORTS S3C84E5/C 84E9/P84E9 9 - 14 PORT 4 Port 4 is a 6 - bit I/O port that you can use two ways: — General - purpose digital I/O — Alternative function: INT8 – INT10, TBPWM Port 4 is accessed directly by writing or reading the port 4 data register, P4 at location E4H in set 1, bank 0. Port 4 Control Register (P4CONH, P4CONL) Port 4 pins a ...

  • Samsung S3C84E5 - page 239

    S3C84E5/C84E9/P84E9 I/O PORTS 9 - 15 Port 4 Control Register, High Byte (P4CONH) F0H, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.4] Not used (must keep always 0) [.3-.2] P4.5 Configuration Bits 0 0 = Input mode with pull-up 0 1 = Input mode 1 X = Push-pull output mode [.1-.0] P4.4 Configuration Bits 0 0 = Inpu ...

  • Samsung S3C84E5 - page 240

    I/O PORTS S3C84E5/C 84E9/P84E9 9 - 16 Port 4 Interrupt Pending Register (P4INTPND) F3H, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.3] Not used (must keep always 0) [.2] P4.2/PND10, Interrupt Pending Bit 0 = No interrupt pending (when read) / Pending bit clear (when write) 1 = Interrupt is pending (when read) / ...

  • Samsung S3C84E5 - page 241

    S3C84E5/C84E9/P84E9 BASIC TIMER 10 - 1 10 BASIC TIMER OVERVIEW BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabiliza tion interval after a reset or a Stop mode release. ...

  • Samsung S3C84E5 - page 242

    BASIC TIMER S3C84E5 /C84E9/P84E9 10 - 2 Basic Timer Control Register (BTCON) D3H, Set 1, R/W LSB MSB .7 .6 .5 .4 .3 .2 .1 .0 Divider clear bit: 0 = No effect 1 = Clear divider Basic timer counter clear bit: 0 = No effect 1 = Clear BTCNT Basic timer input clock selection bit: 00 = fxx/4096 01 = fxx/1024 10 = fxx/128 11 = fxx/1 (Not used) Watchdog ti ...

  • Samsung S3C84E5 - page 243

    S3C84E5/C84E9/P84E9 BASIC TIMER 10 - 3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7 – BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", a ...

  • Samsung S3C84E5 - page 244

    BASIC TIMER S3C84E5 /C84E9/P84E9 10 - 4 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). MUX f xx/4096 DIV f xx/1024 f xx/128 fxx Bits 3, 2 Bit 0 Basic Timer Control Register (Write '1010xxxxB' to disable) Clear Bit 1 RESET o ...

  • Samsung S3C84E5 - page 245

    S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 1 11 8 - BIT TIMER A/B 8 - BIT TIMER A OVERVIEW The 8 - bit timer A is an 8 - bit general - purpose timer/counter. Timer A has three operating modes, you can select one of them using the appropriate TACON setting: — Interval timer mode (Toggle output at TAOUT pin) — Capture input mode with a rising or ...

  • Samsung S3C84E5 - page 246

    8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 2 FUNCTION DESCRIPTION Timer A Interrupts (IRQ1, Vectors C0H and C2H) The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT). TAOVF is interrupt level IRQ1, vector C2H. TAINT also belongs to interrupt level IRQ1, but is assi ...

  • Samsung S3C84E5 - page 247

    S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 3 TIMER A CONTROL REGI STER (TACON) You use the timer A control register, TACON, to: — Select the timer A operating mode (interval timer, capture mode and PWM mode) — Select the timer A input clock frequency — Clear the timer A counter, TACNT — Enable the timer A overflow interrupt or timer A match ...

  • Samsung S3C84E5 - page 248

    8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 4 BLOCK DIAGRAM NOTES: 1. When PWM mode, match signal cannot clear counter. 2. Pending bit is located at TINTPND register. Clear Match TACON.7-.6 f xx/1024 f xx/256 f xx/64 TACK TACON.2 Pending TACON.3 Overflow TAOVF TACAP TAOUT(TAPWM) TINTPND.0 TACON.5.-4 Data Bus 8 Data Bus 8 M U X M U X 8-bit Up-Counte ...

  • Samsung S3C84E5 - page 249

    S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 5 8 - BIT TIMER B OVERVIEW The S3C84E5/C84E9/P84E9 micro - controller has an 8 - bit timer called timer B. Timer B, which can be used to generate the carrier frequency of a remote controller signal. Also, it can be used as the programmable buzz signal generator that makes a sound with a various frequency f ...

  • Samsung S3C84E5 - page 250

    8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 6 TIMER B CONTROL REGI STER (TBCON) Timer B Control Register (TBCON) D0H, Set 1, Bank 0, R/W LSB MSB .7 .6 .5 .4 .3 .2 .1 .0 Timer B mode selection bit: 0 = One-shot mode 1 = Repeating mode Timer B input clock selection bit: 00 = fxx/4 01 = fxx/8 10 = fxx/64 11 = fxx/256 Timer B interrupt time selection b ...

  • Samsung S3C84E5 - page 251

    S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 7 TIMER B PULSE WIDTH CALCULATIONS t LOW t LOW t HIGH To generate the above repeated waveform consisted of low period time, t LOW , and high period time, t HIGH . When T - FF = 0, t LOW = (TBDATAL + 1) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock. t HIGH = (TBDATAH + 1) x 1/fx, 0H < ...

  • Samsung S3C84E5 - page 252

    8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 8 Timer B Clock 0H T-FF = '0' TBDATAL = 01-FFH TBDATAH = 00H T-FF = '0' TBDATAL = 00H TBDATAH = 01-FFH T-FF = '0' TBDATAL = 00H TBDATAH = 00H T-FF = '1' TBDATAL = 00H TBDATAH = 00H High Low Low High Timer B Clock T-FF = '1' TBDATAL = DFH TBDATAH = 1FH T-FF ...

  • Samsung S3C84E5 - page 253

    S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 9 F PROGRAMMING TIP — To Gen erate 38 kHz, 1/3duty signal through P4.3 This example sets Timer B to the repeat mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are: 17.59 µ s 37.9 kHz 1/3 Duty 8 ...

  • Samsung S3C84E5 - page 254

    8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 10 F PROGRAMMING TIP — To generate a one pulse signal through P4.3 This example sets Timer B to the one shot mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 40 µ s width pulse. The program parameters are: 40 µ s — Timer B is used in one shot mode ? ...

  • Samsung S3C84E5 - page 255

    S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 11 F PROGRAMMING TIP — Using the Timer A ORG 0000h VECTOR 0C0h,TAMC_INT VECTOR 0C2h,TAOV_INT ORG 0100h INITIAL: LD SYM,#00h ; Disable Global/Fast interrupt → SYM LD IMR,#00000010b ; Enable IRQ1 interrupt LD SPH,#00000000b ; Set stack area LD SPL,#00000000b LD BTCON,#10100011b ; Disable watch - dog LD P ...

  • Samsung S3C84E5 - page 256

    8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 12 F PROGRAMMING TIP — Using the Timer B ORG 0000h VECTOR 0BEh,TBUN_INT ORG 0100h INITIAL: LD SYM,#00h ; Disable Global/Fast interrupt LD IMR,#00000001b ; Enable IRQ0 interrupt LD SPH,#00000000b ; Set stack area LD SPL,#00000000b LD BTCON,#10100011b ; Disable Watch - dog LD P4CONL,#00000011b ; Enable TB ...

  • Samsung S3C84E5 - page 257

    S3C84E5/C84E9/P84E9 16 - BIT TIMER 1(0,1 ) 12 - 1 12 16 - BIT TIMER 1(0,1) OVERVIEW The S3C84E5/C84E9/P84E9 has two 16 - bit timer/counters. The 16 - bit timer 1(0,1) is an 16 - bit general - purpose timer/counter. Timer 1(0,1) has three operating modes, one of which you select using the appropriate T1CON0, T1CON1 setting is — Interval timer mode ...

  • Samsung S3C84E5 - page 258

    16 - BIT TIMER 1(0,1) S3C84E5/C84E9/P84E9 12 - 2 FUNCTION DESCRIPTION Timer 1 (0,1) Interrupts (IRQ2, Vectors C4H, C6H, C8H and CAH) The timer 1(0) module can generate two interrupts, the timer 1(0) overflow interrupt (T1OVF0), and the timer 1(0) match/capture interrupt (T1INT0). T1OVF0 is interrupt level IRQ2, vector C6H. T1INT0 also belongs to in ...

  • Samsung S3C84E5 - page 259

    S3C84E5/C84E9/P84E9 16 - BIT TIMER 1(0,1 ) 12 - 3 PWM Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T1OUT0, T1OUT1 pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1(0,1) data registers. In PWM mode, how ...

  • Samsung S3C84E5 - page 260

    16 - BIT TIMER 1(0,1) S3C84E5/C84E9/P84E9 12 - 4 NOTE: Interrupt pending bits are located in TINTPND register. Timer 1 Control Register (T1CON0) E8H, Set 1, Bank 1, R/W (T1CON1) E9H, Set 1, Bank 1, R/W LSB MSB .7 .6 .5 .4 .3 .2 .1 .0 Timer 1 overflow interrupt enable bit 0 = Disable overflow interrupt 1 = Enable overflow interrrupt Timer 1 clock so ...

  • Samsung S3C84E5 - page 261

    S3C84E5/C84E9/P84E9 16 - BIT TIMER 1(0,1 ) 12 - 5 Timer A, Timer 1 Pending Register (TINTPND) E0H, Set 1, Bank 1, R/W LSB MSB .7 .6 .5 .4 .3 .2 .1 .0 Timer A overflow interrupt pending bit 0 = No interrupt pending 1 = Interrrupt pending Not used (must keep always 0) Timer A match/capture interrupt pending bit 0 = No interrupt pending 1 = Interrrupt ...

  • Samsung S3C84E5 - page 262

    16 - BIT TIMER 1(0,1) S3C84E5/C84E9/P84E9 12 - 6 BLOCK DIAGRAM f xx/1 f xx/64 f xx/8 V S S T1CK f xx/256 f xx/1024 NOTES: 1. When PWM mode, match signal cannot clear counter. 2. Pending bit is located at TINTPND register. Clear Match T1CON.7-.5 T1CON.0 Pending T1CON.2 Overflow T1OVF T1CAP T1OUT(T1PWM) TINTPND T1CON.4.3 T1CON.4-.3 Data Bus 8 Data Bu ...

  • Samsung S3C84E5 - page 263

    S3C84E5/C84E9/P84E9 16 - BIT TIMER 1(0,1 ) 12 - 7 F PROGRAMMING TIP — Using the Timer 1(0) ORG 0000h VECTOR 0C4h,TIM1_INT ORG 0100h INITIAL: LD SYM,#00h ; Disable Global/Fast interrupt LD IMR,#00001000b ; Enable IRQ2 interrupt LD SPH,#00000000b ; Set stack area LD SPL,#00000000b LD BTCON,#10100011b ; Disable Watch - dog SB1 LD T1CON0,#01000110b ; ...

  • Samsung S3C84E5 - page 264

    S3C84E5/C84E9/P84E9 UART 13 - 1 13 UART OVERVIEW The UART block has a full - duplex serial port with programmable operating modes: There is one synchronous mode and three UART (Universal Asynchronous Receiver/Transmitter) modes: — S hift Register I/O with baud rate of fxx/(16 × (16 - bit BRDATA+1)) — 8 - bit UART mode; variable baud rate, fxx/ ...

  • Samsung S3C84E5 - page 265

    UART S3C84E5/C84E9/ P84E9 13 - 2 UART CONTROL REGISTE R (UARTCON) The control register for the UART is called UARTCON at address F6H. It has the following control functions: — Operating mode and baud rate selection — Multiprocessor communication and interrupt control — Serial receive enable/disable control — 9th data bit location for transm ...

  • Samsung S3C84E5 - page 266

    S3C84E5/C84E9/P84E9 UART 13 - 3 If parity disable mode (PEN = 0), location of the 9th data bit that was received in UART mode 2 ("0" or "1"). If parity enable mode (PEN = 1), Even/odd parity selection bit for receive data in UART mode 2. 0 : Even parity check for the received data 1 : Odd parity check for the received data UART ...

  • Samsung S3C84E5 - page 267

    UART S3C84E5/C84E9/ P84E9 13 - 4 UART INTERRUPT PENDI NG REGISTER (UARTPND ) The UART interrupt pending register, UARTPND is located at address F4H. It contains the UART data transmit interrupt pending bit (UARTPND.0) and the receive interrupt pending bit (UARTPND.1). In mode 0 of the UART module, the receive interrupt pending flag UARTPND.1 is set ...

  • Samsung S3C84E5 - page 268

    S3C84E5/C84E9/P84E9 UART 13 - 5 In mode 2 (9 - bit UART data), by setting the parity enable bit (PEN) of UARTPND register t o '1', the 9 th data bit of transmit data will be an automatically generated parity bit. Also, the 9 th data bit of the received data will be treated as a parity bit for checking the received data. In parity enable m ...

  • Samsung S3C84E5 - page 269

    UART S3C84E5/C84E9/ P84E9 13 - 6 UART BAUD RATE DATA REGISTER (BRDATAH, B RDATAL) The value stored in the UART baud rate register, (BRDATAH, BRDATAL), lets you determine the UART clock rate (baud rate). UART Baud Rate Data Register (BRDATAH) EEH, Set1, Bank 0, R/W, Reset Value: FFH (BRDATAL) EFH, Set1, Bank 0, R/W, Reset Value: FFH .7 MSB LSB .6 .5 ...

  • Samsung S3C84E5 - page 270

    S3C84E5/C84E9/P84E9 UART 13 - 7 Table 13 - 1. Commonly Used Baud Rates Generated by 16 - bit BRDATA Baud Rate Oscillation Clock BRDATAH BRDATAL Decimal Hex Decimal Hex 230,400 Hz 11.0592 MHz 0 0H 02 02H 115,200 Hz 11.0592 MHz 0 0H 05 05H 57,600 Hz 11.0592 MHz 0 0H 11 0BH 38,400 Hz 11.0592 MHz 0 0H 17 11H 19,200 Hz 11.0592 MHz 0 0H 35 23H 9,600 Hz 1 ...

  • Samsung S3C84E5 - page 271

    UART S3C84E5/C84E9/ P84E9 13 - 8 BLOCK DIAGRAM Zero Detector UDATA RxD (P1.4) TIE RIE Interrupt 1-to-0 Transition Detector RE RIE Bit Detector Shift Value MS0 MS1 MS0 MS1 RxD (P1.4) SAM88 Internal Data Bus Write to UDATA Baud Rate Generator S D Q CLK TB8 CLK Tx Control Start Tx Clock TIP Shift EN Send Rx Control Rx Clock Start RIP Receive Shift Shi ...

  • Samsung S3C84E5 - page 272

    S3C84E5/C84E9/P84E9 UART 13 - 9 UART MODE 0 FUNCTION DESCRIPTION In mode 0, UART is input and output through the RxD (P1.4) pin and TxD (P1.5) pin outputs the shift clock. Data is transmitted or received in 8 - bit units only. The LSB of the 8 - bit value is transmitted (or received) first. Mode 0 Transmit Procedure 1. Select mode 0 by setting UART ...

  • Samsung S3C84E5 - page 273

    UART S3C84E5/C84E9/ P84E9 13 - 10 UART MODE 1 FUNCTION DESCRIPTION In mode 1, 10 - bits are transmitted (through the TxD (P1.5) pin) or received (through the RxD (P1.4) pin). Each data frame has three components: — Start bit ("0") — 8 data bits (LSB first) — Stop bit ("1") When receiving, the stop bit is written to the RB8 ...

  • Samsung S3C84E5 - page 274

    S3C84E5/C84E9/P84E9 UART 13 - 11 UART MODE 2 FUNCTION DESCRIPTION In mode 2, 11 - bits are transmitted (through the TxD pin) or received (through the RxD pin). Each data frame has four components: — Start bit ("0") — 8 data bits (LSB first) — Programmable 9th data bit or parity bit — Stop bit ("1") < In parity disable ...

  • Samsung S3C84E5 - page 275

    UART S3C84E5/C84E9/ P84E9 13 - 12 Transmit TIP Write to Shift Register (UARTDATA) Start Bit TxD Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Shift Tx Clock Receive RIP Start Bit Rx Clock Stop Bit RxD D0 D1 D2 D3 D4 D5 D6 D7 Bit Detect Sample Time Shift TB8 or Parity bit RB8 or Parity bit Figure 13 - 8. Timing Diagram for UART Mode 2 Operation ...

  • Samsung S3C84E5 - page 276

    S3C84E5/C84E9/P84E9 UART 13 - 13 SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C9 - series multiprocessor communication features let a "master" S3C84E5/C84E9/P84E9 send a multiple - frame serial message to a "slave" device in a multi - S3C84E5/C84E9/P84E9 configuration. It does this without interrupting other slav ...

  • Samsung S3C84E5 - page 277

    UART S3C84E5/C84E9/ P84E9 13 - 14 Setup Procedure for Multiprocessor Com munications Follow these steps to configure multiprocessor communications: 1. Set all S3C84E5/C84E9/P84E9 devices (masters and slaves) to UART mode 2 with parity disable. 2. Write the MCE bit of all the slave devices to "1". 3. The master device's transmission p ...

  • Samsung S3C84E5 - page 278

    S3C84E5/C84E9/P84E9 WATCH TIMER 14 - 1 14 WATCH TIMER OVERVIEW Watch timer functions include real - time and watch - time measurement and interval timing for the system clock. To start watch timer operation, set bit1 and bit 6 of the watch timer mode register, WTCON.1and 6, to “1”. After the watch timer starts and elapses a time, the watch time ...

  • Samsung S3C84E5 - page 279

    WATCH TIMER S3C84E5 /C84E9/P84E9 14 - 2 WATCH TIMER CONTROL REGISTER (WTCON: R/W ) FAH WTCON.7 WTCON.6 WTCON.5 WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0 RESET "0" "0" "0" "0" "0" "0" "0" "0" Table 14 - 1. Watch Timer Control Register (WTCON): Set 1, Bank 0, FAH, R/W Bit N ...

  • Samsung S3C84E5 - page 280

    S3C84E5/C84E9/P84E9 WATCH TIMER 14 - 3 WATCH TIMER CIRCUIT DIAGRAM WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 Enable/Disable Selector Circuit MUX WTCON.0 WTINT WTCON.6 BUZZER Output (BZOUT) f W2 6 1 Hz f X = Main System Clock (9.8304MHz) f XT = Subsystem Clock (32768 Hz) f W = Watch timer Clock Selector WTCON.7 Frequency Dividing Circuit f W 32768 Hz ...

  • Samsung S3C84E5 - page 281

    WATCH TIMER S3C84E5 /C84E9/P84E9 14 - 4 F PROGRAMMING TIP — Using the Watch Timer ORG 0000h VECTOR 0CCh,WT_INT ORG 0100h INITIAL: LD SYM,#00h ; Disable Global/Fast interrupt LD IMR,#00010000b ; Enable IRQ3 interrupt LD SPH,#00000000b ; Set stack area LD SPL,#0FFh LD BTCON,#10100011b ; Disable Watch - dog LD WTCON,#11001110b ; 0.5 kHz buzzer, 1.95 ...

  • Samsung S3C84E5 - page 282

    S3C84E5/C84E9/P84E9 A/D CONVERTER 15 - 1 15 A/D CONVERTER OVERVIEW The 10 - bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 - bit digital values. T he analog input level must lie between the AV REF and AV SS values. The A/D converter has the fol ...

  • Samsung S3C84E5 - page 283

    A/D CONVERTER S3C84 E5/C84E9 /P84E9 15 - 2 A/D CONVERTER CONTRO L REGISTER (ADCON) The A/D converter control register, ADCON, is located in set1, bank 0 at address F7H. ADCON is read - write addressable using 8 - bit instructions only. But, the EOC bit, ADCON.3 is read only. ADCON has four functions: — Bits 6 – 4 select an analog input pin (ADC ...

  • Samsung S3C84E5 - page 284

    S3C84E5/C84E9/P84E9 A/D CONVERTER 15 - 3 Conversion Data Register High Byte (ADDATAH) F8H, Set 1, Bank 0, Read only LSB MSB .7 .6 .5 .4 .3 .2 .1 .0 Conversion Data Register Low Byte (ADDATAL) F9H, Set 1, Bank 0, Read only LSB MSB xxxxxx .1 .0 Figure 15 - 2. A/D Converter Data Register (ADDATAH, ADDATAL) Input Pins ADC0-ADC7 (P3.0-P3.7) 10-bit resul ...

  • Samsung S3C84E5 - page 285

    A/D CONVERTER S3C84 E5/C84E9 /P84E9 15 - 4 INTERNAL REFERENCE V OLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AV SS to AV REF (AV REF = V DD ). Differen t reference voltage levels are generated internally along the resistor tree durin ...

  • Samsung S3C84E5 - page 286

    S3C84E5/C84E9/P84E9 A/D CONVERTER 15 - 5 INTERNAL A/D CONVERS ION PROCEDURE 1. Analog input must remain between the voltage range of AV SS and AV REF . 2. Configure P3.0 – P3.7 for analog input before A/D convers ions. To do this, you load the appropriate value to the P3CONH and P3CONL (for ADC0 – ADC7) registers. 3. Before the conversion opera ...

  • Samsung S3C84E5 - page 287

    A/D CONVERTER S3C84 E5/C84E9 /P84E9 15 - 6 F PROGRAMMING TIP — Configuring A/D Converter • • LD P3CONH, #11111111B ; P3.7 – P3.4 A/D Input MODE LD P3CONL, #11111111B ; P3.3 – P3.0 A/D Input MODE • • LD ADCON, #00000001B ; Channel ADC0, fxx, Conversion start AD0_CHK: TM ADCON, #0 0001000B ; A/D conversion end → EOC check JR Z, AD0_CH ...

  • Samsung S3C84E5 - page 288

    S3C84E5/C84E9/P 84E9 LOW VOLTAGE R ESET 16 - 1 16 LOW VOLTAGE RESET OVERVIEW The S3C84E5/C84E9/P84E9 can be reset in four ways: — by external power - on - Reset — by the external nReset input pin pulled low — by the digital watchdog timing out — by the Low Voltage reset ci rcuit (LVR) During an external power - on reset, the voltage VDD is ...

  • Samsung S3C84E5 - page 289

    LOW VOLTAGE RESET S 3C84E5/C84E9/P84E9 16 - 2 + - V REF BGR V IN V DD Longger than 1us N.F Internal System RESET When the V DD level is lower than 2.9V Comparator NOTES: 1. The target of voltage detection level is 2.9 V at V DD = 5 V 2. BGR is Band Gap voltage Reference Longger than 1us N.F nRESET Watchdog RESET V REF V DD Figure 16 - 1. Low Voltag ...

  • Samsung S3C84E5 - page 290

    S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-1 17 ELECTRICAL DATA OVERVIEW In this chapter, S3C84E5/C84E9/P 84E9 electrical characteristics ar e presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.C. electrical characteristics — A.C. electrical characterist ...

  • Samsung S3C84E5 - page 291

    ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-2 Table 17-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – – 0.3 to + 6.5 V Input voltage V I All input ports – 0.3 to VDD + 0.3 Output voltage V O All output ports – 0.3 to VDD + 0.3 Output current high I OH One I/O pin active – 18 mA All I/ ...

  • Samsung S3C84E5 - page 292

    S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-3 Table 17-3. D.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Ty p. Max Unit Input high voltage V IH1 V DD = V LVR to 5.5V All port and nRESET 0.8 V DD – V DD V V IH2 V DD = V LVR to 5.5V X IN and XT IN V DD – 0.5 Input low voltage V ...

  • Samsung S3C84E5 - page 293

    ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-4 Table 17-3. D.C. Electrical Characteristics (Continued) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Typ. Max Unit Pull-up resistor R P1 V DD = 5 V; V IN = 0 V, T A = 25 ° C All I/O pins except nRESET 10 50 100 k Ω V DD = 3 V; V IN = 0 V, T A = 25 ° C All I/O p ...

  • Samsung S3C84E5 - page 294

    S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-5 Table 17-4. A.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Ty p. Max Unit Interrupt input high, low width (Ports 4) t INTH , t INTL V DD = 5 V 180 – – ns nRESET input low width t RSL Input 1.0 – – µ s NOTE: User must keep more ...

  • Samsung S3C84E5 - page 295

    ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-6 Table 17-5. Main Oscillator Frequency (f OSC1 ) (T A = – 25 ° C + 85 ° C, V DD = V LVR to 5.5 V) Oscillator Clock Circuit Test Condition Min Typ. Max Unit Main crystal or ceramic X IN C1 C2 X OUT V DD = V LVR to 5.5 V 1 – 12 MHz External clock (main system) X IN X OUT V DD = V LVR to 5.5 V 1 – 12 Ta ...

  • Samsung S3C84E5 - page 296

    S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-7 X IN t XH t XL 1/f OSC1 V DD - 0.5 V 0.4 V Figure 17-3. Clock Timing Measurement at X IN Table 17-7. Sub Oscillator Frequency (f OSC2 ) (T A = –25 ° C + 85 ° C, V DD = V LVR to 5.5 V) Oscillator Clock Circuit Test Condition Min Typ. Max Unit Crystal C1 C2 XT IN XT OUT R Crystal oscillation frequency C1 ...

  • Samsung S3C84E5 - page 297

    ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-8 Table 17-9. Data Retention Supply Voltage in Stop Mode (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR Stop mode 2 – 5.5 v Data retention supply current I DDDR Stop mode, V DDDR = 2.0 V – – 8 µ A NOTE: Supply cu ...

  • Samsung S3C84E5 - page 298

    S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-9 Execution of STOP Instruction ~ ~ V DDDR ~ ~ Stop Mode Idle Mode Data Retention Mode t WAIT V DD Interrupt Normal Operating Mode Oscillation Stabilization Time 0.2 V DD NOTE: When the case of select the fxx/128 for basic timer input clock before enter the stop mode. tWAIT = 128 x 16 x (1/32768) = 62.5 ms Fi ...

  • Samsung S3C84E5 - page 299

    ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-10 Table 17-10. UART Timing Characteristics in Mode 0 (10 MHz) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V, Load capacitance = 80 pF) Parameter Symbol Min Ty p. Max Unit Serial port clock cycle time t SCK 500 t CPU × 6 700 Output data setup to clock rising edge t S1 300 t CPU × 5 – Clock rising ...

  • Samsung S3C84E5 - page 300

    S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-11 Table 17-11. A/D Converter Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V, V SS = 0 V) Parameter Symbol Test Conditions Min Ty p. Max Unit Resolution – 10 – bit Total accuracy V DD = 5.12 V – – ± 3 LSB Integral linearity error IL E CPU clock = 10 MHz AV REF = 5.1 ...

  • Samsung S3C84E5 - page 301

    ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-12 Table 17-12. LVR (Low Voltage Reset) Circuit Characteristics (T A = 25 ° C) Parameter Symbol Test Condition Min Typ Max Unit LVR voltage level V LVR T A = 25 ° C 2.6 2.9 3.2 V CPU Clock 1 MH z Main O scillator Frequency 1234567 Supply Voltage (V) 8 MH z 12 MH z V LVR 5.5 V Minimum instruction clock = 1/4 ...

  • Samsung S3C84E5 - page 302

    S3C84E5/C84E9/P84E9 MECHANICAL DATA 18 - 1 18 MECHANICAL DATA OVERVIEW The S3C84E5/C84E9/P84E9 microcontrollers are available in a 42 - SDIP - 600, 44 - QFP - 1010 package. NOTE : Dimensions are in millimeters. 39.50 MAX 39.10 ?0 .20 0.50 ? 0.10 1.78 (1.77) 0.51 MIN 3.30 ?0.30 3.50 ? 0.20 5.08 MAX 42-SDIP-600 0-15 1.00 ? 0.10 0.25 + 0.10 - 0.05 15. ...

  • Samsung S3C84E5 - page 303

    MECHANICAL DATA S3C 84E5/C84E9/P84E9 18 - 2 NOTE : Dimensions are in millimeters. 44-QFP-1010 13.20 ± 0.3 #44 (1.00) #1 13.20 ± 0.3 10.00 ± 0.2 0.35 +0.10 - 0.05 0.10 MAX 0.15 +0.10 - 0.05 0-8° 0.05 MIN 2.05 ± 0.10 2.30 MAX 0.80 ±0.20 0.80 10.00 ± 0.2 Figure 18 - 2. 44 - QFP - 1010 Package Dimensions ...

  • Samsung S3C84E5 - page 304

    S3C84E5/C84E9/P84E9 OTP VERSION 19-1 19 S3P84E9 OTP VERSION OVERVIEW The S3P84E9 single-chip CMOS microcontro ller is the OTP (One Time Programmable) version of the S3C84E5/C84E9 microcontroller. It has an on-chip EPROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P84E9 is fully compatible with the S3C84E5/C84E9, both ...

  • Samsung S3C84E5 - page 305

    OTP VERSION S3C84E5/C84E9/P84E9 19-2 SDAT /TBPW M /P4.3 SCLK /INT10/P4.2 VDD VSS Xout Xin VPP /TEST S3P84E9 Top View (44-Q FP) 1 2 3 4 5 6 7 8 9 10 11 P4.4 P0.2/T1CAP1 P0.3/T1CK1 P0.4/T1OUT1 P0.5/T1CAP0 P0.6/TACK P0.7/TACAP P1.0/TAOUT P1.1/T1CK0 44 43 42 41 40 39 38 37 36 35 34 P4.5 AVref 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 ...

  • Samsung S3C84E5 - page 306

    S3C84E5/C84E9/P84E9 OTP VERSION 19-3 Table 19-1. Descriptions of Pins Used to Read/Write the OTP Main Chip Pin Name During Programming Pin Name Pin No. I/O Function P4.3 SDAT 9(3) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a input or push-pull output port. P4.2 SCLK 10(4) I Serial clock pin. Input ...

  • Samsung S3C84E5 - page 307

    OTP VERSION S3C84E5/C84E9/P84E9 19-4 NOTES ...

  • Samsung S3C84E5 - page 308

    S3C84E5/C84E9/P84E9 DEVELOPMENT TOOLS 20 - 1 20 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy - to - use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supp orting software. For a host system, any standard computer that employs Win95/98/2000 as its o ...

  • Samsung S3C84E5 - page 309

    DEVELOPMENT TOOLS S 3C84E5/C84E9/P84E9 20 - 2 TARGET BOARDS Target boards are available for all the S3C8 - series microcontrollers. All the required target system cables and adapters are included on the device - specific target board . TB84E5/84E9 is a specific target board for the S3C84E5/C84E9 and S3P84E9 development. OTP One time programmable mi ...

  • Samsung S3C84E5 - page 310

    S3C84E5/C84E9/P84E9 DEVELOPMENT TOOLS 20 - 3 TB84E5/84E9 TARGET B OARD The TB84E5/84E9 target board is used for the S3C84E5/C 84E9 and the S3P84E9 microcontroller. It is supported by the SMDS2+ or SK - 1000 development system (In - Circuit Emulator). Figure 20 - 2. TB84E5/84E9 Target Board Configuration TB84E5/84E9 SM13XXA 100-Pin Connector 25 1 RE ...

  • Samsung S3C84E5 - page 311

    DEVELOPMENT TOOLS S 3C84E5/C84E9/P84E9 20 - 4 Table 20 - 1. Power Selection Settings for TB84E5/84E9 To User_Vcc' Settings Operating Mode Comments To User_V DD Off On Target System SMDS2+ or SK-1000 TB84E5/E9 V DD V SS V DD SMDS2+ or SK - 1000 supplies V DD to the target board (evaluation chip) and the target system. To User_V DD Off On Target ...

  • Samsung S3C84E5 - page 312

    S3C84E5/C84E9/P84E9 DEVELOPMENT TOOLS 20 - 5 Table 20 - 3. The Port 0.0 and Port 0.1 selection setting “Sub - OSC” Setting Description XTin P0.0 XTout P0.1 If you set the Sub - OSC to the XTin and XTout side, 32,768Hz - subsystem crystal will be connected to P0.0 and P0.1 pins, and these pins are isolated to the user system. XTin P0.0 XTout P0. ...

  • Samsung S3C84E5 - page 313

    DEVELOPMENT TOOLS S 3C84E5/C84E9/P84E9 20 - 6 Target Board 44-Pin Connector Target System J101 1 2 43 44 Part Name: AS20D Order Cods: SM6304 1 2 43 44 44-Pin Connector Figure 20 - 4. TB84E5/84E9 Adapter Cable for 44pin Connector Package ...

  • Samsung S3C84E5 - page 314

    (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C8 - SERIES MASK RO M ORDER FORM Product description: Device Number: S3C84E___ - ________ write down the ROM code number) Product Order Form: Package ...

  • Samsung S3C84E5 - page 315

    (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C8 - SERIES REQUEST FOR PRODUCTI ON AT CUSTOMER RISK Customer Information: Company Name: ____________________________________________________________ ...

  • Samsung S3C84E5 - page 316

    (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C84E5/C84E9 MASK O PTION SELECTION FORM Device Number: S3C84E___ - ________(write down the ROM code number) Attachment (Check one): Diskette PROM Cus ...

Manufacturer Samsung Category Microphone

Documents that we receive from a manufacturer of a Samsung S3C84E5 can be divided into several groups. They are, among others:
- Samsung technical drawings
- S3C84E5 manuals
- Samsung product data sheets
- information booklets
- or energy labels Samsung S3C84E5
All of them are important, but the most important information from the point of view of use of the device are in the user manual Samsung S3C84E5.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Samsung S3C84E5, service manual, brief instructions and user manuals Samsung S3C84E5. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Samsung S3C84E5.

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A complete manual for the device Samsung S3C84E5, how should it look like?
A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Samsung S3C84E5 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Samsung S3C84E5.

A complete Samsung manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

1. Preface and tips on how to use the manual Samsung S3C84E5 - At the beginning of each manual we should find clues about how to use the guidelines. It should include information about the location of the Contents of the Samsung S3C84E5, FAQ or common problems, i.e. places that are most often searched by users in each manual
2. Contents - index of all tips concerning the Samsung S3C84E5, that we can find in the current document
3. Tips how to use the basic functions of the device Samsung S3C84E5 - which should help us in our first steps of using Samsung S3C84E5
4. Troubleshooting - systematic sequence of activities that will help us diagnose and subsequently solve the most important problems with Samsung S3C84E5
5. FAQ - Frequently Asked Questions
6. Contact detailsInformation about where to look for contact to the manufacturer/service of Samsung S3C84E5 in a specific country, if it was not possible to solve the problem on our own.

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