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Manual Samsung S3C9228/P9228

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  • Samsung S3C9228/P9228 - page 1

    21 - S3 - C9228/P9228-112002 USER'S M ANUAL S3C9228/P9228 8 -Bit CMOS Microcontroller Revision 1 ...

  • Samsung S3C9228/P9228 - page 2

    S3C9228/P9228 8-BIT CMOS MICROCONTROLLER S USER'S MANUAL Revision 1 ...

  • Samsung S3C9228/P9228 - page 3

    Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make chang ...

  • Samsung S3C9228/P9228 - page 4

    S3C9228/P9228 MICROCONTROLLER S iii Preface The S3C9228/P9228 Microcontroller s User's Manual is designed for application designers and programmers who are using the S3C9228/P9228 microcontroller s for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-rel ...

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    S3C9228/P9228 MICROCONTROLLER S v Table of Contents Part I — Programming Model Chapter 1 Product Overview SAM88RCRI Product Family ................................................................................................................... 1-1 S3C9228/P9228 Microcontroller ................................................................... ...

  • Samsung S3C9228/P9228 - page 7

    vi S3C9228/P9228 MICROCONTROLLER S Table of Contents (Cont inued ) Chapter 4 Control Registers Overview ................................................................................................................................................. 4-1 Chapter 5 Interrupt Structure Overview ......................................................... ...

  • Samsung S3C9228/P9228 - page 8

    S3C9228/P9228 MICROCONTROLLER S vii Table of Contents (Cont inued ) Part II — Hardware Descriptions Chapter 7 Clock Circui t Overview ................................................................................................................................................. 7-1 System Clock Circuit ........................................... ...

  • Samsung S3C9228/P9228 - page 9

    viii S3C9228/P9228 MICROCONTROLLER S Table of Contents (Con tinued ) Chapter 11 Timer 1 One 16-Bit Timer Mode (Timer 1) ............................................................................................................ 11-1 Overview ........................................................................................................... ...

  • Samsung S3C9228/P9228 - page 10

    S3C9228/P9228 MICROCONTROLLER S ix Table of Contents (Con cluded ) Chapter 1 6 Electrical Data Overview ................................................................................................................................................. 16-1 Chapter 1 7 Mechanical Data Overview .......................................................... ...

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    S3C9228/P9228 MICROCONTROLLER S xi List of Figures Figure Title Page Number Number 1-1 Block Diagram .................................................................................................................... 1-3 1-2 S3C9228 44-QFP Pin Assignments .................................................................................... 1-4 1-3 ...

  • Samsung S3C9228/P9228 - page 13

    xii S3C9228/P9228 MICROCONTROLLER S List of Figures (Cont inued ) Figure Title Page Number Number 5-1 S3C9-Series Interrupt Type ................................................................................................ 5-1 5-2 Interrupt Function Diagram ......................................................................................... ...

  • Samsung S3C9228/P9228 - page 14

    S3C9228/P9228 MICROCONTROLLER S xiii List of Figures (Con tinued ) Figure Title Page Number Number 10-1 Basic Timer Control Register (BTCON) .............................................................................. 10-2 10-2 Basic Timer Block Diagram .............................................................................................. ...

  • Samsung S3C9228/P9228 - page 15

    xiv S3C9228/P9228 MICROCONTROLLER S List of Figures (Con cluded ) Figure Title Page Number Number 16-1 Stop Mode Release Timing When Initiated by an External Interrupt .................................... 16-5 16-2 Stop Mode Release Timing When Initiated by a RESET ..................................................... 16-6 16-3 Input Timing for Ext ...

  • Samsung S3C9228/P9228 - page 16

    S3C9228/P9228 MICROCONTROLLER S xv List of Tables Table Title Page Number Number 1-1 Pin Descriptions ................................................................................................................. 1-6 6-1 Instruction Group Summary ................................................................................................ 6-2 ...

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    S3C9228/P9228 MICROCONTROLLER S xvii List of Programming Tips Description Page Number Chapter 2: Address Spaces Addressing the Common Working Register Area ..................................................................................... 2-4 Standard Stack Operations Using PUSH and POP ........................................................... ...

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  • Samsung S3C9228/P9228 - page 20

    S3C9228/P9228 MICROCONTROLLER S xix List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A/D Converter Co ntrol Register .............................................................................. 4-5 BTCON Basic Timer Control Register ............................................................................. ...

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    S3C9228/P9228 MICROCONTROLLER S xxi List of Instruction Descriptions Instruction Full Instruction Name Page Mnemonic Number ADC Add With Carry ...................................................................................................... 6 - 11 ADD Add ......................................................................................... ...

  • Samsung S3C9228/P9228 - page 23

    S3C9228/P9228 PRODUCT OVERVIEW 1- 1 1 PRODUCT OVERVIEW SAM8 8RC RI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chi p CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device . A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexibl ...

  • Samsung S3C9228/P9228 - page 24

    PRODUCT OVERVIEW S3C9228/P9228 1- 2 FEATURES CPU • SAM88RCRI CPU core Memory • 8192 × 8 bits program memory (ROM) • 264 × 8 bits data memory (RAM) (Including LCD data memory) Instruction Set • 41 instructions • Idle and Stop instructions added for power-down modes 36 I/O Pins • I/O: 34 pins (44-pin QFP, 42-pin SDIP) • Output only: 2 ...

  • Samsung S3C9228/P9228 - page 25

    S3C9228/P9228 PRODUCT OVERVIEW 1- 3 BLOCK DIAGRAM 8-Bit Timer/ CounterA Port I/O and Interrupt Control SAM88RCRI CPU RESET X IN XT IN I/O Port 0 8-Kbyte ROM 264-Byte Register File X OUT XT OUT 16-Bit Timer/ Counter1 8-Bit Timer/ CounterB TAOUT/ P0.0 T1CLK/ P0.1 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P0.4 P0.5 I/O Port 1 P1.0/AD0/INT P1 ...

  • Samsung S3C9228/P9228 - page 26

    PRODUCT OVERVIEW S3C9228/P9228 1- 4 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S3C9228 (44-QFP) P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT V DD V SS X OUT X IN TEST XT IN XT OUT RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.0/SCK SEG2/P3.1/INTP SEG3/P3.0/INTP SEG4/P4.0 SEG5/P4.1 SEG6/P4.2 SEG7/P4.3 33 32 31 30 29 28 ...

  • Samsung S3C9228/P9228 - page 27

    S3C9228/P9228 PRODUCT OVERVIEW 1- 5 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT V DD V SS X OUT X IN TEST XT IN XT OUT RESET P2.3 P2.2/SI SEG0/P2.1/SO S3C9228 (42-SDIP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/ ...

  • Samsung S3C9228/P9228 - page 28

    PRODUCT OVERVIEW S3C9228/P9228 1- 6 PIN DESCRIPTIONS Table 1- 1 . Pin Descriptions Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins P0.0 P0.1 P0.2 P0.3 I/O 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. E-4 39(3) 40(4) 41(5) 42(6) TAOUT/INT T1CLK/INT INT B ...

  • Samsung S3C9228/P9228 - page 29

    S3C9228/P9228 PRODUCT OVERVIEW 1- 7 Table 1- 1 . Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins V DD , V SS – Power input pins for internal power block – 5,6(11,12) – X OUT , X IN – Main oscillator pins for main clock – 7,8(13,14) XT OUT , XT IN – Sub oscillator pins for sub clock ? ...

  • Samsung S3C9228/P9228 - page 30

    PRODUCT OVERVIEW S3C9228/P9228 1- 8 PIN CIRCUIT DIAGRAMS RESET V DD Pull-Up Resistor Noise Filter Figure 1-4. Pin Circuit Type B V DD Output Output Disable Data V SS Figure 1-5. Pin Circuit Type C ...

  • Samsung S3C9228/P9228 - page 31

    S3C9228/P9228 PRODUCT OVERVIEW 1- 9 V DD Pull-up Enable V DD I/O Pull-up Resistor Output Disable Data External Interrupt Input Open-Drain Figure 1-7. Pin Circuit Type E-4 V DD I/O Pull-up Resistor Circuit Type E To ADC Data ADEN ADSELECT Open-Drain EN Data Output Disable Pull-up Enable Figure 1-8. Pin Circuit Type F-16A ...

  • Samsung S3C9228/P9228 - page 32

    PRODUCT OVERVIEW S3C9228/P9228 1- 10 Out SEG/COM V LC3 Output Disable V LC2 V LC1 V SS V LC4 V LC5 Figure 1-9. Pin Circuit Type H-23 ...

  • Samsung S3C9228/P9228 - page 33

    S3C9228/P9228 PRODUCT OVERVIEW 1- 11 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Figure 1-10. Pin Circuit Type H-32 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Figure 1-11. Pin Circuit Type H-32A ...

  • Samsung S3C9228/P9228 - page 34

    PRODUCT OVERVIEW S3C9228/P9228 1- 12 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Port Enable (LMOD.5) Figure 1-12. Pin Circuit Type H-32B ...

  • Samsung S3C9228/P9228 - page 35

    S3C9228/P9228 ADDRESS SPACES 2- 1 2 ADDRESS SPACES OVERVIEW The S3C9228/P9228 microcontroller has three kinds of address space: — Program memory (ROM) — Internal register file — LCD display register file A 16 -bit address bus supports program memory operations. Special instructions and related internal logic determine when the 1 6 -bit bus ca ...

  • Samsung S3C9228/P9228 - page 36

    ADDRESS SPACES S3C9228/P9228 2- 2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask- programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H– 0001H) are an interrupt vector address. The program reset address in the ROM is 01 ...

  • Samsung S3C9228/P9228 - page 37

    S3C9228/P9228 ADDRESS SPACES 2- 3 REGISTER ARCHITECTURE The upper 72 bytes of the S3C9228/P9228 's internal register file are addressed as working registers, system cont r ol registe r s and periphe r al control registers. The lower 184 bytes of internal register file (00H– B7 H) is called the general purpose register space . For many SAM88R ...

  • Samsung S3C9228/P9228 - page 38

    ADDRESS SPACES S3C9228/P9228 2- 4 COMMON WORKING REGISTER AREA (C0H–CFH) The SAM88RCR I register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as ...

  • Samsung S3C9228/P9228 - page 39

    S3C9228/P9228 ADDRESS SPACES 2- 5 SYSTEM STACK S 3C9 -series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file. STACK OPERATIONS Return addresses fo ...

  • Samsung S3C9228/P9228 - page 40

    ADDRESS SPACES S3C9228/P9228 2- 6 + + PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SP,#0 B8 H ; SP ← B8 H (Normally, the SP is set to 0 B8 H by the ; initialization routine) • • • PUSH SYM ; S ...

  • Samsung S3C9228/P9228 - page 41

    S3C9228/P9228 ADDRESSING MODES 3- 1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specifi ...

  • Samsung S3C9228/P9228 - page 42

    ADDRESSING MODES S3C9228/P9228 3- 2 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3- 1). Working register addressing differs from Register a ddressing because it uses a 16- byte working register s pace in the register file and a 4-bit register within that space (see Figure 3 ...

  • Samsung S3C9228/P9228 - page 43

    S3C9228/P9228 ADDRESSING MODES 3- 3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external mem ...

  • Samsung S3C9228/P9228 - page 44

    ADDRESSING MODES S3C9228/P9228 3- 4 INDIRECT REGISTER ADDRESSING MODE ( C ontinued ) dst OPCODE PAIR Points to Rigister Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16-Bit Address Points to Program Memory Figure 3- 4 . ...

  • Samsung S3C9228/P9228 - page 45

    S3C9228/P9228 ADDRESSING MODES 3- 5 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE OPERAND 4-Bit Working Register Address Point to the Woking Register (1 of 16) Sample Instruction: OR R6, @R2 Program Memory Register File src 4 LSBs Value used in Instruction OPERAND CFH C0H . . . . Figure 3- 5 . Indirect Working Register Addressing to Re ...

  • Samsung S3C9228/P9228 - page 46

    ADDRESSING MODES S3C9228/P9228 3- 6 INDIRECT REGISTER ADDRESSING MODE (C oncluded ) dst OPCODE 4-Bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program memory access LDE R3,@RR14 ; External data memory access LDE @RR4, R8 ; External data memory access Program Memory Register File src Value used in Instruction OPERAND Example Instru ...

  • Samsung S3C9228/P9228 - page 47

    S3C9228/P9228 ADDRESSING MODES 3- 7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3- 7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short o ...

  • Samsung S3C9228/P9228 - page 48

    ADDRESSING MODES S3C9228/P9228 3- 8 INDEXED ADDRESSING MODE (C ontinued ) Point to Working Register Pair (1 of 8) LSB Selects 16-Bit address added to offset dst OPCODE Program Memory XS (OFFSET) 4-Bit Working Register Address Sample Instructions: LDC R4, #04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4. LDE R4, ...

  • Samsung S3C9228/P9228 - page 49

    S3C9228/P9228 ADDRESSING MODES 3- 9 INDEXED ADDRESSING MODE (C oncluded ) Point to Working Register Pair (1 of 8) LSB Selects 16-Bit address added to offset Program Memory 4-Bit Working Register Address Sample Instructions: LDC R4, #1000H[RR2] ; The values in the program address (RR2 + #1000H) are loaded into register R4. LDE R4, #1000H[RR2] ; Iden ...

  • Samsung S3C9228/P9228 - page 50

    ADDRESSING MODES S3C9228/P9228 3- 10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and ...

  • Samsung S3C9228/P9228 - page 51

    S3C9228/P9228 ADDRESSING MODES 3- 11 DIRECT ADDRESS MODE (C ontinued ) OPCODE Program Memory Upper Address Byte Program Memory Address Used Lower Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3- 11 . Direct Addressing for Call and ...

  • Samsung S3C9228/P9228 - page 52

    ADDRESSING MODES S3C9228/P9228 3- 12 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occ ...

  • Samsung S3C9228/P9228 - page 53

    S3C9228/P9228 CONTROL REGISTERS 4- 1 4 CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing applicati ...

  • Samsung S3C9228/P9228 - page 54

    CONTROL REGISTERS S3C9228/P9228 4- 2 Table 4-1. Sys tem and Peripheral C ontrol Registers (Page 0) Register Name Mnemonic Address (Page 0) R/W Decimal Hex Port 0 Control Register P0CON 235 EBH R/W Port 0 Pull-up Resistor Enable Register P0PUR 236 ECH R/W Port 0 Interrupt Control Register P0INT 237 EDH R/W Port 0 Interrupt Edge Selection Register P0 ...

  • Samsung S3C9228/P9228 - page 55

    S3C9228/P9228 CONTROL REGISTERS 4- 3 Table 4- 1. Sys tem and Peripheral C ontrol Registers (Page 0) Register Name Mnemonic Address (Page 0) R/W Decimal Hex Locations D8H-B9H are not mapped. Timer B Control Register TBCON 202 BAH R/W Timer 1/A Control Register TACON 203 BBH R/W Timer B Data Register TBDATA 204 BCH R/W Timer A Data Register TADATA 20 ...

  • Samsung S3C9228/P9228 - page 56

    CONTROL REGISTERS S3C9228/P9228 4- 4 FLAGS - System Flags Register .7 .6 .5 Bit Identifier RESET RESET Value Read/Write R = Read-only W = Write-only R/W = Read/write ' - ' = Not used Bit number: MSB = Bit 7 LSB = Bit 0 Addressing mode or modes you can use to modify register values Description of the effect of specific bit settings RESET v ...

  • Samsung S3C9228/P9228 - page 57

    S3C9228/P9228 CONTROL REGISTERS 4- 5 AD C ON — A/D Converter Co ntrol Register D 0 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––000000 Read/Write – – R/W R/W R R/W R/W R/W .7-.6 Not used for the S3C9228/P9228 .5- . 4 A/D Input Pin Selection Bits 0 0 AD0 (P1.0) 0 1 AD1 (P1.1) 1 0 AD2 (P1.2) 1 1 AD3 (P1.3) .3 End of Conversi ...

  • Samsung S3C9228/P9228 - page 58

    CONTROL REGISTERS S3C9228/P9228 4- 6 BTC ON — Basic Timer Co ntrol Register DCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7- .4 Watchdog Timer En able Bits 1010 Disable watchdog function Any other value Enable watchdog function .3- .2 Basic Timer Input Clock Selection Bits 0 0 f ...

  • Samsung S3C9228/P9228 - page 59

    S3C9228/P9228 CONTROL REGISTERS 4- 7 CLKCON — System Clock Control Register D4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 Oscillator IRQ Wake-up Function Bit 0 Enable IRQ for main or sub oscillator wake-up in power down mode 1 Disable IRQ for main or sub oscillator wake-up in p ...

  • Samsung S3C9228/P9228 - page 60

    CONTROL REGISTERS S3C9228/P9228 4- 8 FLAGS — System Flags Register D5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value xxxx –––– Read/Write R/W R/W R/W R/W –––– .7 Carry Flag (C) 0 Operation does not generate a carry or borrow condition .6 Zero Flag (Z) 0 Operation result is a non-zero value 1 Operation result is zero .5 ...

  • Samsung S3C9228/P9228 - page 61

    S3C9228/P9228 CONTROL REGISTERS 4- 9 INTPND1 — Interrupt Pending Register 1 D6 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 P1.3's Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) .6 P1.2's Inte ...

  • Samsung S3C9228/P9228 - page 62

    CONTROL REGISTERS S3C9228/P9228 4- 10 INTPND2 — Interrupt Pending Register 2 D7 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––000000 Read/Write – – R/W R/W R/W R/W R/W R/W .7 -.6 Not used for S3C9228/P9228 . 5 P3.1 (INTP) Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is ...

  • Samsung S3C9228/P9228 - page 63

    S3C9228/P9228 CONTROL REGISTERS 4- 11 LMOD — LCD Mode Control Register FE H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –0000000 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6 COM Pins High Impedance Control Bit 0 Normal COMs signal output 1 COM pins are at high impedance .5 Port3 High Impedance Control ...

  • Samsung S3C9228/P9228 - page 64

    CONTROL REGISTERS S3C9228/P9228 4- 12 LPOT — LCD Port Control Register D8 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –0000000 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6-.4 SEG4-SEG19 and COM0-COM3 Selection Bit SEG4-7 SEG8-11 SEG12-15 SEG16-19/ COM7-COM4 COM0-3 P4.0-P4.3 P4.4-P4.7 P5.0-P5.3 P5.4- ...

  • Samsung S3C9228/P9228 - page 65

    S3C9228/P9228 CONTROL REGISTERS 4- 13 OSCCON — Oscillator Control Register D3 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––00–0 Read/Write –––– R/W R/W – R/W .7 -.4 Not used for S3C9228/P9228 .3 Main Oscillator Control Bit 0 Main oscillator RUN 1 Main oscillator STOP .2 Sub Oscillator Control Bit 0 Sub oscill ...

  • Samsung S3C9228/P9228 - page 66

    CONTROL REGISTERS S3C9228/P9228 4- 14 P0CON – Port 0 Control Register EBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P0.3/BUZ/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (BUZ output) .5-.4 P0.2 ...

  • Samsung S3C9228/P9228 - page 67

    S3C9228/P9228 CONTROL REGISTERS 4- 15 P0INT –Port 0 Interrupt Enable Register EDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .2 P0.2's Interrupt Enable Bit 0 Disabl ...

  • Samsung S3C9228/P9228 - page 68

    CONTROL REGISTERS S3C9228/P9228 4- 16 P0PUR –Port 0 Pull-up Resistors Enable Register ECH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .2 P0.2's ...

  • Samsung S3C9228/P9228 - page 69

    S3C9228/P9228 CONTROL REGISTERS 4- 17 P0EDGE –Port 0 Interrupt Edge Selection Register EEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Edge Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .2 P0.2's Inte ...

  • Samsung S3C9228/P9228 - page 70

    CONTROL REGISTERS S3C9228/P9228 4- 18 P1CON – Port 1 Control Register EFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P1.3/AD3/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (ADC mode) .5-.4 P1.2/A ...

  • Samsung S3C9228/P9228 - page 71

    S3C9228/P9228 CONTROL REGISTERS 4- 19 P1INT –Port 1 Interrupt Enable Register F1H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .2 P1.2's Interrupt Enable Bit 0 Disabl ...

  • Samsung S3C9228/P9228 - page 72

    CONTROL REGISTERS S3C9228/P9228 4- 20 P1PUR –Port 1 Pull-up Resistors Enable Register F0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .2 P1.2's ...

  • Samsung S3C9228/P9228 - page 73

    S3C9228/P9228 CONTROL REGISTERS 4- 21 P1EDGE –Port 1 Interrupt Edge Selection Register F2H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Edge Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .2 P1.2's Inte ...

  • Samsung S3C9228/P9228 - page 74

    CONTROL REGISTERS S3C9228/P9228 4- 22 P2CON – Port 2 Control Register F3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P2.3 Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not available .5-.4 P2.2/SI Configuration Bits 0 0 S ...

  • Samsung S3C9228/P9228 - page 75

    S3C9228/P9228 CONTROL REGISTERS 4- 23 P2PUR –Port 2 Pull-up Resistors Enable Register F4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P2.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .2 P2.2's ...

  • Samsung S3C9228/P9228 - page 76

    CONTROL REGISTERS S3C9228/P9228 4- 24 P3CON – Port 3 Control Register F5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3-.2 P3.1/SEG2/INTP Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not ...

  • Samsung S3C9228/P9228 - page 77

    S3C9228/P9228 CONTROL REGISTERS 4- 25 P3INT –Port 3 Interrupt Enable Register F7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .0 P3.0's Interrupt Enable Bit 0 Disa ...

  • Samsung S3C9228/P9228 - page 78

    CONTROL REGISTERS S3C9228/P9228 4- 26 P3PUR –Port 3 Pull-up Resistors Enable Register F6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .0 P3.0' ...

  • Samsung S3C9228/P9228 - page 79

    S3C9228/P9228 CONTROL REGISTERS 4- 27 P3EDGE –Port 3 Interrupt Edge Selection Register F8H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.4 Not used for S3C9228/P9228 .1 P3.1's Interrupt State Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .0 P3.0's I ...

  • Samsung S3C9228/P9228 - page 80

    CONTROL REGISTERS S3C9228/P9228 4- 28 P4CONH – Port 4 Control Register High Byte F9H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P4.7/SEG11 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P4.6/SEG10 Configura ...

  • Samsung S3C9228/P9228 - page 81

    S3C9228/P9228 CONTROL REGISTERS 4- 29 P4CONL –Port 4 Control Register Low Byte FAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P4.3/SEG7 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P4.2/SEG6 Configuration ...

  • Samsung S3C9228/P9228 - page 82

    CONTROL REGISTERS S3C9228/P9228 4- 30 P5CONH – Port 5 Control Register High Byte FBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P5.7/SEG19/COM4 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P5.6/SEG18/COM ...

  • Samsung S3C9228/P9228 - page 83

    S3C9228/P9228 CONTROL REGISTERS 4- 31 P5CONL – Port 5 Control Register Low Byte FCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P5.3/SEG15 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P5.2/SEG14 Configura ...

  • Samsung S3C9228/P9228 - page 84

    CONTROL REGISTERS S3C9228/P9228 4- 32 P6CON – Port 6 Control Register High Byte FDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P6.3/COM0 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P6.2/COM1 Configurati ...

  • Samsung S3C9228/P9228 - page 85

    S3C9228/P9228 CONTROL REGISTERS 4- 33 SIOCON — SIO Control Register E1 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 SIO Shift Clock Selection Bit 0 Internal clock ( P.S clock) 1 External clock (SCK) .6 Data Direction Control Bit 0 MSB-first mode 1 LSB-first mode . 5 SIO Mode S ...

  • Samsung S3C9228/P9228 - page 86

    CONTROL REGISTERS S3C9228/P9228 4- 34 STPCON – Stop Control Register E0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 Stop Control Bits 1 0100101 Enable Stop instruction Other values Disable Stop instruction NOTE: Before executing the STOP instruction, the STPCON register must be ...

  • Samsung S3C9228/P9228 - page 87

    S3C9228/P9228 CONTROL REGISTERS 4- 35 SYM — System Mode Register DFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 Global Interrupt Enable Bit 0 G lobal interrupt processing disable (DI instruction) 1 G lobal interrupt processing enable (EI ins ...

  • Samsung S3C9228/P9228 - page 88

    CONTROL REGISTERS S3C9228/P9228 4- 36 T A CON — Timer 1/A Control Register BBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0 000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 Timer 1 Mode Selection Bit 0 Two 8-bit timers mode (Timer A/B) 1 One 16-bit timer mode (Timer 1) .6-.4 Timer 1/A Clock Selection Bits 000 fxx/512 001 fxx/ ...

  • Samsung S3C9228/P9228 - page 89

    S3C9228/P9228 CONTROL REGISTERS 4- 37 T B CON — Timer B Control Register BA H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –000000– Read/Write – R/W R/W R/W R/W R/W R/W – .7 Not used for S3C9228/P9228 .6-.4 Timer B Clock Selection Bits 000 fxx/512 001 fxx/256 010 fxx/64 011 fxx/8 100 fxx (system clock) 101 fxt (sub clock) .3 T ...

  • Samsung S3C9228/P9228 - page 90

    CONTROL REGISTERS S3C9228/P9228 4- 38 WTCON — Watch Timer Control Register DA H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 Watch Timer Clock Selection Bit 0 Select main clock divided by 2 7 (fx/128) 1 Select sub clock ( fxt) .6 Watch Timer Interrupt Enable Bit 0 Disable watch ...

  • Samsung S3C9228/P9228 - page 91

    S3C9228/P9228 INTERRUPT STRUCTURE 5- 1 5 INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H. SOURCES VECTOR S1 S2 S3 Sn 0000H 0001H NOTES: 1. The SAM88RCRI interrupt h ...

  • Samsung S3C9228/P9228 - page 92

    INTERRUPT STRUCTURE S3C9228/P9228 5- 2 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87 RCR I ...

  • Samsung S3C9228/P9228 - page 93

    S3C9228/P9228 INTERRUPT STRUCTURE 5- 3 INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source&apos ...

  • Samsung S3C9228/P9228 - page 94

    INTERRUPT STRUCTURE S3C9228/P9228 5- 4 S3C9228/P9228 INTERRUPT STRUCTURE The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources: — Timer 1/A interr upt — Timer B interrupt — SIO interrupt — Watch Timer interrupt — Four external interrupts for port 0 — Four external interrupts for port 1 — Two external interrupts f ...

  • Samsung S3C9228/P9228 - page 95

    S3C9228/P9228 INTERRUPT STRUCTURE 5- 5 SYM.3 (EI, DI) P0INT.0 P0.0 External Interript P0INT.1 P0.1 External Interript P0.3 External Interript P0.2 External Interript P0INT.2 P0INT.3 INTPND1.0 INTPND1.1 INTPND1.2 INTPND1.3 P1.0 External Interript P1INT.0 P1.2 External Interript P1.3 External Interrupt P1.1 External Interript P1INT.1 P1INT.2 P1INT.3 ...

  • Samsung S3C9228/P9228 - page 96

    INTERRUPT STRUCTURE S3C9228/P9228 5- 6 Programming Tip — How to clear an interrupt pending bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD INTPND1, #11111011B ; Clear P0.2's interrupt pending bit • • • IRET 2. L D INTPND2, #11110111B ; Clear watch timer inter ...

  • Samsung S3C9228/P9228 - page 97

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 1 6 SAM8 8RC R I INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8- bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers ar ...

  • Samsung S3C9228/P9228 - page 98

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 2 Table 6- 1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDC dst,src Load program memory LDE dst,src Load external data memory LDCD dst,src Load program memory and decrement LDED dst,src Load external data memory and decrement LDCI dst,src Load ...

  • Samsung S3C9228/P9228 - page 99

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 3 Table 6- 1 . Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL dst Call procedure IRET Interrupt return JP cc,dst Jump on condition code JP dst Jump unconditional JR cc,dst Jump relative on condition code RET Return Bit Manipulation Instructions TCM ...

  • Samsung S3C9228/P9228 - page 100

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 4 FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 – FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect ...

  • Samsung S3C9228/P9228 - page 101

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 5 INSTRUCTION SET NOTATION Table 6- 2 . Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined Table 6- 3 . Instruction Set Symbols Sy ...

  • Samsung S3C9228/P9228 - page 102

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 6 Table 6- 4 . Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6- 6. r Working register only Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, ..., 14) R Register or working register reg or Rn ( reg = 0–255, n = 0 ...

  • Samsung S3C9228/P9228 - page 103

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 7 Table 6- 5 . Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0123456 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM P 2 INC R1 INC IR1 SUB r1,r2 SUB r1,Ir2 SUB R2,R1 SUB IR2,R1 SUB R1,IM E 3 JP I ...

  • Samsung S3C9228/P9228 - page 104

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 8 Table 6- 5 . Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 JR cc,RA LD r1,IM JP cc,DA INC r1 P 1 ↓↓ ↓↓↓↓ P 2 E 3 R 4 5 N 6 IDLE I 7 ↓↓ ↓↓↓↓ STOP B 8 DI B 9 EI L A RE T E B IRET C RCF H D ↓↓ ↓↓↓↓ SCF E E CCF ...

  • Samsung S3C9228/P9228 - page 105

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 9 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two ...

  • Samsung S3C9228/P9228 - page 106

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 10 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction ...

  • Samsung S3C9228/P9228 - page 107

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 11 ADC — Add With Carry ADC dst,src Operation: dst ¨ dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed. In m ...

  • Samsung S3C9228/P9228 - page 108

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 12 ADD — Add ADD dst,src Operation: dst ¨ dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of ...

  • Samsung S3C9228/P9228 - page 109

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 13 AND — Logical AND AND dst,src Operation: dst ¨ dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ...

  • Samsung S3C9228/P9228 - page 110

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 14 CALL — Call Procedure CALL dst Operation: SP ¨ SP – 1 @SP ¨ PCL SP ¨ SP –1 @SP ¨ PCH PC ¨ dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified ...

  • Samsung S3C9228/P9228 - page 111

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 15 CCF — Complement Carry Flag CCF Operation: C ¨ NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Form ...

  • Samsung S3C9228/P9228 - page 112

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 16 CLR — Clear CLR dst Operation: dst ¨ "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 B0 R 4 B1 IR Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR 00H → ...

  • Samsung S3C9228/P9228 - page 113

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 17 COM — Complement COM dst Operation: dst ¨ NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the resu ...

  • Samsung S3C9228/P9228 - page 114

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 18 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred ( src > dst); cl ...

  • Samsung S3C9228/P9228 - page 115

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 19 DEC — Decrement DEC dst Operation: dst ¨ dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, dst ...

  • Samsung S3C9228/P9228 - page 116

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 20 DI — Disable Interrupts DI Operation: SYM (2) ¨ 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt ...

  • Samsung S3C9228/P9228 - page 117

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 21 EI — Enable Interrupts EI Operation: SYM (2) ¨ 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction ...

  • Samsung S3C9228/P9228 - page 118

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 22 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src ...

  • Samsung S3C9228/P9228 - page 119

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 23 INC — Increment INC dst Operation: dst ¨ dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is dst ...

  • Samsung S3C9228/P9228 - page 120

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 24 IRET — Interrupt Return IRET IRET Operation: FLAGS ¨ @SP SP ¨ SP + 1 PC ¨ @SP SP ¨ SP + 2 SYM(2) ¨ 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. Flags: All flags are restored to ...

  • Samsung S3C9228/P9228 - page 121

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 25 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ¨ dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction ...

  • Samsung S3C9228/P9228 - page 122

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 26 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ¨ PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction followi ...

  • Samsung S3C9228/P9228 - page 123

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 27 LD — Load LD dst,src Operation: dst ¨ src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src dst | opc src 2 4 rC r IM 4 r8 r R src | opc dst 2 4 r9 R r r = 0 to F ...

  • Samsung S3C9228/P9228 - page 124

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 28 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD R0,#10H → R0 = 10H LD R0,01H → R0 = 20H, register 01H = 20H LD 01H,R0 → Register 01H = 01H, R0 = 01H LD R1,@R0 → R1 = 20H, R0 = 01H ...

  • Samsung S3C9228/P9228 - page 125

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 29 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ¨ src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes ' Irr' or ' rr&apos ...

  • Samsung S3C9228/P9228 - page 126

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 30 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 110 ...

  • Samsung S3C9228/P9228 - page 127

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 31 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ¨ src rr ¨ rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The cont ...

  • Samsung S3C9228/P9228 - page 128

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 32 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ¨ src rr ¨ rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents ...

  • Samsung S3C9228/P9228 - page 129

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 33 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typic ally, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 FF Example: When th ...

  • Samsung S3C9228/P9228 - page 130

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 34 OR — Logical OR OR dst,src Operation: dst ¨ dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the correspondi ...

  • Samsung S3C9228/P9228 - page 131

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 35 POP — Pop From Stack POP dst Operation: dst ¨ @SP SP ¨ SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 8 50 R 8 51 ...

  • Samsung S3C9228/P9228 - page 132

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 36 PUSH — Push To Stack PUSH src Operation: SP ¨ SP – 1 @SP ¨ src A PUSH instruction decrements the stack pointer value and loads the contents of the source ( src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No f ...

  • Samsung S3C9228/P9228 - page 133

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 37 RCF — Reset Carry Flag RCF RCF Operation: C ¨ 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 CF Example: Given: C = "1" or "0": The instruct ...

  • Samsung S3C9228/P9228 - page 134

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 38 RET — Return RET Operation: PC ¨ @SP SP ¨ SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next st ...

  • Samsung S3C9228/P9228 - page 135

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 39 RL — Rotate Left RL dst Operation: C ¨ dst (7) dst (0) ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value o f bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. C 7 0 Flags: C: Set ...

  • Samsung S3C9228/P9228 - page 136

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 40 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ¨ C C ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag rep ...

  • Samsung S3C9228/P9228 - page 137

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 41 RR — Rotate Right RR dst Operation: C ¨ dst (0) dst (7) ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The content s of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). C 7 0 Flags: C: Set i ...

  • Samsung S3C9228/P9228 - page 138

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 42 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ¨ C C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry fl ...

  • Samsung S3C9228/P9228 - page 139

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 43 SBC — Subtract With Carry SBC dst,src Operation: dst ¨ dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed ...

  • Samsung S3C9228/P9228 - page 140

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 44 SCF — Set Carry Flag SCF Operation: C ¨ 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to logic one. ...

  • Samsung S3C9228/P9228 - page 141

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 45 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ¨ dst (7) C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is perform ed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and i ...

  • Samsung S3C9228/P9228 - page 142

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 46 STOP — Stop Operation STOP Operation: The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be ...

  • Samsung S3C9228/P9228 - page 143

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 47 SUB — Subtract SUB dst,src Operation: dst ¨ dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the d ...

  • Samsung S3C9228/P9228 - page 144

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 48 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src Thi s instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM stat ...

  • Samsung S3C9228/P9228 - page 145

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 49 TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the dest ...

  • Samsung S3C9228/P9228 - page 146

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 50 XOR — Logical Exclusive OR XOR dst,src Operation: dst ¨ dst XOR src The source operand is logically exclusive- ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the ...

  • Samsung S3C9228/P9228 - page 147

    S3C9228/P9228 CLOCK CIRCUITS 7- 1 7 CLOCK CIRCUITS OVERVIEW The S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency, is determined by CLKCON register settings . SYSTEM CLOCK C ...

  • Samsung S3C9228/P9228 - page 148

    CLOCK CIRCUITS S3C9 228/P9228 7- 2 MAIN OSCILLATOR CIRCUITS X IN X OUT Figure 7-1. Crystal/Ceramic Oscillator X IN X OUT Figure 7-2. External Oscillator X IN X OUT R Figure 7-3. RC Oscillator SUB OSCILLATOR CIRCUITS XT IN XT OUT 32.768 kHz Figure 7-4. Crystal/Ceramic Oscillator XT IN XT OUT Figure 7-5. External Oscillator ...

  • Samsung S3C9228/P9228 - page 149

    S3C9228/P9228 CLOCK CIRCUITS 7- 3 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is ...

  • Samsung S3C9228/P9228 - page 150

    CLOCK CIRCUITS S3C9 228/P9228 7- 4 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following functions: — Oscillator IRQ wake-up function enable/disable — Oscillator frequency divide-by value CLKCON register settings control whether or not an e ...

  • Samsung S3C9228/P9228 - page 151

    S3C9228/P9228 CLOCK CIRCUITS 7- 5 OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the following functions: — System clock selection — Main oscillator control — Sub oscillator control OSCCON.0 register settings select Main clock or Sub clock as system ...

  • Samsung S3C9228/P9228 - page 152

    CLOCK CIRCUITS S3C9 228/P9228 7- 6 SWITCHING THE CPU CLOCK Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating fr ...

  • Samsung S3C9228/P9228 - page 153

    S3C9228/P9228 CLOCK CIRCUITS 7- 7 STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: — Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values". If necessary, you c ...

  • Samsung S3C9228/P9228 - page 154

    CLOCK CIRCUITS S3C9 228/P9228 7- 8 NOTES ...

  • Samsung S3C9228/P9228 - page 155

    S3C9228/P9228 RESET RESET and POWER-DOWN 8- 1 8 RESET RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, the voltage at V DD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C9228/P9228 i ...

  • Samsung S3C9228/P9228 - page 156

    RESET RESET and POWER-DOWN S3C9228 /P9228 8- 2 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. But the watch timer and LCD controller will not ...

  • Samsung S3C9228/P9228 - page 157

    S3C9228/P9228 RESET RESET and POWER-DOWN 8- 3 Using an Internal Interrupt to Release Stop Mode An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release stop mode. That ...

  • Samsung S3C9228/P9228 - page 158

    RESET RESET and POWER-DOWN S3C9228 /P9228 8- 4 HARDWARE RESET RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these table to represent specific RESET values: — A "1" or ...

  • Samsung S3C9228/P9228 - page 159

    S3C9228/P9228 RESET RESET and POWER-DOWN 8- 5 Table 8-1. Register Values after RESET RESET (Continued) Register Name Mnemonic Address Bit Values after RESET RESET Dec Hex 76543210 System Mode Register SYM 223 DFH ––––0000 STOP Control Register STPCON 224 E0H 00000000 SIO Control Register SIOCON 225 E1H 0000000– SIO Data Register SIODATA 2 ...

  • Samsung S3C9228/P9228 - page 160

    RESET RESET and POWER-DOWN S3C9228 /P9228 8- 6 NOTES ...

  • Samsung S3C9228/P9228 - page 161

    S3C9228/P9228 I/O P ORTS 9- 1 9 I/O PORTS OVERVIEW The S3C9228/P9228 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports. This gives a total of 36 I/O pins. Each port can be flexibly configured to meet application d ...

  • Samsung S3C9228/P9228 - page 162

    I/O PORTS S3C9228/P 9228 9- 2 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Mnemonic Decimal Hex R/W Port 0 data register P0 228 ...

  • Samsung S3C9228/P9228 - page 163

    S3C9228/P9228 I/O P ORTS 9- 3 PORT 0 Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0. P0.0-P0.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following fu ...

  • Samsung S3C9228/P9228 - page 164

    I/O PORTS S3C9228/P 9228 9- 4 Port 0 Control Register (P0CON) EBH, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P0.3/BUZ (INT) P0CON bit-pair pin configuration settings: 00 01 10 11 N-channel open-drain output mode Alternative function (TAOUT, BUZ) P0.2 (INT) P0.1/T1CLK (INT) P0.0/TAOUT (INT) Push-pull output mode Schmitt trigger input mode (T1CLK) ...

  • Samsung S3C9228/P9228 - page 165

    S3C9228/P9228 I/O P ORTS 9- 5 Port 0 Interrupt Pending Bits (INTPND1.3-.0) D6H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB INTPND1 bit configuration settings: 0 1 P0.3 (INT) Interrupt is pending (when read) No interrupt pending (when read), clear pending bit (when write) P0.2 (INT) P0.1 (INT) P0.0 (INT) P1.3 (INT) P1.2 (INT) P1.1 (INT) P1.0 (INT) ...

  • Samsung S3C9228/P9228 - page 166

    I/O PORTS S3C9228/P 9228 9- 6 PORT 1 Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0. P1.0-P1.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following fu ...

  • Samsung S3C9228/P9228 - page 167

    S3C9228/P9228 I/O P ORTS 9- 7 Port 1 Interrupt Control Register (P1INT) F1H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used P1INT bit configuration settings: 0 1 P1.3 (INT) Enable interrupt Disable interrupt P1.2 (INT) P1.1 (INT) P1.0 (INT) Figure 9-8. Port 1 Interrupt Control Register (P1INT) Port 1 Interrupt Pending Bits (INTPND1.7-.4) D6H, ...

  • Samsung S3C9228/P9228 - page 168

    I/O PORTS S3C9228/P 9228 9- 8 Port 1 Interrupt Edge Selection Register (P1EDGE) F2H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P1EDGE bit configuration settings: 0 1 P1.3 (INT) Rising edge detection Falling edge detection P1.2 (INT) P1.1 (INT) P1.0 (INT) Not used Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE) Port 1 Pull-up Contro ...

  • Samsung S3C9228/P9228 - page 169

    S3C9228/P9228 I/O P ORTS 9- 9 PORT 2 Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0. P2.0-P2.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following fu ...

  • Samsung S3C9228/P9228 - page 170

    I/O PORTS S3C9228/P 9228 9- 10 Port 2 Pull-up Control Register (P2PUR) F4H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P2PUR bit configuration settings: 0 1 Enable pull-up resistor Disable pull-up resistor Not used P2.3 P2.2 P2.1 P2.0 Figure 9-13. Port 2 Pull-up Control Register (P2PUR) ...

  • Samsung S3C9228/P9228 - page 171

    S3C9228/P9228 I/O P ORTS 9- 11 PORT 3 Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0. P3.0-P3.1 can serve as inputs (with or without pull- up, and high impedance input), as outputs (push-pull or open-drain) or you can be ...

  • Samsung S3C9228/P9228 - page 172

    I/O PORTS S3C9228/P 9228 9- 12 Port 3 Interrupt Control Register (P3INT) F7H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used P3INT bit configuration settings: 0 1 Enable interrupt Disable interrupt P3.1 (INTP) P3.0 (INTP) Figure 9-15. Port 3 Interrupt Control Register (P3INT) Port 3 Interrupt Pending Bits (INTPND2.5-.4) D7H, Page 0, R/W .7 .6 ...

  • Samsung S3C9228/P9228 - page 173

    S3C9228/P9228 I/O P ORTS 9- 13 Port 3 Interrupt Edge Selection Register (P3EDGE) F8H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P3EDGE bit configuration settings: 0 1 Rising edge detection Falling edge detection P3.1 (INTP) P3.0 (INTP) Not used Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE) Port 3 Pull-up Control Register (P3PUR) ...

  • Samsung S3C9228/P9228 - page 174

    I/O PORTS S3C9228/P 9228 9- 14 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port ...

  • Samsung S3C9228/P9228 - page 175

    S3C9228/P9228 I/O P ORTS 9- 15 PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port ...

  • Samsung S3C9228/P9228 - page 176

    I/O PORTS S3C9228/P 9228 9- 16 PORT 6 Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port ...

  • Samsung S3C9228/P9228 - page 177

    S3C9228/P9228 ( Preliminary Spec ) BASIC TIMER 10- 1 10 BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a stop mode release. The func ...

  • Samsung S3C9228/P9228 - page 178

    BASIC TIMER S3C9228 /P9228 ( Preliminary Spec ) 10- 2 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH, and is read/write addres ...

  • Samsung S3C9228/P9228 - page 179

    S3C9228/P9228 ( Preliminary Spec ) BASIC TIMER 10- 3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to “00H”, automat ...

  • Samsung S3C9228/P9228 - page 180

    BASIC TIMER S3C9228 /P9228 ( Preliminary Spec ) 10- 4 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). MUX f XX /4096 DIV f XX /1024 f XX /128 f XX /16 f XX Bits 3, 2 Bit 0 Basic Timer Control Register (Write '1010xxxxB' to D ...

  • Samsung S3C9228/P9228 - page 181

    S3C9228/P9228 TIMER 1 11- 1 11 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers. — One 16-bit tim er mode (Timer 1) — Two 8-bit timers mode ...

  • Samsung S3C9228/P9228 - page 182

    TIMER 1 S3C9228/P922 8 11- 2 Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to — Enable the timer 1 operating (interval timer) — Select the timer 1 input clock frequency — Clear the timer 1 counter, TACNT and TBCNT — Enable the timer 1 interrupt TACON is located in page 0, at address BBH, and is read/write add ...

  • Samsung S3C9228/P9228 - page 183

    S3C9228/P9228 TIMER 1 11- 3 NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) TACON.6-.4 M U X 1/8 1 /64 1 /256 1 /512 INTPND2.0 TAOUT T1INT 1/1 DIV R fxt T1CLK (X IN or XT IN ) fxx BTCON.0 TACON.2 TBCNT TACNT 16-Bit Comparator TBDATA Buffer TADATA Buffer TBDATA TADATA LSB MSB LSB MSB Match Signal Counter clear signal TACON.1 ...

  • Samsung S3C9228/P9228 - page 184

    TIMER 1 S3C9228/P922 8 11- 4 TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively. Timer A and B have the following functional components: — Clock frequency divider with multiplexer – ...

  • Samsung S3C9228/P9228 - page 185

    S3C9228/P9228 TIMER 1 11- 5 TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer A cou ...

  • Samsung S3C9228/P9228 - page 186

    TIMER 1 S3C9228/P922 8 11- 6 Timer B Control Register (TBCON) BAH, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Timer B match interrupt enable bit: 0 = Disable match interrupt 1 = Enable match interrupt Not used Timer B count enable bit: 0 = Disable counting operating 1 = Enable counting operating Timer B counter clear bit: 0 = No effect 1 = Clear the timer ...

  • Samsung S3C9228/P9228 - page 187

    S3C9228/P9228 TIMER 1 11- 7 FUNCTION DESCRIPTION Interval Timer Function (Timer A and Timer B) The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). The timer A match interrupt pending condition (INTPND2.0) and the timer B match interrupt pending condition (INTPND2.1) must b ...

  • Samsung S3C9228/P9228 - page 188

    TIMER 1 S3C9228/P922 8 11- 8 NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) TACON.6-.4 M U X 1/8 1 /64 1 /256 1 /512 INTPND2.0 TAOUT TAINT DIV R fxt T1CLK/ P0.1 (X IN or XT IN ) fxx BTCON.0 TACON.2 8-Bit Comparator TADATA Buffer TADATA Register LSB MSB LSB MSB Match Signal Counter Clear Signal TACON.1 Match R TACON.3 Data B ...

  • Samsung S3C9228/P9228 - page 189

    S3C9228/P9228 TIMER 1 11- 9 1/1 1/8 1 /64 1 /256 1 /512 NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) TBCON.6-.4 M U X INTPND2.1 TBINT DIV R fxt (X IN or XT IN ) fxx BTCON.0 TBCON.2 8-Bit Comparator TBDATA Buffer TBDATA Register LSB MSB LSB MSB Match Signal Counter Clear Signal TBCON.1 Match R TBCON.3 Data Bus Data Bus TBC ...

  • Samsung S3C9228/P9228 - page 190

    TIMER 1 S3C9228/P922 8 11- 10 NOTES ...

  • Samsung S3C9228/P9228 - page 191

    S3C9228/P9228 WATCH TIMER 12- 1 12 WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt, then set the WTCON.6 ...

  • Samsung S3C9228/P9228 - page 192

    WATCH TIMER S3C922 8/P9228 12- 2 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode. ...

  • Samsung S3C9228/P9228 - page 193

    S3C9228/P9228 WATCH TIMER 12- 3 WATCH TIMER CIRCUIT DIAGRAM WT INT Enable WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 WTCON.6 Enable/Disable Selector Circuit MUX INTPND2.3 WTINT WTCON.6 f W /2 15 f W /2 14 f W /2 13 f W /2 7 f W /64 (0.5 kHz) f W /32 (1 kHz) f W /16 (2 kHz) f W /8 (4 kHz) (1 Hz) f X = Main clock (where fx = 4.19 MHz) fxt = Sub clock (3 ...

  • Samsung S3C9228/P9228 - page 194

    WATCH TIMER S3C922 8/P9228 12- 4 NOTES ...

  • Samsung S3C9228/P9228 - page 195

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 1 13 LCD CONTROLLER/DRIV ER OVERVIEW The S3C9228/P9228 microcontroller can directly drive an up-to- 128 -dot ( 16 segments x 8 commons) LCD panel. Its LCD block has the following components: — LCD control ler/driver — Display RAM for storing display data — 16 segment output pins (SEG0 – SEG 15 ) — ...

  • Samsung S3C9228/P9228 - page 196

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 2 LCD CIRCUIT DIAGRAM SEG15/P5.3 COM4/SEG19/P5.7 COM7/SEG16/P5.4 160 16 Data BUS Port Latch LPOT Display RAM (Page1) Port Latch Port Latch Timing Controller MUX SEG Control or Selector COM Control or selector f LCD SEG0/P2.1 COM3/P6.0 COM0/P6.3 COM Control LCD Voltage Control Port 3 Control P3.1/INTP/SEG2 P3. ...

  • Samsung S3C9228/P9228 - page 197

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 3 LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0–SEG 19 using a direct m ...

  • Samsung S3C9228/P9228 - page 198

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 4 LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode. It has the following control functions. — LCD duty and bias selection — LCD clock selection — LCD display control — COMs signal output control — P3 high imped ...

  • Samsung S3C9228/P9228 - page 199

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 5 LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET , a LPOT values are cleared to "0". LCD Port Control Register D8H, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used SEG0/P2.1 selection bit: 0 = SEG port 1 = Normal I/ ...

  • Samsung S3C9228/P9228 - page 200

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 6 LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS 1/4 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS 1/3 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS Figure 13-6. Internal Voltage Dividin ...

  • Samsung S3C9228/P9228 - page 201

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 7 1 Frame FR V DD V SS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM1 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 SEG0 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 COM2 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 COM0 V LC2 ( V LC3 ) V LC4 V SS V DD V LC1 SEG0-COM0 + V DD 0V + 1/4V LCD -V LCD - 1/4V LCD 0 1 2 3 7 4 6 5 0 1 2 3 7 4 ...

  • Samsung S3C9228/P9228 - page 202

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 8 1 Frame V DD V SS 0 1 2 3 0 1 2 3 COM1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM2 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM3 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG0 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM0-SEG0 + V LCD COM0 V SS V DD V LC1 ...

  • Samsung S3C9228/P9228 - page 203

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 9 1 Frame V DD V SS 0 1 2 COM1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM2 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG0 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM0-SEG0 + V LCD COM0 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) + 1/3 V LCD 0V - 1/3 V LCD - V ...

  • Samsung S3C9228/P9228 - page 204

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 10 NOTES ...

  • Samsung S3C9228/P9228 - page 205

    S3C9228/P9228 A/D C ONVERTER 14- 1 14 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10 -bit digital values. The an alog input level must lie between the AV REF and AV SS values. The A/D converter ...

  • Samsung S3C9228/P9228 - page 206

    A/D CONVERTER S3C9 228/P9228 14- 2 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is ...

  • Samsung S3C9228/P9228 - page 207

    S3C9228/P9228 A/D C ONVERTER 14- 3 Conversion Data Register ADDATAH/ADDATAL D1H/D2H, Page 0, Read Only .9 .8 .7 .6 .5 .4 .3 .2 MSB LSB (ADDATAH) ------ .1 .0 MSB LSB (ADDATAL) Figure 14-2. A/D Converter Data Register (ADDATAH/ADDATAL) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the refe ...

  • Samsung S3C9228/P9228 - page 208

    A/D CONVERTER S3C9 228/P9228 14- 4 S3C9228 AD0-AD3 Analog Input Pin V DD 101 C (V SS ≤ ADC input ≤ V DD ) Figure 14-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy ...

  • Samsung S3C9228/P9228 - page 209

    S3C9228/P9228 SERIAL I/O INTERFACE 1 5- 1 15 SERIAL I/O INTERFAC E OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: — 8-bit control register (S IOCON ) — Clock selector logic — 8-bit data buffer (SIODATA) — 8-bit prescaler (SIOPS ...

  • Samsung S3C9228/P9228 - page 210

    SERIAL I/O INTERFACE S3C9228/P9228 15- 2 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0. It has the control setting for SIO module. — Clock source selection (internal or external) for shift clock — Interrupt enable — Edge selection for shift operation — Clear 3-bit co ...

  • Samsung S3C9228/P9228 - page 211

    S3C9228/P9228 SERIAL I/O INTERFACE 1 5- 3 SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0. The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/( Prescaler value + 1), or SCK inp ...

  • Samsung S3C9228/P9228 - page 212

    SERIAL I/O INTERFACE S3C9228/P9228 15- 4 SERIAL I/O TIMING DIAGRAM (SIO) SO Transmit Complete SIO INT Set SIOCON.3 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI SCK Figure 15-4 . Serial I/O Timing in Transmit/Receive Mode ( Tx at falling, SIOCON.4 = 0) SIO INT DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK ...

  • Samsung S3C9228/P9228 - page 213

    S3C9228/P9228 ELECT RICAL DATA 16- 1 16 ELECTRICAL DATA OVERVIEW In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supp ly voltage in Stop mode — Stop mode release timi ...

  • Samsung S3C9228/P9228 - page 214

    ELECTRICAL DATA S3C 9228/P9228 16- 2 Table 16-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – – 0.3 to + 6.5 V Input voltage V IN Ports 0 –6 – 0.3 to V DD + 0.3 V Output voltage V O – – 0.3 to V DD + 0.3 V Output current High I OH One I/O pin active – 15 mA All I/O pins active ...

  • Samsung S3C9228/P9228 - page 215

    S3C9228/P9228 ELECT RICAL DATA 16- 3 Table 16-2. D.C. Electrical Characteristics (Continued) (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input Low leakage current I LIL1 V I = 0 V; All input pins except RESET , X OUT , XT IN , XT OUT – – –3 µ A I LIL2 V I = 0 V; X IN , X OUT , XT IN , ...

  • Samsung S3C9228/P9228 - page 216

    ELECTRICAL DATA S3C 9228/P9228 16- 4 Table 16-2. D.C. Electrical Characteristics (Concluded) (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 Run mode: V DD = 5 V ± 10% 8.0 MHz – 6.0 12.0 mA Crystal oscillator C1 = C2 = 22pF 4.19 MHz 3.0 6.0 V DD = 3 V ± 10% 8.0 MHz 2. ...

  • Samsung S3C9228/P9228 - page 217

    S3C9228/P9228 ELECT RICAL DATA 16- 5 Table 16-3. Data Retention Supply Voltage in Stop Mode (T A = – 25 ° C to + 85 ° C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR – 2.0 – 5.5 V Data retention supply current I DDDR Stop mode, T A = 25 ° C V DDDR = 2.0 V ––1 µA Execution of STOP Instruction Idle M ...

  • Samsung S3C9228/P9228 - page 218

    ELECTRICAL DATA S3C 9228/P9228 16- 6 Execution of STOP Instrction RESET Occurs ~ ~ V DDDR ~ ~ Stop Mode Oscillation Stabilization TIme Normal Operating Mode Data Retention Mode t WAIT RESET V DD 0.2 V DD 0.8 V DD NOTE: t WAIT is the same as 16 × 1/BT clock. Figure 16-2. Stop Mode Release Timing When Initiated by a RESET RESET Table 16-4. Input/Out ...

  • Samsung S3C9228/P9228 - page 219

    S3C9228/P9228 ELECT RICAL DATA 16- 7 Table 16-5. A.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit SCK cycle time t KCY External SCK source 1,000 – – ns Internal SCK source 1,000 SCK high, low width t KH , t KL External SCK source 500 Internal SCK source t KCY /2 ...

  • Samsung S3C9228/P9228 - page 220

    ELECTRICAL DATA S3C 9228/P9228 16- 8 Table 16-6. A/D Converter Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.7 V to 5.5 V, V SS = 0 V) Parameter Symbol Conditions Min Typ Max Unit Resolution – 10 – bit Total accuracy VDD = 5.12 V – – ± 3 LSB Integral linearity error ILE fxx = 8 MHz – – ± 2 Differential linearity ...

  • Samsung S3C9228/P9228 - page 221

    S3C9228/P9228 ELECT RICAL DATA 16- 9 RESET t RSL 0.2 V DD Figure 16-4. Input Timing for RESET RESET t KH t KL 0.2V DD SCK t KCY 0.8V DD 0.8V DD 0.2V DD t SIK t KSI SI SO t KSO Output Data Figure 16-5. Serial Data Transfer Timing ...

  • Samsung S3C9228/P9228 - page 222

    ELECTRICAL DATA S3C 9228/P9228 16- 10 Table 16-7. Main Oscillation Characteristics (T A = – 25 ° C to + 85 ° C) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal X IN C1 X OUT Main oscillation frequency 2.7 V – 5.5 V 0.4 – 8 MHz 2.0 V – 5.5 V 0.4 – 4 Ceramic Oscillator X IN C1 X OUT Main oscillation frequ ...

  • Samsung S3C9228/P9228 - page 223

    S3C9228/P9228 ELECT RICAL DATA 16- 11 Table 16-9. Main Oscillation Stabilization Time (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal fx > 1 MHz – – 30 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage ranage. – – 10 ms External clock ...

  • Samsung S3C9228/P9228 - page 224

    ELECTRICAL DATA S3C 9228/P9228 16- 12 Table 16-10. Sub Oscillation Stabilization Time (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal – – – 10 s External clock XT IN input high and low width (t XH , t XL ) 5 – 15 µ s t XTH t XTL V DD -0.1 V 0.1 V XT IN 1/fxt Figure 16-7. Clock Timi ...

  • Samsung S3C9228/P9228 - page 225

    S3C9228/P9228 ELECT RICAL DATA 16- 13 2 MHz 6.25 kHz (main)/8.2 kHz(sub) 1 2 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 MHz Instruction Clock 8 MHz 4 MHz fx (Main/Sub oscillation frequency) 400 kHz 2.7 5.5 400 kHz (main)/32.8 kHz(sub) Figure 16-8. Operating Voltage Range ...

  • Samsung S3C9228/P9228 - page 226

    ELECTRICAL DATA S3C 9228/P9228 16- 14 NOTES ...

  • Samsung S3C9228/P9228 - page 227

    S3C9228/P9228 MECHANICAL DATA 1 7- 1 17 MECHANICAL DATA OVERVIEW The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package. NOTE : Dimensions are in millimeters. 39.50 MAX 39.10 ± 0 .2 0.50 ± 0.1 1.78 (1.77) 0.51 MIN 3.30 ± 0.3 3.50 ± 0.2 5.08 MAX 42-SDIP-600 0-15 1.00 ± 0.1 0.25 + 0.1 - 0.05 15.24 14.00 ...

  • Samsung S3C9228/P9228 - page 228

    MECHANICAL DATA S3C9228/P9228 1 7- 2 44-QFP-1010B #44 NOTE : Dimensions are in millimeters. 10.00 ± 0.2 13.20 ± 0.3 10.00 ± 0.2 13.20 ± 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 MAX 0.80 ± 0.20 0.05 MIN 2.05 ± 0.10 2.30 MAX 0.15 + 0.10 - 0.05 0-8 Figure 17-2. 44-QFP-1010B Package Dimensions ...

  • Samsung S3C9228/P9228 - page 229

    S3C9228/P9228 S3P9228 OTP 18- 1 18 S3P9228 OTP OVERVIEW The S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9228 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9228 is fully compatible with the S3C9228, both in function and in pin co ...

  • Samsung S3C9228/P9228 - page 230

    S3P9228 OTP S3C9228/P9228 18- 2 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT SDAT /P1.2/AD2/INT SCLK /P1.3/AD3/INT V DD /V DD V SS /V SS X OUT X IN V PP /TEST XT IN XT OUT RESET RESET / RESET P2.3 P2.2/SI SEG0/P2.1/SO S3C9228 (42-SDIP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 COM2/P6 ...

  • Samsung S3C9228/P9228 - page 231

    S3C9228/P9228 S3P9228 OTP 18- 3 Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P1.2 SDAT 3 (9) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. P1.3 SCLK 4 (10) I/O Serial clock pin. Input on ...

  • Samsung S3C9228/P9228 - page 232

    S3P9228 OTP S3C9228/P9228 18- 4 Table 18-4. D.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 Run mode: V DD = 5 V ± 10% 8.0 MHz – 6.0 12.0 mA Crystal oscillator C1 = C2 = 22pF 4.19 MHz 3.0 6.0 V DD = 3 V ± 10% 8.0 MHz 2.5 5.0 4.19 MHz 1. ...

  • Samsung S3C9228/P9228 - page 233

    S3C9228/P9228 S3P9228 OTP 18- 5 2 MHz 6.25 kHz (main)/8.2 kHz(sub) 1 2 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 MHz Instruction Clock 8 MHz 4 MHz fx (Main/Sub oscillation frequency) 400 kHz 2.7 5.5 400 kHz (main)/32.8 kHz(sub) Figure 18-3. Standard Operating Voltage Range ...

  • Samsung S3C9228/P9228 - page 234

    S3P9228 OTP S3C9228/P9228 18- 6 NOTES ...

  • Samsung S3C9228/P9228 - page 235

    S3C9228/P9228 DEVEL OPMENT TOOLS 19- 1 19 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating sy ...

  • Samsung S3C9228/P9228 - page 236

    DEVELOPMENT TOOLS S3C9228/P9228 19- 2 BUS SMDS2+ RS-232C POD Probe Adapter PROM/OTP Writer Unit RAM Break/Display Unit Trace/Timer Unit SAM8 Base Unit Power Supply Unit IBM-PC AT or Compatible TB9228 Target Board EVA Chip Target Application System Figure 19-1. SMDS Product Configuration (SMDS2+) ...

  • Samsung S3C9228/P9228 - page 237

    S3C9228/P9228 DEVEL OPMENT TOOLS 19- 3 TB9228 TARGET BOARD The TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ development system. TB9228 SM1347A GND V CC To User_V CC OFF ON SMDS2 SMDS2+ J101 42SDIP J102 44QFP 1 5 15 21 10 42 40 25 22 30 35 1 5 15 22 10 44 40 30 23 35 25 20 P2 25 160 30 20 10 1 150 140 13 ...

  • Samsung S3C9228/P9228 - page 238

    DEVELOPMENT TOOLS S3C9228/P9228 19- 4 Table 19-1. Power Selection Settings for TB9228 "To User_V CC " Settings Operating Mode Comments To User_V CC Off On Target System SMDS2/SMDS2+ TB9228 V CC V SS V CC The SMDS2/SMDS2+ supplies V CC to the target board (evaluation chip) and the target system. To User_V CC Off On Target System SMDS2/SMDS ...

  • Samsung S3C9228/P9228 - page 239

    S3C9228/P9228 DEVEL OPMENT TOOLS 19- 5 SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 19-2. The SMDS2+ Tool Selection Setting "SW1" Settin ...

  • Samsung S3C9228/P9228 - page 240

    DEVELOPMENT TOOLS S3C9228/P9228 19- 6 J101 42-SDIP J102 44-QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47 P6.2 P6.3 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.1 NC NC NC NC P6.1 P6.0 P5.7 P5.6 P5.5 P5.4 ...

  • Samsung S3C9228/P9228 - page 241

    S3C9228/P9228 DEVEL OPMENT TOOLS 19- 7 Target Board Target System Target Cable for Connector Part Name: AP42SD Order Code: SM6538 J101 1 42 21 22 J101 1 42 21 22 50-Pin DIP Connector Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package Target Board Target System 50-Pin Connector Target Cable for 50-pin Connector Part Name: AP50D-A Order Code: SM6 ...

  • Samsung S3C9228/P9228 - page 242

    DEVELOPMENT TOOLS S3C9228/P9228 19- 8 NOTES ...

  • Samsung S3C9228/P9228 - page 243

    S3C9228/P9228 PRODUCT OVERVIEW 1- 1 1 PRODUCT OVERVIEW SAM8 8RC RI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chi p CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device . A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexibl ...

  • Samsung S3C9228/P9228 - page 244

    PRODUCT OVERVIEW S3C9228/P9228 1- 2 FEATURES CPU • SAM88RCRI CPU core Memory • 8192 × 8 bits program memory (ROM) • 264 × 8 bits data memory (RAM) (Including LCD data memory) Instruction Set • 41 instructions • Idle and Stop instructions added for power-down modes 36 I/O Pins • I/O: 34 pins (44-pin QFP, 42-pin SDIP) • Output only: 2 ...

  • Samsung S3C9228/P9228 - page 245

    S3C9228/P9228 PRODUCT OVERVIEW 1- 3 BLOCK DIAGRAM 8-Bit Timer/ CounterA Port I/O and Interrupt Control SAM88RCRI CPU RESET X IN XT IN I/O Port 0 8-Kbyte ROM 264-Byte Register File X OUT XT OUT 16-Bit Timer/ Counter1 8-Bit Timer/ CounterB TAOUT/ P0.0 T1CLK/ P0.1 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P0.4 P0.5 I/O Port 1 P1.0/AD0/INT P1 ...

  • Samsung S3C9228/P9228 - page 246

    PRODUCT OVERVIEW S3C9228/P9228 1- 4 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S3C9228 (44-QFP) P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT V DD V SS X OUT X IN TEST XT IN XT OUT RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.0/SCK SEG2/P3.1/INTP SEG3/P3.0/INTP SEG4/P4.0 SEG5/P4.1 SEG6/P4.2 SEG7/P4.3 33 32 31 30 29 28 ...

  • Samsung S3C9228/P9228 - page 247

    S3C9228/P9228 PRODUCT OVERVIEW 1- 5 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT V DD V SS X OUT X IN TEST XT IN XT OUT RESET P2.3 P2.2/SI SEG0/P2.1/SO S3C9228 (42-SDIP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/ ...

  • Samsung S3C9228/P9228 - page 248

    PRODUCT OVERVIEW S3C9228/P9228 1- 6 PIN DESCRIPTIONS Table 1- 1 . Pin Descriptions Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins P0.0 P0.1 P0.2 P0.3 I/O 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. E-4 39(3) 40(4) 41(5) 42(6) TAOUT/INT T1CLK/INT INT B ...

  • Samsung S3C9228/P9228 - page 249

    S3C9228/P9228 PRODUCT OVERVIEW 1- 7 Table 1- 1 . Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins V DD , V SS – Power input pins for internal power block – 5,6(11,12) – X OUT , X IN – Main oscillator pins for main clock – 7,8(13,14) XT OUT , XT IN – Sub oscillator pins for sub clock ? ...

  • Samsung S3C9228/P9228 - page 250

    PRODUCT OVERVIEW S3C9228/P9228 1- 8 PIN CIRCUIT DIAGRAMS RESET V DD Pull-Up Resistor Noise Filter Figure 1-4. Pin Circuit Type B V DD Output Output Disable Data V SS Figure 1-5. Pin Circuit Type C ...

  • Samsung S3C9228/P9228 - page 251

    S3C9228/P9228 PRODUCT OVERVIEW 1- 9 V DD Pull-up Enable V DD I/O Pull-up Resistor Output Disable Data External Interrupt Input Open-Drain Figure 1-7. Pin Circuit Type E-4 V DD I/O Pull-up Resistor Circuit Type E To ADC Data ADEN ADSELECT Open-Drain EN Data Output Disable Pull-up Enable Figure 1-8. Pin Circuit Type F-16A ...

  • Samsung S3C9228/P9228 - page 252

    PRODUCT OVERVIEW S3C9228/P9228 1- 10 Out SEG/COM V LC3 Output Disable V LC2 V LC1 V SS V LC4 V LC5 Figure 1-9. Pin Circuit Type H-23 ...

  • Samsung S3C9228/P9228 - page 253

    S3C9228/P9228 PRODUCT OVERVIEW 1- 11 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Figure 1-10. Pin Circuit Type H-32 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Figure 1-11. Pin Circuit Type H-32A ...

  • Samsung S3C9228/P9228 - page 254

    PRODUCT OVERVIEW S3C9228/P9228 1- 12 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Port Enable (LMOD.5) Figure 1-12. Pin Circuit Type H-32B ...

  • Samsung S3C9228/P9228 - page 255

    S3C9228/P9228 ADDRESS SPACES 2- 1 2 ADDRESS SPACES OVERVIEW The S3C9228/P9228 microcontroller has three kinds of address space: — Program memory (ROM) — Internal register file — LCD display register file A 16 -bit address bus supports program memory operations. Special instructions and related internal logic determine when the 1 6 -bit bus ca ...

  • Samsung S3C9228/P9228 - page 256

    ADDRESS SPACES S3C9228/P9228 2- 2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask- programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H– 0001H) are an interrupt vector address. The program reset address in the ROM is 01 ...

  • Samsung S3C9228/P9228 - page 257

    S3C9228/P9228 ADDRESS SPACES 2- 3 REGISTER ARCHITECTURE The upper 72 bytes of the S3C9228/P9228 's internal register file are addressed as working registers, system cont r ol registe r s and periphe r al control registers. The lower 184 bytes of internal register file (00H– B7 H) is called the general purpose register space . For many SAM88R ...

  • Samsung S3C9228/P9228 - page 258

    ADDRESS SPACES S3C9228/P9228 2- 4 COMMON WORKING REGISTER AREA (C0H–CFH) The SAM88RCR I register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as ...

  • Samsung S3C9228/P9228 - page 259

    S3C9228/P9228 ADDRESS SPACES 2- 5 SYSTEM STACK S 3C9 -series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file. STACK OPERATIONS Return addresses fo ...

  • Samsung S3C9228/P9228 - page 260

    ADDRESS SPACES S3C9228/P9228 2- 6 + + PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SP,#0 B8 H ; SP ← B8 H (Normally, the SP is set to 0 B8 H by the ; initialization routine) • • • PUSH SYM ; S ...

  • Samsung S3C9228/P9228 - page 261

    S3C9228/P9228 ADDRESSING MODES 3- 1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specifi ...

  • Samsung S3C9228/P9228 - page 262

    ADDRESSING MODES S3C9228/P9228 3- 2 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3- 1). Working register addressing differs from Register a ddressing because it uses a 16- byte working register s pace in the register file and a 4-bit register within that space (see Figure 3 ...

  • Samsung S3C9228/P9228 - page 263

    S3C9228/P9228 ADDRESSING MODES 3- 3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external mem ...

  • Samsung S3C9228/P9228 - page 264

    ADDRESSING MODES S3C9228/P9228 3- 4 INDIRECT REGISTER ADDRESSING MODE ( C ontinued ) dst OPCODE PAIR Points to Rigister Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16-Bit Address Points to Program Memory Figure 3- 4 . ...

  • Samsung S3C9228/P9228 - page 265

    S3C9228/P9228 ADDRESSING MODES 3- 5 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE OPERAND 4-Bit Working Register Address Point to the Woking Register (1 of 16) Sample Instruction: OR R6, @R2 Program Memory Register File src 4 LSBs Value used in Instruction OPERAND CFH C0H . . . . Figure 3- 5 . Indirect Working Register Addressing to Re ...

  • Samsung S3C9228/P9228 - page 266

    ADDRESSING MODES S3C9228/P9228 3- 6 INDIRECT REGISTER ADDRESSING MODE (C oncluded ) dst OPCODE 4-Bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program memory access LDE R3,@RR14 ; External data memory access LDE @RR4, R8 ; External data memory access Program Memory Register File src Value used in Instruction OPERAND Example Instru ...

  • Samsung S3C9228/P9228 - page 267

    S3C9228/P9228 ADDRESSING MODES 3- 7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3- 7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short o ...

  • Samsung S3C9228/P9228 - page 268

    ADDRESSING MODES S3C9228/P9228 3- 8 INDEXED ADDRESSING MODE (C ontinued ) Point to Working Register Pair (1 of 8) LSB Selects 16-Bit address added to offset dst OPCODE Program Memory XS (OFFSET) 4-Bit Working Register Address Sample Instructions: LDC R4, #04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4. LDE R4, ...

  • Samsung S3C9228/P9228 - page 269

    S3C9228/P9228 ADDRESSING MODES 3- 9 INDEXED ADDRESSING MODE (C oncluded ) Point to Working Register Pair (1 of 8) LSB Selects 16-Bit address added to offset Program Memory 4-Bit Working Register Address Sample Instructions: LDC R4, #1000H[RR2] ; The values in the program address (RR2 + #1000H) are loaded into register R4. LDE R4, #1000H[RR2] ; Iden ...

  • Samsung S3C9228/P9228 - page 270

    ADDRESSING MODES S3C9228/P9228 3- 10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and ...

  • Samsung S3C9228/P9228 - page 271

    S3C9228/P9228 ADDRESSING MODES 3- 11 DIRECT ADDRESS MODE (C ontinued ) OPCODE Program Memory Upper Address Byte Program Memory Address Used Lower Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3- 11 . Direct Addressing for Call and ...

  • Samsung S3C9228/P9228 - page 272

    ADDRESSING MODES S3C9228/P9228 3- 12 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occ ...

  • Samsung S3C9228/P9228 - page 273

    S3C9228/P9228 CONTROL REGISTERS 4- 1 4 CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing applicati ...

  • Samsung S3C9228/P9228 - page 274

    CONTROL REGISTERS S3C9228/P9228 4- 2 Table 4-1. Sys tem and Peripheral C ontrol Registers (Page 0) Register Name Mnemonic Address (Page 0) R/W Decimal Hex Port 0 Control Register P0CON 235 EBH R/W Port 0 Pull-up Resistor Enable Register P0PUR 236 ECH R/W Port 0 Interrupt Control Register P0INT 237 EDH R/W Port 0 Interrupt Edge Selection Register P0 ...

  • Samsung S3C9228/P9228 - page 275

    S3C9228/P9228 CONTROL REGISTERS 4- 3 Table 4- 1. Sys tem and Peripheral C ontrol Registers (Page 0) Register Name Mnemonic Address (Page 0) R/W Decimal Hex Locations D8H-B9H are not mapped. Timer B Control Register TBCON 202 BAH R/W Timer 1/A Control Register TACON 203 BBH R/W Timer B Data Register TBDATA 204 BCH R/W Timer A Data Register TADATA 20 ...

  • Samsung S3C9228/P9228 - page 276

    CONTROL REGISTERS S3C9228/P9228 4- 4 FLAGS - System Flags Register .7 .6 .5 Bit Identifier RESET RESET Value Read/Write R = Read-only W = Write-only R/W = Read/write ' - ' = Not used Bit number: MSB = Bit 7 LSB = Bit 0 Addressing mode or modes you can use to modify register values Description of the effect of specific bit settings RESET v ...

  • Samsung S3C9228/P9228 - page 277

    S3C9228/P9228 CONTROL REGISTERS 4- 5 AD C ON — A/D Converter Co ntrol Register D 0 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––000000 Read/Write – – R/W R/W R R/W R/W R/W .7-.6 Not used for the S3C9228/P9228 .5- . 4 A/D Input Pin Selection Bits 0 0 AD0 (P1.0) 0 1 AD1 (P1.1) 1 0 AD2 (P1.2) 1 1 AD3 (P1.3) .3 End of Conversi ...

  • Samsung S3C9228/P9228 - page 278

    CONTROL REGISTERS S3C9228/P9228 4- 6 BTC ON — Basic Timer Co ntrol Register DCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7- .4 Watchdog Timer En able Bits 1010 Disable watchdog function Any other value Enable watchdog function .3- .2 Basic Timer Input Clock Selection Bits 0 0 f ...

  • Samsung S3C9228/P9228 - page 279

    S3C9228/P9228 CONTROL REGISTERS 4- 7 CLKCON — System Clock Control Register D4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 Oscillator IRQ Wake-up Function Bit 0 Enable IRQ for main or sub oscillator wake-up in power down mode 1 Disable IRQ for main or sub oscillator wake-up in p ...

  • Samsung S3C9228/P9228 - page 280

    CONTROL REGISTERS S3C9228/P9228 4- 8 FLAGS — System Flags Register D5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value xxxx –––– Read/Write R/W R/W R/W R/W –––– .7 Carry Flag (C) 0 Operation does not generate a carry or borrow condition .6 Zero Flag (Z) 0 Operation result is a non-zero value 1 Operation result is zero .5 ...

  • Samsung S3C9228/P9228 - page 281

    S3C9228/P9228 CONTROL REGISTERS 4- 9 INTPND1 — Interrupt Pending Register 1 D6 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 P1.3's Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) .6 P1.2's Inte ...

  • Samsung S3C9228/P9228 - page 282

    CONTROL REGISTERS S3C9228/P9228 4- 10 INTPND2 — Interrupt Pending Register 2 D7 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––000000 Read/Write – – R/W R/W R/W R/W R/W R/W .7 -.6 Not used for S3C9228/P9228 . 5 P3.1 (INTP) Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is ...

  • Samsung S3C9228/P9228 - page 283

    S3C9228/P9228 CONTROL REGISTERS 4- 11 LMOD — LCD Mode Control Register FE H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –0000000 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6 COM Pins High Impedance Control Bit 0 Normal COMs signal output 1 COM pins are at high impedance .5 Port3 High Impedance Control ...

  • Samsung S3C9228/P9228 - page 284

    CONTROL REGISTERS S3C9228/P9228 4- 12 LPOT — LCD Port Control Register D8 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –0000000 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6-.4 SEG4-SEG19 and COM0-COM3 Selection Bit SEG4-7 SEG8-11 SEG12-15 SEG16-19/ COM7-COM4 COM0-3 P4.0-P4.3 P4.4-P4.7 P5.0-P5.3 P5.4- ...

  • Samsung S3C9228/P9228 - page 285

    S3C9228/P9228 CONTROL REGISTERS 4- 13 OSCCON — Oscillator Control Register D3 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––00–0 Read/Write –––– R/W R/W – R/W .7 -.4 Not used for S3C9228/P9228 .3 Main Oscillator Control Bit 0 Main oscillator RUN 1 Main oscillator STOP .2 Sub Oscillator Control Bit 0 Sub oscill ...

  • Samsung S3C9228/P9228 - page 286

    CONTROL REGISTERS S3C9228/P9228 4- 14 P0CON – Port 0 Control Register EBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P0.3/BUZ/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (BUZ output) .5-.4 P0.2 ...

  • Samsung S3C9228/P9228 - page 287

    S3C9228/P9228 CONTROL REGISTERS 4- 15 P0INT –Port 0 Interrupt Enable Register EDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .2 P0.2's Interrupt Enable Bit 0 Disabl ...

  • Samsung S3C9228/P9228 - page 288

    CONTROL REGISTERS S3C9228/P9228 4- 16 P0PUR –Port 0 Pull-up Resistors Enable Register ECH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .2 P0.2's ...

  • Samsung S3C9228/P9228 - page 289

    S3C9228/P9228 CONTROL REGISTERS 4- 17 P0EDGE –Port 0 Interrupt Edge Selection Register EEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Edge Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .2 P0.2's Inte ...

  • Samsung S3C9228/P9228 - page 290

    CONTROL REGISTERS S3C9228/P9228 4- 18 P1CON – Port 1 Control Register EFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P1.3/AD3/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (ADC mode) .5-.4 P1.2/A ...

  • Samsung S3C9228/P9228 - page 291

    S3C9228/P9228 CONTROL REGISTERS 4- 19 P1INT –Port 1 Interrupt Enable Register F1H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .2 P1.2's Interrupt Enable Bit 0 Disabl ...

  • Samsung S3C9228/P9228 - page 292

    CONTROL REGISTERS S3C9228/P9228 4- 20 P1PUR –Port 1 Pull-up Resistors Enable Register F0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .2 P1.2's ...

  • Samsung S3C9228/P9228 - page 293

    S3C9228/P9228 CONTROL REGISTERS 4- 21 P1EDGE –Port 1 Interrupt Edge Selection Register F2H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Edge Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .2 P1.2's Inte ...

  • Samsung S3C9228/P9228 - page 294

    CONTROL REGISTERS S3C9228/P9228 4- 22 P2CON – Port 2 Control Register F3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P2.3 Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not available .5-.4 P2.2/SI Configuration Bits 0 0 S ...

  • Samsung S3C9228/P9228 - page 295

    S3C9228/P9228 CONTROL REGISTERS 4- 23 P2PUR –Port 2 Pull-up Resistors Enable Register F4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P2.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .2 P2.2's ...

  • Samsung S3C9228/P9228 - page 296

    CONTROL REGISTERS S3C9228/P9228 4- 24 P3CON – Port 3 Control Register F5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3-.2 P3.1/SEG2/INTP Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not ...

  • Samsung S3C9228/P9228 - page 297

    S3C9228/P9228 CONTROL REGISTERS 4- 25 P3INT –Port 3 Interrupt Enable Register F7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .0 P3.0's Interrupt Enable Bit 0 Disa ...

  • Samsung S3C9228/P9228 - page 298

    CONTROL REGISTERS S3C9228/P9228 4- 26 P3PUR –Port 3 Pull-up Resistors Enable Register F6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .0 P3.0' ...

  • Samsung S3C9228/P9228 - page 299

    S3C9228/P9228 CONTROL REGISTERS 4- 27 P3EDGE –Port 3 Interrupt Edge Selection Register F8H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.4 Not used for S3C9228/P9228 .1 P3.1's Interrupt State Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .0 P3.0's I ...

  • Samsung S3C9228/P9228 - page 300

    CONTROL REGISTERS S3C9228/P9228 4- 28 P4CONH – Port 4 Control Register High Byte F9H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P4.7/SEG11 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P4.6/SEG10 Configura ...

  • Samsung S3C9228/P9228 - page 301

    S3C9228/P9228 CONTROL REGISTERS 4- 29 P4CONL –Port 4 Control Register Low Byte FAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P4.3/SEG7 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P4.2/SEG6 Configuration ...

  • Samsung S3C9228/P9228 - page 302

    CONTROL REGISTERS S3C9228/P9228 4- 30 P5CONH – Port 5 Control Register High Byte FBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P5.7/SEG19/COM4 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P5.6/SEG18/COM ...

  • Samsung S3C9228/P9228 - page 303

    S3C9228/P9228 CONTROL REGISTERS 4- 31 P5CONL – Port 5 Control Register Low Byte FCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P5.3/SEG15 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P5.2/SEG14 Configura ...

  • Samsung S3C9228/P9228 - page 304

    CONTROL REGISTERS S3C9228/P9228 4- 32 P6CON – Port 6 Control Register High Byte FDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P6.3/COM0 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .5-.4 P6.2/COM1 Configurati ...

  • Samsung S3C9228/P9228 - page 305

    S3C9228/P9228 CONTROL REGISTERS 4- 33 SIOCON — SIO Control Register E1 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 SIO Shift Clock Selection Bit 0 Internal clock ( P.S clock) 1 External clock (SCK) .6 Data Direction Control Bit 0 MSB-first mode 1 LSB-first mode . 5 SIO Mode S ...

  • Samsung S3C9228/P9228 - page 306

    CONTROL REGISTERS S3C9228/P9228 4- 34 STPCON – Stop Control Register E0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 Stop Control Bits 1 0100101 Enable Stop instruction Other values Disable Stop instruction NOTE: Before executing the STOP instruction, the STPCON register must be ...

  • Samsung S3C9228/P9228 - page 307

    S3C9228/P9228 CONTROL REGISTERS 4- 35 SYM — System Mode Register DFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 Global Interrupt Enable Bit 0 G lobal interrupt processing disable (DI instruction) 1 G lobal interrupt processing enable (EI ins ...

  • Samsung S3C9228/P9228 - page 308

    CONTROL REGISTERS S3C9228/P9228 4- 36 T A CON — Timer 1/A Control Register BBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0 000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 Timer 1 Mode Selection Bit 0 Two 8-bit timers mode (Timer A/B) 1 One 16-bit timer mode (Timer 1) .6-.4 Timer 1/A Clock Selection Bits 000 fxx/512 001 fxx/ ...

  • Samsung S3C9228/P9228 - page 309

    S3C9228/P9228 CONTROL REGISTERS 4- 37 T B CON — Timer B Control Register BA H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –000000– Read/Write – R/W R/W R/W R/W R/W R/W – .7 Not used for S3C9228/P9228 .6-.4 Timer B Clock Selection Bits 000 fxx/512 001 fxx/256 010 fxx/64 011 fxx/8 100 fxx (system clock) 101 fxt (sub clock) .3 T ...

  • Samsung S3C9228/P9228 - page 310

    CONTROL REGISTERS S3C9228/P9228 4- 38 WTCON — Watch Timer Control Register DA H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 Watch Timer Clock Selection Bit 0 Select main clock divided by 2 7 (fx/128) 1 Select sub clock ( fxt) .6 Watch Timer Interrupt Enable Bit 0 Disable watch ...

  • Samsung S3C9228/P9228 - page 311

    S3C9228/P9228 INTERRUPT STRUCTURE 5- 1 5 INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H. SOURCES VECTOR S1 S2 S3 Sn 0000H 0001H NOTES: 1. The SAM88RCRI interrupt h ...

  • Samsung S3C9228/P9228 - page 312

    INTERRUPT STRUCTURE S3C9228/P9228 5- 2 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87 RCR I ...

  • Samsung S3C9228/P9228 - page 313

    S3C9228/P9228 INTERRUPT STRUCTURE 5- 3 INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source&apos ...

  • Samsung S3C9228/P9228 - page 314

    INTERRUPT STRUCTURE S3C9228/P9228 5- 4 S3C9228/P9228 INTERRUPT STRUCTURE The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources: — Timer 1/A interr upt — Timer B interrupt — SIO interrupt — Watch Timer interrupt — Four external interrupts for port 0 — Four external interrupts for port 1 — Two external interrupts f ...

  • Samsung S3C9228/P9228 - page 315

    S3C9228/P9228 INTERRUPT STRUCTURE 5- 5 SYM.3 (EI, DI) P0INT.0 P0.0 External Interript P0INT.1 P0.1 External Interript P0.3 External Interript P0.2 External Interript P0INT.2 P0INT.3 INTPND1.0 INTPND1.1 INTPND1.2 INTPND1.3 P1.0 External Interript P1INT.0 P1.2 External Interript P1.3 External Interrupt P1.1 External Interript P1INT.1 P1INT.2 P1INT.3 ...

  • Samsung S3C9228/P9228 - page 316

    INTERRUPT STRUCTURE S3C9228/P9228 5- 6 Programming Tip — How to clear an interrupt pending bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD INTPND1, #11111011B ; Clear P0.2's interrupt pending bit • • • IRET 2. L D INTPND2, #11110111B ; Clear watch timer inter ...

  • Samsung S3C9228/P9228 - page 317

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 1 6 SAM8 8RC R I INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8- bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers ar ...

  • Samsung S3C9228/P9228 - page 318

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 2 Table 6- 1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDC dst,src Load program memory LDE dst,src Load external data memory LDCD dst,src Load program memory and decrement LDED dst,src Load external data memory and decrement LDCI dst,src Load ...

  • Samsung S3C9228/P9228 - page 319

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 3 Table 6- 1 . Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL dst Call procedure IRET Interrupt return JP cc,dst Jump on condition code JP dst Jump unconditional JR cc,dst Jump relative on condition code RET Return Bit Manipulation Instructions TCM ...

  • Samsung S3C9228/P9228 - page 320

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 4 FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 – FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect ...

  • Samsung S3C9228/P9228 - page 321

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 5 INSTRUCTION SET NOTATION Table 6- 2 . Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined Table 6- 3 . Instruction Set Symbols Sy ...

  • Samsung S3C9228/P9228 - page 322

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 6 Table 6- 4 . Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6- 6. r Working register only Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, ..., 14) R Register or working register reg or Rn ( reg = 0–255, n = 0 ...

  • Samsung S3C9228/P9228 - page 323

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 7 Table 6- 5 . Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0123456 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM P 2 INC R1 INC IR1 SUB r1,r2 SUB r1,Ir2 SUB R2,R1 SUB IR2,R1 SUB R1,IM E 3 JP I ...

  • Samsung S3C9228/P9228 - page 324

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 8 Table 6- 5 . Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 JR cc,RA LD r1,IM JP cc,DA INC r1 P 1 ↓↓ ↓↓↓↓ P 2 E 3 R 4 5 N 6 IDLE I 7 ↓↓ ↓↓↓↓ STOP B 8 DI B 9 EI L A RE T E B IRET C RCF H D ↓↓ ↓↓↓↓ SCF E E CCF ...

  • Samsung S3C9228/P9228 - page 325

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 9 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two ...

  • Samsung S3C9228/P9228 - page 326

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 10 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction ...

  • Samsung S3C9228/P9228 - page 327

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 11 ADC — Add With Carry ADC dst,src Operation: dst ¨ dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed. In m ...

  • Samsung S3C9228/P9228 - page 328

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 12 ADD — Add ADD dst,src Operation: dst ¨ dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of ...

  • Samsung S3C9228/P9228 - page 329

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 13 AND — Logical AND AND dst,src Operation: dst ¨ dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ...

  • Samsung S3C9228/P9228 - page 330

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 14 CALL — Call Procedure CALL dst Operation: SP ¨ SP – 1 @SP ¨ PCL SP ¨ SP –1 @SP ¨ PCH PC ¨ dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified ...

  • Samsung S3C9228/P9228 - page 331

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 15 CCF — Complement Carry Flag CCF Operation: C ¨ NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Form ...

  • Samsung S3C9228/P9228 - page 332

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 16 CLR — Clear CLR dst Operation: dst ¨ "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 B0 R 4 B1 IR Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR 00H → ...

  • Samsung S3C9228/P9228 - page 333

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 17 COM — Complement COM dst Operation: dst ¨ NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the resu ...

  • Samsung S3C9228/P9228 - page 334

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 18 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred ( src > dst); cl ...

  • Samsung S3C9228/P9228 - page 335

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 19 DEC — Decrement DEC dst Operation: dst ¨ dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, dst ...

  • Samsung S3C9228/P9228 - page 336

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 20 DI — Disable Interrupts DI Operation: SYM (2) ¨ 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt ...

  • Samsung S3C9228/P9228 - page 337

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 21 EI — Enable Interrupts EI Operation: SYM (2) ¨ 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction ...

  • Samsung S3C9228/P9228 - page 338

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 22 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src ...

  • Samsung S3C9228/P9228 - page 339

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 23 INC — Increment INC dst Operation: dst ¨ dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is dst ...

  • Samsung S3C9228/P9228 - page 340

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 24 IRET — Interrupt Return IRET IRET Operation: FLAGS ¨ @SP SP ¨ SP + 1 PC ¨ @SP SP ¨ SP + 2 SYM(2) ¨ 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. Flags: All flags are restored to ...

  • Samsung S3C9228/P9228 - page 341

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 25 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ¨ dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction ...

  • Samsung S3C9228/P9228 - page 342

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 26 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ¨ PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction followi ...

  • Samsung S3C9228/P9228 - page 343

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 27 LD — Load LD dst,src Operation: dst ¨ src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src dst | opc src 2 4 rC r IM 4 r8 r R src | opc dst 2 4 r9 R r r = 0 to F ...

  • Samsung S3C9228/P9228 - page 344

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 28 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD R0,#10H → R0 = 10H LD R0,01H → R0 = 20H, register 01H = 20H LD 01H,R0 → Register 01H = 01H, R0 = 01H LD R1,@R0 → R1 = 20H, R0 = 01H ...

  • Samsung S3C9228/P9228 - page 345

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 29 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ¨ src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes ' Irr' or ' rr&apos ...

  • Samsung S3C9228/P9228 - page 346

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 30 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 110 ...

  • Samsung S3C9228/P9228 - page 347

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 31 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ¨ src rr ¨ rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The cont ...

  • Samsung S3C9228/P9228 - page 348

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 32 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ¨ src rr ¨ rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents ...

  • Samsung S3C9228/P9228 - page 349

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 33 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typic ally, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 FF Example: When th ...

  • Samsung S3C9228/P9228 - page 350

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 34 OR — Logical OR OR dst,src Operation: dst ¨ dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the correspondi ...

  • Samsung S3C9228/P9228 - page 351

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 35 POP — Pop From Stack POP dst Operation: dst ¨ @SP SP ¨ SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 8 50 R 8 51 ...

  • Samsung S3C9228/P9228 - page 352

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 36 PUSH — Push To Stack PUSH src Operation: SP ¨ SP – 1 @SP ¨ src A PUSH instruction decrements the stack pointer value and loads the contents of the source ( src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No f ...

  • Samsung S3C9228/P9228 - page 353

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 37 RCF — Reset Carry Flag RCF RCF Operation: C ¨ 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 CF Example: Given: C = "1" or "0": The instruct ...

  • Samsung S3C9228/P9228 - page 354

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 38 RET — Return RET Operation: PC ¨ @SP SP ¨ SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next st ...

  • Samsung S3C9228/P9228 - page 355

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 39 RL — Rotate Left RL dst Operation: C ¨ dst (7) dst (0) ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value o f bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. C 7 0 Flags: C: Set ...

  • Samsung S3C9228/P9228 - page 356

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 40 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ¨ C C ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag rep ...

  • Samsung S3C9228/P9228 - page 357

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 41 RR — Rotate Right RR dst Operation: C ¨ dst (0) dst (7) ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The content s of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). C 7 0 Flags: C: Set i ...

  • Samsung S3C9228/P9228 - page 358

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 42 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ¨ C C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry fl ...

  • Samsung S3C9228/P9228 - page 359

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 43 SBC — Subtract With Carry SBC dst,src Operation: dst ¨ dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed ...

  • Samsung S3C9228/P9228 - page 360

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 44 SCF — Set Carry Flag SCF Operation: C ¨ 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to logic one. ...

  • Samsung S3C9228/P9228 - page 361

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 45 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ¨ dst (7) C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is perform ed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and i ...

  • Samsung S3C9228/P9228 - page 362

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 46 STOP — Stop Operation STOP Operation: The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be ...

  • Samsung S3C9228/P9228 - page 363

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 47 SUB — Subtract SUB dst,src Operation: dst ¨ dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the d ...

  • Samsung S3C9228/P9228 - page 364

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 48 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src Thi s instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM stat ...

  • Samsung S3C9228/P9228 - page 365

    S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 49 TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the dest ...

  • Samsung S3C9228/P9228 - page 366

    SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 50 XOR — Logical Exclusive OR XOR dst,src Operation: dst ¨ dst XOR src The source operand is logically exclusive- ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the ...

  • Samsung S3C9228/P9228 - page 367

    S3C9228/P9228 CLOCK CIRCUITS 7- 1 7 CLOCK CIRCUITS OVERVIEW The S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency, is determined by CLKCON register settings . SYSTEM CLOCK C ...

  • Samsung S3C9228/P9228 - page 368

    CLOCK CIRCUITS S3C9 228/P9228 7- 2 MAIN OSCILLATOR CIRCUITS X IN X OUT Figure 7-1. Crystal/Ceramic Oscillator X IN X OUT Figure 7-2. External Oscillator X IN X OUT R Figure 7-3. RC Oscillator SUB OSCILLATOR CIRCUITS XT IN XT OUT 32.768 kHz Figure 7-4. Crystal/Ceramic Oscillator XT IN XT OUT Figure 7-5. External Oscillator ...

  • Samsung S3C9228/P9228 - page 369

    S3C9228/P9228 CLOCK CIRCUITS 7- 3 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is ...

  • Samsung S3C9228/P9228 - page 370

    CLOCK CIRCUITS S3C9 228/P9228 7- 4 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following functions: — Oscillator IRQ wake-up function enable/disable — Oscillator frequency divide-by value CLKCON register settings control whether or not an e ...

  • Samsung S3C9228/P9228 - page 371

    S3C9228/P9228 CLOCK CIRCUITS 7- 5 OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the following functions: — System clock selection — Main oscillator control — Sub oscillator control OSCCON.0 register settings select Main clock or Sub clock as system ...

  • Samsung S3C9228/P9228 - page 372

    CLOCK CIRCUITS S3C9 228/P9228 7- 6 SWITCHING THE CPU CLOCK Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating fr ...

  • Samsung S3C9228/P9228 - page 373

    S3C9228/P9228 CLOCK CIRCUITS 7- 7 STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: — Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values". If necessary, you c ...

  • Samsung S3C9228/P9228 - page 374

    CLOCK CIRCUITS S3C9 228/P9228 7- 8 NOTES ...

  • Samsung S3C9228/P9228 - page 375

    S3C9228/P9228 RESET RESET and POWER-DOWN 8- 1 8 RESET RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, the voltage at V DD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C9228/P9228 i ...

  • Samsung S3C9228/P9228 - page 376

    RESET RESET and POWER-DOWN S3C9228 /P9228 8- 2 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. But the watch timer and LCD controller will not ...

  • Samsung S3C9228/P9228 - page 377

    S3C9228/P9228 RESET RESET and POWER-DOWN 8- 3 Using an Internal Interrupt to Release Stop Mode An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release stop mode. That ...

  • Samsung S3C9228/P9228 - page 378

    RESET RESET and POWER-DOWN S3C9228 /P9228 8- 4 HARDWARE RESET RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these table to represent specific RESET values: — A "1" or ...

  • Samsung S3C9228/P9228 - page 379

    S3C9228/P9228 RESET RESET and POWER-DOWN 8- 5 Table 8-1. Register Values after RESET RESET (Continued) Register Name Mnemonic Address Bit Values after RESET RESET Dec Hex 76543210 System Mode Register SYM 223 DFH ––––0000 STOP Control Register STPCON 224 E0H 00000000 SIO Control Register SIOCON 225 E1H 0000000– SIO Data Register SIODATA 2 ...

  • Samsung S3C9228/P9228 - page 380

    RESET RESET and POWER-DOWN S3C9228 /P9228 8- 6 NOTES ...

  • Samsung S3C9228/P9228 - page 381

    S3C9228/P9228 I/O P ORTS 9- 1 9 I/O PORTS OVERVIEW The S3C9228/P9228 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports. This gives a total of 36 I/O pins. Each port can be flexibly configured to meet application d ...

  • Samsung S3C9228/P9228 - page 382

    I/O PORTS S3C9228/P 9228 9- 2 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Mnemonic Decimal Hex R/W Port 0 data register P0 228 ...

  • Samsung S3C9228/P9228 - page 383

    S3C9228/P9228 I/O P ORTS 9- 3 PORT 0 Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0. P0.0-P0.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following fu ...

  • Samsung S3C9228/P9228 - page 384

    I/O PORTS S3C9228/P 9228 9- 4 Port 0 Control Register (P0CON) EBH, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P0.3/BUZ (INT) P0CON bit-pair pin configuration settings: 00 01 10 11 N-channel open-drain output mode Alternative function (TAOUT, BUZ) P0.2 (INT) P0.1/T1CLK (INT) P0.0/TAOUT (INT) Push-pull output mode Schmitt trigger input mode (T1CLK) ...

  • Samsung S3C9228/P9228 - page 385

    S3C9228/P9228 I/O P ORTS 9- 5 Port 0 Interrupt Pending Bits (INTPND1.3-.0) D6H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB INTPND1 bit configuration settings: 0 1 P0.3 (INT) Interrupt is pending (when read) No interrupt pending (when read), clear pending bit (when write) P0.2 (INT) P0.1 (INT) P0.0 (INT) P1.3 (INT) P1.2 (INT) P1.1 (INT) P1.0 (INT) ...

  • Samsung S3C9228/P9228 - page 386

    I/O PORTS S3C9228/P 9228 9- 6 PORT 1 Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0. P1.0-P1.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following fu ...

  • Samsung S3C9228/P9228 - page 387

    S3C9228/P9228 I/O P ORTS 9- 7 Port 1 Interrupt Control Register (P1INT) F1H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used P1INT bit configuration settings: 0 1 P1.3 (INT) Enable interrupt Disable interrupt P1.2 (INT) P1.1 (INT) P1.0 (INT) Figure 9-8. Port 1 Interrupt Control Register (P1INT) Port 1 Interrupt Pending Bits (INTPND1.7-.4) D6H, ...

  • Samsung S3C9228/P9228 - page 388

    I/O PORTS S3C9228/P 9228 9- 8 Port 1 Interrupt Edge Selection Register (P1EDGE) F2H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P1EDGE bit configuration settings: 0 1 P1.3 (INT) Rising edge detection Falling edge detection P1.2 (INT) P1.1 (INT) P1.0 (INT) Not used Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE) Port 1 Pull-up Contro ...

  • Samsung S3C9228/P9228 - page 389

    S3C9228/P9228 I/O P ORTS 9- 9 PORT 2 Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0. P2.0-P2.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following fu ...

  • Samsung S3C9228/P9228 - page 390

    I/O PORTS S3C9228/P 9228 9- 10 Port 2 Pull-up Control Register (P2PUR) F4H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P2PUR bit configuration settings: 0 1 Enable pull-up resistor Disable pull-up resistor Not used P2.3 P2.2 P2.1 P2.0 Figure 9-13. Port 2 Pull-up Control Register (P2PUR) ...

  • Samsung S3C9228/P9228 - page 391

    S3C9228/P9228 I/O P ORTS 9- 11 PORT 3 Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0. P3.0-P3.1 can serve as inputs (with or without pull- up, and high impedance input), as outputs (push-pull or open-drain) or you can be ...

  • Samsung S3C9228/P9228 - page 392

    I/O PORTS S3C9228/P 9228 9- 12 Port 3 Interrupt Control Register (P3INT) F7H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used P3INT bit configuration settings: 0 1 Enable interrupt Disable interrupt P3.1 (INTP) P3.0 (INTP) Figure 9-15. Port 3 Interrupt Control Register (P3INT) Port 3 Interrupt Pending Bits (INTPND2.5-.4) D7H, Page 0, R/W .7 .6 ...

  • Samsung S3C9228/P9228 - page 393

    S3C9228/P9228 I/O P ORTS 9- 13 Port 3 Interrupt Edge Selection Register (P3EDGE) F8H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P3EDGE bit configuration settings: 0 1 Rising edge detection Falling edge detection P3.1 (INTP) P3.0 (INTP) Not used Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE) Port 3 Pull-up Control Register (P3PUR) ...

  • Samsung S3C9228/P9228 - page 394

    I/O PORTS S3C9228/P 9228 9- 14 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port ...

  • Samsung S3C9228/P9228 - page 395

    S3C9228/P9228 I/O P ORTS 9- 15 PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port ...

  • Samsung S3C9228/P9228 - page 396

    I/O PORTS S3C9228/P 9228 9- 16 PORT 6 Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port ...

  • Samsung S3C9228/P9228 - page 397

    S3C9228/P9228 ( Preliminary Spec ) BASIC TIMER 10- 1 10 BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a stop mode release. The func ...

  • Samsung S3C9228/P9228 - page 398

    BASIC TIMER S3C9228 /P9228 ( Preliminary Spec ) 10- 2 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH, and is read/write addres ...

  • Samsung S3C9228/P9228 - page 399

    S3C9228/P9228 ( Preliminary Spec ) BASIC TIMER 10- 3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to “00H”, automat ...

  • Samsung S3C9228/P9228 - page 400

    BASIC TIMER S3C9228 /P9228 ( Preliminary Spec ) 10- 4 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). MUX f XX /4096 DIV f XX /1024 f XX /128 f XX /16 f XX Bits 3, 2 Bit 0 Basic Timer Control Register (Write '1010xxxxB' to D ...

  • Samsung S3C9228/P9228 - page 401

    S3C9228/P9228 TIMER 1 11- 1 11 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers. — One 16-bit tim er mode (Timer 1) — Two 8-bit timers mode ...

  • Samsung S3C9228/P9228 - page 402

    TIMER 1 S3C9228/P922 8 11- 2 Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to — Enable the timer 1 operating (interval timer) — Select the timer 1 input clock frequency — Clear the timer 1 counter, TACNT and TBCNT — Enable the timer 1 interrupt TACON is located in page 0, at address BBH, and is read/write add ...

  • Samsung S3C9228/P9228 - page 403

    S3C9228/P9228 TIMER 1 11- 3 NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) TACON.6-.4 M U X 1/8 1 /64 1 /256 1 /512 INTPND2.0 TAOUT T1INT 1/1 DIV R fxt T1CLK (X IN or XT IN ) fxx BTCON.0 TACON.2 TBCNT TACNT 16-Bit Comparator TBDATA Buffer TADATA Buffer TBDATA TADATA LSB MSB LSB MSB Match Signal Counter clear signal TACON.1 ...

  • Samsung S3C9228/P9228 - page 404

    TIMER 1 S3C9228/P922 8 11- 4 TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively. Timer A and B have the following functional components: — Clock frequency divider with multiplexer – ...

  • Samsung S3C9228/P9228 - page 405

    S3C9228/P9228 TIMER 1 11- 5 TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer A cou ...

  • Samsung S3C9228/P9228 - page 406

    TIMER 1 S3C9228/P922 8 11- 6 Timer B Control Register (TBCON) BAH, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Timer B match interrupt enable bit: 0 = Disable match interrupt 1 = Enable match interrupt Not used Timer B count enable bit: 0 = Disable counting operating 1 = Enable counting operating Timer B counter clear bit: 0 = No effect 1 = Clear the timer ...

  • Samsung S3C9228/P9228 - page 407

    S3C9228/P9228 TIMER 1 11- 7 FUNCTION DESCRIPTION Interval Timer Function (Timer A and Timer B) The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). The timer A match interrupt pending condition (INTPND2.0) and the timer B match interrupt pending condition (INTPND2.1) must b ...

  • Samsung S3C9228/P9228 - page 408

    TIMER 1 S3C9228/P922 8 11- 8 NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) TACON.6-.4 M U X 1/8 1 /64 1 /256 1 /512 INTPND2.0 TAOUT TAINT DIV R fxt T1CLK/ P0.1 (X IN or XT IN ) fxx BTCON.0 TACON.2 8-Bit Comparator TADATA Buffer TADATA Register LSB MSB LSB MSB Match Signal Counter Clear Signal TACON.1 Match R TACON.3 Data B ...

  • Samsung S3C9228/P9228 - page 409

    S3C9228/P9228 TIMER 1 11- 9 1/1 1/8 1 /64 1 /256 1 /512 NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) TBCON.6-.4 M U X INTPND2.1 TBINT DIV R fxt (X IN or XT IN ) fxx BTCON.0 TBCON.2 8-Bit Comparator TBDATA Buffer TBDATA Register LSB MSB LSB MSB Match Signal Counter Clear Signal TBCON.1 Match R TBCON.3 Data Bus Data Bus TBC ...

  • Samsung S3C9228/P9228 - page 410

    TIMER 1 S3C9228/P922 8 11- 10 NOTES ...

  • Samsung S3C9228/P9228 - page 411

    S3C9228/P9228 WATCH TIMER 12- 1 12 WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt, then set the WTCON.6 ...

  • Samsung S3C9228/P9228 - page 412

    WATCH TIMER S3C922 8/P9228 12- 2 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode. ...

  • Samsung S3C9228/P9228 - page 413

    S3C9228/P9228 WATCH TIMER 12- 3 WATCH TIMER CIRCUIT DIAGRAM WT INT Enable WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 WTCON.6 Enable/Disable Selector Circuit MUX INTPND2.3 WTINT WTCON.6 f W /2 15 f W /2 14 f W /2 13 f W /2 7 f W /64 (0.5 kHz) f W /32 (1 kHz) f W /16 (2 kHz) f W /8 (4 kHz) (1 Hz) f X = Main clock (where fx = 4.19 MHz) fxt = Sub clock (3 ...

  • Samsung S3C9228/P9228 - page 414

    WATCH TIMER S3C922 8/P9228 12- 4 NOTES ...

  • Samsung S3C9228/P9228 - page 415

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 1 13 LCD CONTROLLER/DRIV ER OVERVIEW The S3C9228/P9228 microcontroller can directly drive an up-to- 128 -dot ( 16 segments x 8 commons) LCD panel. Its LCD block has the following components: — LCD control ler/driver — Display RAM for storing display data — 16 segment output pins (SEG0 – SEG 15 ) — ...

  • Samsung S3C9228/P9228 - page 416

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 2 LCD CIRCUIT DIAGRAM SEG15/P5.3 COM4/SEG19/P5.7 COM7/SEG16/P5.4 160 16 Data BUS Port Latch LPOT Display RAM (Page1) Port Latch Port Latch Timing Controller MUX SEG Control or Selector COM Control or selector f LCD SEG0/P2.1 COM3/P6.0 COM0/P6.3 COM Control LCD Voltage Control Port 3 Control P3.1/INTP/SEG2 P3. ...

  • Samsung S3C9228/P9228 - page 417

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 3 LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0–SEG 19 using a direct m ...

  • Samsung S3C9228/P9228 - page 418

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 4 LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode. It has the following control functions. — LCD duty and bias selection — LCD clock selection — LCD display control — COMs signal output control — P3 high imped ...

  • Samsung S3C9228/P9228 - page 419

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 5 LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET , a LPOT values are cleared to "0". LCD Port Control Register D8H, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used SEG0/P2.1 selection bit: 0 = SEG port 1 = Normal I/ ...

  • Samsung S3C9228/P9228 - page 420

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 6 LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS 1/4 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS 1/3 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS Figure 13-6. Internal Voltage Dividin ...

  • Samsung S3C9228/P9228 - page 421

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 7 1 Frame FR V DD V SS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM1 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 SEG0 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 COM2 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 COM0 V LC2 ( V LC3 ) V LC4 V SS V DD V LC1 SEG0-COM0 + V DD 0V + 1/4V LCD -V LCD - 1/4V LCD 0 1 2 3 7 4 6 5 0 1 2 3 7 4 ...

  • Samsung S3C9228/P9228 - page 422

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 8 1 Frame V DD V SS 0 1 2 3 0 1 2 3 COM1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM2 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM3 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG0 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM0-SEG0 + V LCD COM0 V SS V DD V LC1 ...

  • Samsung S3C9228/P9228 - page 423

    S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 9 1 Frame V DD V SS 0 1 2 COM1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM2 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG0 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM0-SEG0 + V LCD COM0 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) + 1/3 V LCD 0V - 1/3 V LCD - V ...

  • Samsung S3C9228/P9228 - page 424

    LCD CONTROLLER/DRIVER S3C9228/P9228 13- 10 NOTES ...

  • Samsung S3C9228/P9228 - page 425

    S3C9228/P9228 A/D C ONVERTER 14- 1 14 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10 -bit digital values. The an alog input level must lie between the AV REF and AV SS values. The A/D converter ...

  • Samsung S3C9228/P9228 - page 426

    A/D CONVERTER S3C9 228/P9228 14- 2 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is ...

  • Samsung S3C9228/P9228 - page 427

    S3C9228/P9228 A/D C ONVERTER 14- 3 Conversion Data Register ADDATAH/ADDATAL D1H/D2H, Page 0, Read Only .9 .8 .7 .6 .5 .4 .3 .2 MSB LSB (ADDATAH) ------ .1 .0 MSB LSB (ADDATAL) Figure 14-2. A/D Converter Data Register (ADDATAH/ADDATAL) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the refe ...

  • Samsung S3C9228/P9228 - page 428

    A/D CONVERTER S3C9 228/P9228 14- 4 S3C9228 AD0-AD3 Analog Input Pin V DD 101 C (V SS ≤ ADC input ≤ V DD ) Figure 14-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy ...

  • Samsung S3C9228/P9228 - page 429

    S3C9228/P9228 SERIAL I/O INTERFACE 1 5- 1 15 SERIAL I/O INTERFAC E OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: — 8-bit control register (S IOCON ) — Clock selector logic — 8-bit data buffer (SIODATA) — 8-bit prescaler (SIOPS ...

  • Samsung S3C9228/P9228 - page 430

    SERIAL I/O INTERFACE S3C9228/P9228 15- 2 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0. It has the control setting for SIO module. — Clock source selection (internal or external) for shift clock — Interrupt enable — Edge selection for shift operation — Clear 3-bit co ...

  • Samsung S3C9228/P9228 - page 431

    S3C9228/P9228 SERIAL I/O INTERFACE 1 5- 3 SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0. The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/( Prescaler value + 1), or SCK inp ...

  • Samsung S3C9228/P9228 - page 432

    SERIAL I/O INTERFACE S3C9228/P9228 15- 4 SERIAL I/O TIMING DIAGRAM (SIO) SO Transmit Complete SIO INT Set SIOCON.3 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI SCK Figure 15-4 . Serial I/O Timing in Transmit/Receive Mode ( Tx at falling, SIOCON.4 = 0) SIO INT DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK ...

  • Samsung S3C9228/P9228 - page 433

    S3C9228/P9228 ELECT RICAL DATA 16- 1 16 ELECTRICAL DATA OVERVIEW In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supp ly voltage in Stop mode — Stop mode release timi ...

  • Samsung S3C9228/P9228 - page 434

    ELECTRICAL DATA S3C 9228/P9228 16- 2 Table 16-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – – 0.3 to + 6.5 V Input voltage V IN Ports 0 –6 – 0.3 to V DD + 0.3 V Output voltage V O – – 0.3 to V DD + 0.3 V Output current High I OH One I/O pin active – 15 mA All I/O pins active ...

  • Samsung S3C9228/P9228 - page 435

    S3C9228/P9228 ELECT RICAL DATA 16- 3 Table 16-2. D.C. Electrical Characteristics (Continued) (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input Low leakage current I LIL1 V I = 0 V; All input pins except RESET , X OUT , XT IN , XT OUT – – –3 µ A I LIL2 V I = 0 V; X IN , X OUT , XT IN , ...

  • Samsung S3C9228/P9228 - page 436

    ELECTRICAL DATA S3C 9228/P9228 16- 4 Table 16-2. D.C. Electrical Characteristics (Concluded) (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 Run mode: V DD = 5 V ± 10% 8.0 MHz – 6.0 12.0 mA Crystal oscillator C1 = C2 = 22pF 4.19 MHz 3.0 6.0 V DD = 3 V ± 10% 8.0 MHz 2. ...

  • Samsung S3C9228/P9228 - page 437

    S3C9228/P9228 ELECT RICAL DATA 16- 5 Table 16-3. Data Retention Supply Voltage in Stop Mode (T A = – 25 ° C to + 85 ° C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR – 2.0 – 5.5 V Data retention supply current I DDDR Stop mode, T A = 25 ° C V DDDR = 2.0 V ––1 µA Execution of STOP Instruction Idle M ...

  • Samsung S3C9228/P9228 - page 438

    ELECTRICAL DATA S3C 9228/P9228 16- 6 Execution of STOP Instrction RESET Occurs ~ ~ V DDDR ~ ~ Stop Mode Oscillation Stabilization TIme Normal Operating Mode Data Retention Mode t WAIT RESET V DD 0.2 V DD 0.8 V DD NOTE: t WAIT is the same as 16 × 1/BT clock. Figure 16-2. Stop Mode Release Timing When Initiated by a RESET RESET Table 16-4. Input/Out ...

  • Samsung S3C9228/P9228 - page 439

    S3C9228/P9228 ELECT RICAL DATA 16- 7 Table 16-5. A.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit SCK cycle time t KCY External SCK source 1,000 – – ns Internal SCK source 1,000 SCK high, low width t KH , t KL External SCK source 500 Internal SCK source t KCY /2 ...

  • Samsung S3C9228/P9228 - page 440

    ELECTRICAL DATA S3C 9228/P9228 16- 8 Table 16-6. A/D Converter Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.7 V to 5.5 V, V SS = 0 V) Parameter Symbol Conditions Min Typ Max Unit Resolution – 10 – bit Total accuracy VDD = 5.12 V – – ± 3 LSB Integral linearity error ILE fxx = 8 MHz – – ± 2 Differential linearity ...

  • Samsung S3C9228/P9228 - page 441

    S3C9228/P9228 ELECT RICAL DATA 16- 9 RESET t RSL 0.2 V DD Figure 16-4. Input Timing for RESET RESET t KH t KL 0.2V DD SCK t KCY 0.8V DD 0.8V DD 0.2V DD t SIK t KSI SI SO t KSO Output Data Figure 16-5. Serial Data Transfer Timing ...

  • Samsung S3C9228/P9228 - page 442

    ELECTRICAL DATA S3C 9228/P9228 16- 10 Table 16-7. Main Oscillation Characteristics (T A = – 25 ° C to + 85 ° C) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal X IN C1 X OUT Main oscillation frequency 2.7 V – 5.5 V 0.4 – 8 MHz 2.0 V – 5.5 V 0.4 – 4 Ceramic Oscillator X IN C1 X OUT Main oscillation frequ ...

  • Samsung S3C9228/P9228 - page 443

    S3C9228/P9228 ELECT RICAL DATA 16- 11 Table 16-9. Main Oscillation Stabilization Time (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal fx > 1 MHz – – 30 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage ranage. – – 10 ms External clock ...

  • Samsung S3C9228/P9228 - page 444

    ELECTRICAL DATA S3C 9228/P9228 16- 12 Table 16-10. Sub Oscillation Stabilization Time (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal – – – 10 s External clock XT IN input high and low width (t XH , t XL ) 5 – 15 µ s t XTH t XTL V DD -0.1 V 0.1 V XT IN 1/fxt Figure 16-7. Clock Timi ...

  • Samsung S3C9228/P9228 - page 445

    S3C9228/P9228 ELECT RICAL DATA 16- 13 2 MHz 6.25 kHz (main)/8.2 kHz(sub) 1 2 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 MHz Instruction Clock 8 MHz 4 MHz fx (Main/Sub oscillation frequency) 400 kHz 2.7 5.5 400 kHz (main)/32.8 kHz(sub) Figure 16-8. Operating Voltage Range ...

  • Samsung S3C9228/P9228 - page 446

    ELECTRICAL DATA S3C 9228/P9228 16- 14 NOTES ...

  • Samsung S3C9228/P9228 - page 447

    S3C9228/P9228 MECHANICAL DATA 1 7- 1 17 MECHANICAL DATA OVERVIEW The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package. NOTE : Dimensions are in millimeters. 39.50 MAX 39.10 ± 0 .2 0.50 ± 0.1 1.78 (1.77) 0.51 MIN 3.30 ± 0.3 3.50 ± 0.2 5.08 MAX 42-SDIP-600 0-15 1.00 ± 0.1 0.25 + 0.1 - 0.05 15.24 14.00 ...

  • Samsung S3C9228/P9228 - page 448

    MECHANICAL DATA S3C9228/P9228 1 7- 2 44-QFP-1010B #44 NOTE : Dimensions are in millimeters. 10.00 ± 0.2 13.20 ± 0.3 10.00 ± 0.2 13.20 ± 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 MAX 0.80 ± 0.20 0.05 MIN 2.05 ± 0.10 2.30 MAX 0.15 + 0.10 - 0.05 0-8 Figure 17-2. 44-QFP-1010B Package Dimensions ...

  • Samsung S3C9228/P9228 - page 449

    S3C9228/P9228 S3P9228 OTP 18- 1 18 S3P9228 OTP OVERVIEW The S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9228 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9228 is fully compatible with the S3C9228, both in function and in pin co ...

  • Samsung S3C9228/P9228 - page 450

    S3P9228 OTP S3C9228/P9228 18- 2 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT SDAT /P1.2/AD2/INT SCLK /P1.3/AD3/INT V DD /V DD V SS /V SS X OUT X IN V PP /TEST XT IN XT OUT RESET RESET / RESET P2.3 P2.2/SI SEG0/P2.1/SO S3C9228 (42-SDIP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 COM2/P6 ...

  • Samsung S3C9228/P9228 - page 451

    S3C9228/P9228 S3P9228 OTP 18- 3 Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P1.2 SDAT 3 (9) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. P1.3 SCLK 4 (10) I/O Serial clock pin. Input on ...

  • Samsung S3C9228/P9228 - page 452

    S3P9228 OTP S3C9228/P9228 18- 4 Table 18-4. D.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 Run mode: V DD = 5 V ± 10% 8.0 MHz – 6.0 12.0 mA Crystal oscillator C1 = C2 = 22pF 4.19 MHz 3.0 6.0 V DD = 3 V ± 10% 8.0 MHz 2.5 5.0 4.19 MHz 1. ...

  • Samsung S3C9228/P9228 - page 453

    S3C9228/P9228 S3P9228 OTP 18- 5 2 MHz 6.25 kHz (main)/8.2 kHz(sub) 1 2 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 MHz Instruction Clock 8 MHz 4 MHz fx (Main/Sub oscillation frequency) 400 kHz 2.7 5.5 400 kHz (main)/32.8 kHz(sub) Figure 18-3. Standard Operating Voltage Range ...

  • Samsung S3C9228/P9228 - page 454

    S3P9228 OTP S3C9228/P9228 18- 6 NOTES ...

  • Samsung S3C9228/P9228 - page 455

    S3C9228/P9228 DEVEL OPMENT TOOLS 19- 1 19 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating sy ...

  • Samsung S3C9228/P9228 - page 456

    DEVELOPMENT TOOLS S3C9228/P9228 19- 2 BUS SMDS2+ RS-232C POD Probe Adapter PROM/OTP Writer Unit RAM Break/Display Unit Trace/Timer Unit SAM8 Base Unit Power Supply Unit IBM-PC AT or Compatible TB9228 Target Board EVA Chip Target Application System Figure 19-1. SMDS Product Configuration (SMDS2+) ...

  • Samsung S3C9228/P9228 - page 457

    S3C9228/P9228 DEVEL OPMENT TOOLS 19- 3 TB9228 TARGET BOARD The TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ development system. TB9228 SM1347A GND V CC To User_V CC OFF ON SMDS2 SMDS2+ J101 42SDIP J102 44QFP 1 5 15 21 10 42 40 25 22 30 35 1 5 15 22 10 44 40 30 23 35 25 20 P2 25 160 30 20 10 1 150 140 13 ...

  • Samsung S3C9228/P9228 - page 458

    DEVELOPMENT TOOLS S3C9228/P9228 19- 4 Table 19-1. Power Selection Settings for TB9228 "To User_V CC " Settings Operating Mode Comments To User_V CC Off On Target System SMDS2/SMDS2+ TB9228 V CC V SS V CC The SMDS2/SMDS2+ supplies V CC to the target board (evaluation chip) and the target system. To User_V CC Off On Target System SMDS2/SMDS ...

  • Samsung S3C9228/P9228 - page 459

    S3C9228/P9228 DEVEL OPMENT TOOLS 19- 5 SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 19-2. The SMDS2+ Tool Selection Setting "SW1" Settin ...

  • Samsung S3C9228/P9228 - page 460

    DEVELOPMENT TOOLS S3C9228/P9228 19- 6 J101 42-SDIP J102 44-QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47 P6.2 P6.3 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.1 NC NC NC NC P6.1 P6.0 P5.7 P5.6 P5.5 P5.4 ...

  • Samsung S3C9228/P9228 - page 461

    S3C9228/P9228 DEVEL OPMENT TOOLS 19- 7 Target Board Target System Target Cable for Connector Part Name: AP42SD Order Code: SM6538 J101 1 42 21 22 J101 1 42 21 22 50-Pin DIP Connector Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package Target Board Target System 50-Pin Connector Target Cable for 50-pin Connector Part Name: AP50D-A Order Code: SM6 ...

  • Samsung S3C9228/P9228 - page 462

    DEVELOPMENT TOOLS S3C9228/P9228 19- 8 NOTES ...

Manufacturer Samsung Category Microcassette Recorder

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- Samsung technical drawings
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All of them are important, but the most important information from the point of view of use of the device are in the user manual Samsung S3C9228/P9228.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Samsung S3C9228/P9228, service manual, brief instructions and user manuals Samsung S3C9228/P9228. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Samsung S3C9228/P9228.

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A complete manual for the device Samsung S3C9228/P9228, how should it look like?
A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Samsung S3C9228/P9228 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Samsung S3C9228/P9228.

A complete Samsung manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

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