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Manual Intel 21555

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  • Intel 21555 - page 1

    21555 Non-T ransp arent PCI-to- PCI Bridge User Manual July 2001 Order Nu mber: 278 321–00 2 ...

  • Intel 21555 - page 2

    2 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Informati on in this doc ument is provide d in con nection with Intel ® p roducts. No license, e xpress or implie d, by es toppel o r othe rwise, to any inte llectual property rights is granted b y this document . Excep t as provi ded in Int el ’ s T erms an d Cond itions of Sale for s uc ...

  • Intel 21555 - page 3

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 3 Contents Contents 1 Preface ........... ............. ............. .................... ............. ............ ............. .................... ............. .......... 11 1.1 Cautions and Notes .............. ............. ...... ....... ...... ............. ...... ....... .......... ...

  • Intel 21555 - page 4

    4 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Contents 5.2 Posted Writ e Transac ti ons ....... ...... ............. ....... ...... ............. ...... ....... ............. ...... ....... ....... 5 0 5.2.1 Memory W rite Tran saction s ..... ............. ............ .................... ............. ............. ....... 51 5.2.2 Me ...

  • Intel 21555 - page 5

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 5 Contents 9.2 SROMSROM Preload Operation ....... ................... ............. ............. ............. ................... .... 9 1 9.3 SROM Con figuration Da ta Prelo ad Form at .... ............ ............. ............. .................... .......... 92 9.4 SROM Operati on by CS ...

  • Intel 21555 - page 6

    6 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Contents 16.7 Interrupt R egister s ............ ............. .................... ............ ............. ............. ............. ........ .... 170 16.8 Scratchp ad Regist ers .................... ....... ...... ....... ...... ............. ...... ....... ...... ............. ...... ...

  • Intel 21555 - page 7

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 7 Contents 7 Primar y PCI Bus In terface 6 4-Bit Exte nsion S ignals .......... .................... ............. ............. .......... 2 6 8 Secon dary PCI Bus Interfa ce Signa ls .............. ............. ............. ............. ............. ............. .......... 28 9 Secon da ...

  • Intel 21555 - page 8

    8 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Contents 57 Primary Interface Con figur ation Spa ce Addr ess Map ..... ............. ............. ................... ............ 148 58 Seconda ry Interfac e Configur ation Sp ace A ddress Map . ............. ............. ............. .................. 148 59 Vendor I D Register ..... ...

  • Intel 21555 - page 9

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 9 Contents 107 Primary E xpansion ROM BAR ............ .................... ............ ............. ............. .................... ........ 1 75 108 Primary E xpansion ROM Setup Register .. ............. ............ ............. ............. .................... ........ 176 109 ROM ...

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  • Intel 21555 - page 11

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 11 Preface 1 A brief desc ription of the conten ts of this man ual follows. Chapter 1, “ Pr efac e ” Provides information about the contents and organization of this book. Chapter 2, “ Introduction ” Provides an overview of the 21555 functionality and architecture. Chapter 3, “ Signa ...

  • Intel 21555 - page 12

    12 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Preface 1.1 Cautions and Notes Caution: C autions provide in for mat ion to prevent damage to equipment or loss of d a ta. Note: Notes emphasize p articularly important informati on. 1.2 Dat a Unit s This manual uses the followin g da ta- unit ter m inology . 1.3 Numbering All numbers are d ...

  • Intel 21555 - page 13

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 13 Prefac e 1.4 Signal Nomenclatu re 21555 device si gnal n ames are p rinted in lowercas e typ e. Prefixes and suf fixes are tagged with a leading or trailing letter and are delimited with an “ _ ” underscore: • The prefix “ p_ ” d enotes a primary bus s ignal. For example: p_ad is ...

  • Intel 21555 - page 14

    14 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Preface 1.5 Register Abbreviatio ns When a register is associated with the primary interface, its name is preceded with Primary . When a register is associated with the secondar y interface, its name is pr eceded with Secondary . Wh en a register is shared by both interfaces, it is not prec ...

  • Intel 21555 - page 15

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 15 Introduction 2 The Intel ® 21555 is a PCI periph eral dev i ce that perf orm s PCI bri dg ing f unctions f or em bedd ed and i ntel lig ent I/O applications. The 21555 has a 64-bit primary interface, a 64-bit seco ndary interface, and 66-MHz capability . In this document the 21555 non -tra ...

  • Intel 21555 - page 16

    16 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Introduction A primary goal of the PPB architecture is that PPB are tran sparent to devices and device drivers. For ex ample, no changes are needed to a device driver when a PCI peripher al is located behind a PPB. Once configured durin g system initial ization, a PPB operates without the a ...

  • Intel 21555 - page 17

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 17 Introduction Ta b l e 3 shows compares a 215 55 and to a transparent PPB. T abl e 3. 21555 an d PPB Fea ture Comparison Feature Non-T ranspa r ent P PB or 21555 T ransparent PPB Transaction forwarding • Adheres to P PB ordering rules. • Uses posted writes and delayed transactions. • A ...

  • Intel 21555 - page 18

    18 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Introduction 2.2 Architectural Overview This secti on descri bes the buf fers, reg isters, and co ntrol lo gic of the 2155 5: 2.2.1 Da t a Bu ffers Data buf fers include the buf fers along with the associated data path control logic. Delayed transaction buf fers contain the compare function ...

  • Intel 21555 - page 19

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 19 Introduction Figur e 2 shows the 21555 mi croarchitectur e. Figur e 2. 21 555 Mic roarchi tecture A7418-01 Primary Config Registers Device- Specific Config Registers CSR Registers Secondary Config Registers JTAG ROM Interface Control Primary Target Control Primary Master Control Secondary T ...

  • Intel 21555 - page 20

    20 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Introduction 2.3 Special Applications 2.3.1 Primary Bu s VGA Suppo rt The 21555 provides hardware sup port that allows configuration o f itself as a V ideo Graphics Adapter (VGA) device. The prim ary class code should be preloaded through the serial ROM (SROM) o r loaded by the local proces ...

  • Intel 21555 - page 21

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 21 Introduction • Setting a translated bas e addr ess f o r a downstream range to fall within an address r ange defined for upstream forwarding. This would cause the 215 55 to respond as a target o n the secondary bus to a downstream transaction that it has initiated as a master . The transa ...

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    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 23 Signal Descriptions 3 This chapter presents the theory of o peration information about the PCI signal interface. See Chap ter 16 for specific informati on about PCI regist ers. Ta b l e 5 des c ribe s the PC I sig nal grou p s, f unct i o n, a n d pr ovid es a pa g e ref ere nce. T able 5. ...

  • Intel 21555 - page 24

    24 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Signal Descriptions 3.1 Primary PCI Bus Interface Sig nals Ta b l e 6 describes the primary PCI bus interface si gnals. The letters in the “ Ty p e ” column are described in Ta b l e 1 . T able 6 . Pri mary PCI Bus Inter face Sig nals ( Sheet 1 of 2) Signal Name T ype Description p_ad[3 ...

  • Intel 21555 - page 25

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 25 Signal Descriptions p_p ar TS Primary PCI interface parity . Signal p_p ar carries the even parity of the 36 bits of p_ad[31:0] and p_cbe_l[3:0] for both address and data phases. Signal p_pa r is driven by the same agent that drives the addres s (for address parity) or the data (for data p ...

  • Intel 21555 - page 26

    26 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Signal Descriptions 3.2 Primary PCI Bus Interface 64 - Bit Extens ion Sig nals Ta b l e 7 describes the primary PCI bus interface 64 -bit extension signals. Th e letters in the “ Ty p e ” column are desc ribe d in Ta b l e 1 . T able 7 . Pri mary PCI Bus Inter face 64 - Bit Extension Si ...

  • Intel 21555 - page 27

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 27 Signal Descriptions p_p ar64 TS Primary PCI interface upper 32 bits parity . The 21555 does not bus p ark this pin. This pin is tristated during the assertion of p_rst _l . S ignal p_p ar64 is driven to a valid value when the 64-bit extension is disabled ( p_req64_l is deasserted during p_r ...

  • Intel 21555 - page 28

    28 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Signal Descriptions 3.3 Secondary PCI Bu s Interface Signals Ta b l e 8 describes the secondary PCI bus interface signals. Th e letters in the “ Ty p e ” column are described in Ta b l e 1 . T able 8. Secon dar y PCI Bus In ter face Si gnal s (Sh eet 1 o f 2) Signal Name T ype Descripti ...

  • Intel 21555 - page 29

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 29 Signal Descriptions s_p a r TS Secondary PC I interface parity . Signal s_p ar carries the even parity of the 36 bits of s_ad[31:0] and s_cbe_l[3:0] for both address and data phases. Signal s_ p a r is driven by the same agent that drives the address (for address parity) or the dat a (for d ...

  • Intel 21555 - page 30

    30 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Signal Descriptions 3.4 Secondary PCI Bu s Interface 64 - Bit Exten sion Signals Ta b l e 9 describes the secondary PCI bus interface 64-bit extens ion signals. The letters in the “ Ty p e ” column are desc ribe d in Ta b l e 1 . T able 9 . Sec onda ry PCI Bu s Interfa ce 64 - Bit Exten ...

  • Intel 21555 - page 31

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 31 Signal Descriptions 3.5 Miscellaneous Signals Ta b l e 1 0 de scr ib es the miscellaneous s ignals. The letters in the “ T ype ” column are d escribed in Ta b l e 1 . s_p a r6 4 TS Secondary PCI interface upper 32 bits parity . The 21555 does not bus p ark this pin. This pin is tristate ...

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  • Intel 21555 - page 33

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 33 Address Decoding 4 This chapter presents the theo ry of operation information abo ut add res s mapping and deco ding. See Cha pter 1 6 for specific information about addressing registers. The f ollowing areas are covered : • Section 4 .1, “ CSR Address Decod ing ” on pag e 34 . • Se ...

  • Intel 21555 - page 34

    34 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Address Decoding 4.1 CSR Address Deco ding The 21555 implements a set of CSRs tha t are mapped in memory o r in I/O space. The regis ters are mapped independently o n the primary and s econdary interfaces. Th e following BARs are u sed for CSR mappin g: • The primary C SR and: — Downstr ...

  • Intel 21555 - page 35

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 35 Address Decoding 4.3.1 Using the BAR Setup Registe rs All downstream and ups tream BARs have pro grammable sizes, and can be d isabled so that they req uest no space. The Primary CSR and Downs tream Memory 0 B AR cannot be totally disabled, as the 21555 CSRs ar e always mapped in th e botto ...

  • Intel 21555 - page 36

    36 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Address Decoding 4.3.2 Direct Address T r anslation W ith the exception of secondary bus transacti ons falling into the Upstream Memory 2 addres s range (see Section 4.3.3 ) and all dual a ddres s trans actions ( Section 4.3.5 ) , the 2 155 5 u ses d ir ect addr ess tran slation when forwar ...

  • Intel 21555 - page 37

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 37 Address Decoding This new base addres s, also called the translated base add ress, references a new location in the secondary bus address map. The offset is not affected. The process is si milar for transactions forwarded f rom the second ary bus to the primary b us. Each memory address ran ...

  • Intel 21555 - page 38

    38 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Address Decoding The Upstream Memo ry 2 address r ange consists of a fixed number (64) of pages. The page size is programmable in the Chip Control 1 conf iguration regi ster . Th erefore, the size of the Upstream Memory 2 B AR is dependent o n the page size. The page s ize varies between 25 ...

  • Intel 21555 - page 39

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 39 Address Decoding Figur e 7 shows how a translated address is bu ilt using the lookup tab le, assuming a page size of 4 KB . Figur e 8 shows an ex ample of how dif ferent address reg ions might be forward ed upstream using the lookup table address translation. The lookup t able is impl ement ...

  • Intel 21555 - page 40

    40 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Address Decoding Note: The indirect access mechanism mu st be used only by one inter face at a time. When access to the lookup table by multiple mas ters is possible, it is strongly recommended that the Generic Own bits or some other semaphore mechanism be u sed to restrict access to on e m ...

  • Intel 21555 - page 41

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 41 Address Decoding Note: The lookup table is not cleared by reset. Th e lookup table must b e initialized by the local processor before the Upstr eam Memory 2 Address ran ge is used. 4.3.5 Forwarding of 64 - Bit Address Memory T ransactions The 21555 co nsiders the host and lo cal memory spac ...

  • Intel 21555 - page 42

    42 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Address Decoding the Downstream memor y 3 address ran ge must be se t to a non-zero v alue when the upper 32 bits are enabled (a bas e address of 0 is no t allowed). . 4.4 I/O T ransactio n Address Decoding The 21555 provides a mechanism where one BAR on each interface can be conf igured to ...

  • Intel 21555 - page 43

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 43 Address Decoding transaction. One pair is used for down stream I/O transactions an d one pair is used for upstream I/O transactions . The downstream r egisters can only be acc essed from the primary interface, an d the upstream regis ters can only b e accessed from the s econdary interface. ...

  • Intel 21555 - page 44

    44 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Address Decoding 4.4.2 Sub tractive Decoding of I/O T ransactio ns The 21555 can be enabled to sub tractively decode I/O trans actions and forward these transactions to the opposite bus. No address trans lation is performed on subtractively decoded I/O transactions. The transaction is treat ...

  • Intel 21555 - page 45

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 45 Address Decoding Accesses to the 215 55 con figuration space are not o rdered with respect to tr ansactions in the 2155 5 queues. T hat is, the 21555 responds immediately to con figu ration transaction s regardles s of what transactions exist in the ups tream and downstream queues. Exceptio ...

  • Intel 21555 - page 46

    46 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Address Decoding The 21555 provides a semaphor e method that may be used to guarantee atomicity o f the address and data register accesses using the Up stream Configuration Own bit and Downstream Configur ation Own bit. Atomicity of these accesses is not guaranteed in hardware . When the co ...

  • Intel 21555 - page 47

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 47 Address Decoding 4.6 21555 Bar Summary Ta b l e 1 2 shows a summary of the 2155 5 BARs. T abl e 12. Ba r Summary Bar Size Address T ranslation Primary C SR and Dow nstream Memor y 0 4K B t o 2G B Low 4 KB: None Above 4KB bo undary: Direct Offset Primary CSR I/O 256 bytes — Secondary C SR ...

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  • Intel 21555 - page 49

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 49 PCI Bus T ransactions 5 This chapter presents the theory of operation inf ormation about PCI trans actions. See Chapt er 16 f or specific information abou t PCI registers. Th e following sections are d iscussed: • Section 5 .2, “ Posted W rite T ransactions ” on page 50 . • Section ...

  • Intel 21555 - page 50

    50 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual PCI Bus Transact ions 5.2 Posted Write T ransactions This section discusses th e f oll owing Posted Write T ransactions: • Section 5.2.1, “ Memory W r ite T rans actions ” on page 51 . • Section 5.2.2, “ Memory W rite a nd Invalidate T rans actions ” on pag e 51 . • Section 5. ...

  • Intel 21555 - page 51

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 51 PCI Bus T ransa ct ions 5.2.1 Memory W rite T ransactions As a target, the 21555 disconn ects memory write transactions at the following add ress boundaries: • An aligned 4K B address boundary . • An aligned page address bou ndar y for upstream tran sactio ns falling in the Upstream Mem ...

  • Intel 21555 - page 52

    52 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual PCI Bus Transact ions When any of these conditions is not met, the 21555 uses the memory write command. When a subsequent cache line in the transaction does not have all bytes enabled , the 21555 term inat es th e MWI transaction and delivers the remaining data using a memory write command. ...

  • Intel 21555 - page 53

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 53 PCI Bus T ransa ct ions 5.2. 4.3 Write -Through When the 21555 is able to obtain access to the tar get bus and st art transferring write data to th e target before the transaction has been term inated on the initiator bu s, it automatically enters fl ow-through mode. I n flow-through mode, ...

  • Intel 21555 - page 54

    54 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual PCI Bus Transact ions 5.3 Delayed Write T ransactions The 21555 uses delayed transactions when forwarding I/O writes from one PCI interface to the other . Delayed transactions are also us ed for CSR or con figuration register writes that caus e the 21555 to initiate a transaction on the opp ...

  • Intel 21555 - page 55

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 55 PCI Bus T ransa ct ions When the initiator repeats the transaction using the same address, bus command, write data, and byte enables, then the 21555 ret urns the appro priate tar get terminatio n when orderi ng rules allow . Otherwi se, the 2155 5 continues to return target retry . The targ ...

  • Intel 21555 - page 56

    56 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual PCI Bus Transact ions The 21555 requests the target bus and initiates the delayed read transacti on as soon as the 21555 ordering rules allow . See Section 5.7 . When the transaction is a nonpref etchable read as described in Section 5.4.1 , the 21555 requests o nly a single Dword of data. ...

  • Intel 21555 - page 57

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 57 PCI Bus T ransa ct ions 5.4.2 Prefetchable Reads The following trans actions are considered by the 21555 to b e prefetchable read tran sactions: • T ransactions using the memory read line command. • T ransactions using the m emor y read multip le co mman d . • T ransactions using the ...

  • Intel 21555 - page 58

    58 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual PCI Bus Transact ions When using the Quadwo rd bo un dary , REQ 64# asserts every time the transaction is Quadword-aligned ( AD[3:0] = x000b). In some cases, the addr ess is only 2 Dwor ds away from a cache line boundary , or a 4KB boundary . This means that if an ACK64# is not rece ived fr ...

  • Intel 21555 - page 59

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 59 PCI Bus T ransa ct ions 5.4.4.3 Read Qu eue Ful l Thresh old T un ing The 21555 imp lements read queue management co ntrol bits for each read data queue in the Chip C ontrol 1 configuration register . These bits specify at what read-queue threshold the 21555 initiat es a delayed prefetchabl ...

  • Intel 21555 - page 60

    60 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual PCI Bus Transact ions 5.6 T arget T erminations This section describes the following targ et retries, targ et disconnects, an d tar get aborts received and retu rned by th e 21555. • Section 5.6.1, “ T ar get T erminations Retur ned b y the 21555 ” on pag e 60 . • Section 5.6.2, “ ...

  • Intel 21555 - page 61

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 61 PCI Bus T ransa ct ions 5.6.2 T ransaction T ermin ation Errors on the T arget Bus When the 21555 d etects a target abort o n the targ et bus, the 21555 sets the Received T ar get Abort in the Primar y and Secondary S tatus register . See T able 62, “ Primary an d Secondary S tatus Regist ...

  • Intel 21555 - page 62

    62 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual PCI Bus Transact ions • A target retry in response to a posted write is allowed, but only due to temporary conditions, such as a buf fer-fu ll condition. The orderi ng rules ap ply to trans actions crossi ng the bridge i n the same dire ction. — A posted write. — A delayed write and r ...

  • Intel 21555 - page 63

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 63 PCI Bus T ransa ct ions Note: Performance may b e affected if the Delayed T ransaction Order Control bit is set, as the 21555 deasserts the PCI r equest signal between trans actions. When the Delayed T ransaction Order Control bit is zero, t he 21555 may keep REQ# asserted af ter a target r ...

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    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 65 Initialization Requirements 6 This chapter presents the theor y of oper ation in formation about the 21555 initializatio n requirements. See Chapt er 16 fo r specific in for m ation about the initializatio n registers. 6.1 Power Management, Hot-Swap, and R eset Signals Ta b l e 1 7 describe ...

  • Intel 21555 - page 66

    66 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Initialization Requireme nts 6.2 Reset Behavio r The 21555 implements a primary reset input, p_rst_ l , a secondary reset input s_rst _in_l , and a secondary reset output , s_ rst_l . The 21555 also implemen ts a Chip Reset bit and a Secondary Reset bit in the Ta b l e 1 2 3 , “ Reset Con ...

  • Intel 21555 - page 67

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 67 Initialization Requirements The secondary res et output, s_rst_l , is asserted and remains ass erted when any of the fo llowing are true: • The 21555 pri mary rese t input, p_ rst _l , is asserted. • The 21555 s econdary rese t input, s_r st_in_ l , is asserted. • The Secondary Reset ...

  • Intel 21555 - page 68

    68 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Initialization Requireme nts 6.2.1 Central Function Duri ng Reset The 21555 is selected to be the secondar y bus central function when it detects pr_a d[6] low when s_rst_l is asserted. When the 21555 detects this condition, it immediately dr ives s_ad, s_ cbe_l , and s_par low and tristate ...

  • Intel 21555 - page 69

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 69 Initialization Requirements 6.3.1 Wit h SROM, Local, and Host Processors The fol lowing is the 2 1555 initi alization proce dure usin g all configu ration m echanisms: 1. Serial Pr eload Upon deassertio n of p_rst_l or completi on of chip reset, the 21555 automatically starts the serial loa ...

  • Intel 21555 - page 70

    70 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Initialization Requireme nts The remainder o f the 21555 configuration pr oceeds as described in Section 6.3.1 . 6.3.3 Without Local Process or Initialization of the 21555 is poss ible without a local processo r, or without local processor intervention. Serial preload is still perfo rmed as ...

  • Intel 21555 - page 71

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 71 Initialization Requirements 6.4.1 T ransi tions Between Po wer Managem ent St ates The 21555 is put into a different power state by w riting the Power State bits in the Power Managemen t Control and Status co nfi gura tion re giste r . Ta b l e 1 9 sh ows the actions that the 21555 takes wh ...

  • Intel 21555 - page 72

    72 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Initialization Requireme nts 6.4.3 Power Management Dat a Regi ster The PCI Power Management s pecification defines an optional data r egister that can be used for static or dynamic data repo rting. A D ata Select fiel d in the Power Management Control an d S tatus register selects th e typ ...

  • Intel 21555 - page 73

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 73 Initialization Requirements A CompactPCI hot-swap card also implemen ts an indicator LED. When the LED is on, this ind icates that the boar d can be removed f rom the slot. Software may choose to flash the LED to indicate an intermediate state as well. The CompactPCI hot-swap controller con ...

  • Intel 21555 - page 74

    74 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Initialization Requireme nts The 21555 enters the Signal Insertio n state fro m the Ser ial Preload state when the following conditio ns are satisfied: • Serial pr eload is comple te. • Primary Lockou t Reset V alue bit cleared. • Ejector handle is closed (micr o-switch opens, and l_s ...

  • Intel 21555 - page 75

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 75 Initialization Requirements When the INS_ST A T bit is cleared, the card is ready for normal o peration. When l_stat conti nues to be sampled low , that indicates that the ejector handle is closed ( and the micro -switch is open), meaning the card rem ains fully inserted. Th e 21555 enters ...

  • Intel 21555 - page 76

    76 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Initialization Requireme nts However , when the 21555 samples l_st at h igh once the INS_ST A T bit is cleared, this indicates that the ejector handle has been o pened. This is interpreted as a removal event, an d the 21555 enters the Signal Removal state instead. The same is true when the ...

  • Intel 21555 - page 77

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 77 Clocking 7 The 21555 s upports t wo clock inp uts, p_cl k and s_c lk . The signal p_clk corresponds to the p rimary interface and s_clk correspon ds to the secondar y interface. Both clocks must adhere to the PCI Local Bu s specification. The 21555 may operate in eit her synch ronous or asy ...

  • Intel 21555 - page 78

    78 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Clocking 7.2 21555 Secondary Clock Output s When the secon dary clock is not supplied i ndependentl y , the secondary cl ock output i mplemented on th e 21555 can be used in eit her s ynchron ous or as ynchro nous mode . The 21 555 secon dary cl ock ou tput, s_c lk_o , may be buffe red exte ...

  • Intel 21555 - page 79

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 79 Clocking 7.3 66 MHz Support The 21555 s upports 66 MHz operation. It has two p ins, p_m66ena and s_ m66en a , that indicate whether the primary and s econdary bus are operating at 66 MHz, respectively . Signal p_m66e na is an input- only pin. • When sampl ed high, t he primary bus is assu ...

  • Intel 21555 - page 80

    ...

  • Intel 21555 - page 81

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 81 Parallel ROM Interface 8 This chapter presents the theory of operation inf ormation about the 21555 Parallel R OM (PROM) interface. See Chapt er 16 fo r specific information about the PROM registers. The 21555 supp orts the attachment of a standard PROM or EPROM wit h the addition of a sma ...

  • Intel 21555 - page 82

    82 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Paral lel ROM Int erface T able 2 1. PROM I nterface Signa ls (Sheet 1 of 2 ) Signal Name T ype Description pr_ad[7:0] TS These signals interface to both the serial and parallel external ROM circuitry and have multiple functions. The signals pr_ad[7:0] serv e as multiplexed address/data for ...

  • Intel 21555 - page 83

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 83 Paral lel ROM Int erface pr_ale_l O PROM address latch enable/c hip select decoder enable. The signal p r_ale_l is used to enable the PROM address latc hes. The 21555 asserts pr_ale_l low when it drives the first eight bi ts of the 24-bit address on pr_ad[7:0] , and keeps it assert ed until ...

  • Intel 21555 - page 84

    84 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Paral lel ROM Int erface 8.2 Parallel and Serial ROM Con nection Figur e 14 shows how a parallel an d serial R OM can be conn ected to th e 21555 . This fig ure illu st rates the connection of a 16MB ROM. When a smaller RO M is used, the address regis ters correspond ing to the upper addres ...

  • Intel 21555 - page 85

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 85 Paral lel ROM Int erface When a byte read of th e PROM is perfor med, the 2 1555 follows this sequence on the ROM interface, als o shown in Figur e 15 . 1. The 21555 drives address b its [23:16 ] on the p r_ad[ 7:0] pin s and assert s pr_ale _l to enable the addr ess registers. 2. The 21555 ...

  • Intel 21555 - page 86

    86 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Paral lel ROM Int erface 8.4 PROM Write by CSR Access Byte writes of the PROM can be per formed by CSR acces s of the T able 1 12, “ RO M Control Register ” on page 178 , T ab l e 111, “ ROM Address Regis ter ” on p a ge 178 , and T able 110, “ ROM Da ta Regi ster ” on page 177 ...

  • Intel 21555 - page 87

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 87 Paral lel ROM Int erface . 8.5 PROM Dword Read A Dword read is performed on the PROM interface when a read is in itiated on the primary bus whose add ress falls into the address range defined by the Ta b l e 1 0 7 , “ Prima ry Exp ansi o n ROM BAR ” on page 175 . The 215 55 treats a mem ...

  • Intel 21555 - page 88

    88 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Paral lel ROM Int erface 8.6 Access Time and Strobe Control The 21555 controls both the access time and the read and write strobe timing thro ugh the ROM Setup CSR. The access time is specified as a multiple of the p_clk signal and mu st be set to 8, 16, 64, o r 256 times t he len gth o f a ...

  • Intel 21555 - page 89

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 89 Paral lel ROM Int erface 8.7 Att ac hing Additio nal Devices to the ROM Interface The 21555 allows add itional devices to be attached to the ROM interface. T wo ROM interface sign als are slightly redefined to support multi ple devices by setting the Multiple Device Enable bit in the Chip C ...

  • Intel 21555 - page 90

    90 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Paral lel ROM Int erface . Figure 18. Attaching Mu ltiple Device s on th e ROM In terface A7473-01 Other Device Selects Other Device Read Strobe Other Device Write Strobe Other Device Data Other Device Ready Line 21555 pr_ad[7:0] pr_wr_l pr_rd_l pr_cs_l(pr_rdy) sr_cs sr_cs sr_ck sr_di sr_do ...

  • Intel 21555 - page 91

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 91 Serial ROM Interface 9 This chapter presents the theory of operation inf ormation about the 21555 Serial R OM (SROM) interface. See Chapt er 16 fo r specific information about the SROM registers. The serial ROM interface is used to preload data into the 215 55 configuration regi sters with ...

  • Intel 21555 - page 92

    92 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Serial RO M Interface 9.3 SROM Conf iguration Data Preload Format Some fields of the 21555 configur ation registers m ay be preloaded usin g the SROM interface. The f irst two bits read from th e SROM after the completion o f chip reset indicate whether a r egister preload shou ld be perfor ...

  • Intel 21555 - page 93

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 93 Serial RO M Interf ace Prior to a SROM write or write all transacti on, the 8-bit write data must be written in the ROM Data CS R. T o i nitiate the SROM access, the SROM Star t bit in the ROM Control CSR is written with a 1 (the P ROM Start bit must be written to a 0 with this access). The ...

  • Intel 21555 - page 94

    94 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Serial RO M Interface Note: When a SROM access using the CSR mechanism is attempted when the SROM is not implemented, the ROM interface may hang. This pre vents access to any PROMs that may be present. A chip reset may be needed to put the R OM interface in an operational state . Figure 19. ...

  • Intel 21555 - page 95

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 95 Serial RO M Interf ace Figure 22 . SROM Eras e Timing Diagram Figure 23 . SROM Eras e All Ope ration Figure 24 . SROM Chec k St atus Timing Diagram A7479-01 A8 A0 111 pr_ad[1] (sr_di) sr_cs pr_ad[0] (sr_ck) A7480-01 11 00 0 pr_ad[1] (sr_di) sr_cs pr_ad[0] (sr_ck) A7481-01 pr_ad[2] (sr_di) s ...

  • Intel 21555 - page 96

    ...

  • Intel 21555 - page 97

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 97 Arbitration 10 This chapter describes t he arbitrati on signal s. It also describes ho w the 21555 i mplements primar y and second ary PCI bus arbitration. See Chapt er 16 for s pecific information about the Arbiter r egisters. 10.1 Primary PC I Bus Arbitration Signal s Ta b l e 2 3 describ ...

  • Intel 21555 - page 98

    98 21555 No n-Transpare nt PCI-to-PCI Br idge User Man ual Arbitration 10.3 Primary PCI Bus Arbitration The 21555 implements primary PCI bus request and grant pi ns, p_req_l and p_gnt_ l , that interface to an external primary bus arb iter . Thes e pins are used when the 2 1555 wants to initiate a trans action on the primary PCI bus. The 21555 asse ...

  • Intel 21555 - page 99

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 99 Arbitration . Each bus master , including the 2155 5, may be configured t o be in either the low prior ity group or the high pr iority group by setting the corresponding priority bit in the Arbiter Control register in device-specific configuration space. When the bit is set to a one, the ma ...

  • Intel 21555 - page 100

    100 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual Arbitration The 21555 ’ s inter nal arbiter may be progr ammed to park the secondary PCI bus either at the last master to us e the bus, or always on the 21 555 . In the former case, an in itiator' s seco ndar y b us gr ant rem ains asserted un less and un til another initiator has as ...

  • Intel 21555 - page 101

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 101 Interrupt and Scratchpad Registers 11 This chapter presents the theor y of oper ation in formation about the 21555 inte rrupt han dling and about the 32-bit scratchpad registers. See Chapt er 16 fo r specific information about these reg isters. 1 1.1 Primary a nd Secondary PCI Bu s Interru ...

  • Intel 21555 - page 102

    102 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual Interrupt and Scratc hpa d Registers — Cleared by writ ing a 1 to the corresponding status bit in the Upstream Page Boun dary IRQ 0 or 1 regist ers. — Asserts s_inta _l when the corresponding mask bit is zero. • A subsystem event is indicated by a rising edge on s_pme_l . — Cleared b ...

  • Intel 21555 - page 103

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 103 Interrupt and Scratc hpad Registers 1 1.3 Do orbell Interru pt s A 16-bit software controlled interrupt request register and an associated 1 6-bit mask register is implemented for each interface (primary and secondary). Each register is b yte addressable for us e as two sets of 8 -bit inte ...

  • Intel 21555 - page 104

    ...

  • Intel 21555 - page 105

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 105 Error Handling 12 This chapter presents the theory of operation information about the 21555 Error handling capability . See Chapt er 16 for specif ic informati on about t he Error regis ters. 12.1 Error Signals This section describes bo th the pri mary and second ary PCI bu s error sig nal ...

  • Intel 21555 - page 106

    106 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual Error Hand ling 12.1.2 Second ary PCI Bus Erro r Signals Ta b l e 2 8 describes the s econdary PCI b us error signals . T able 2 8. Sec ondary PCI B us Ar bitration Si gnals Signal Name T ype Description s_perr_l STS Secondary PCI interface PERR# . Signal s_perr_l is asserted when a data p a ...

  • Intel 21555 - page 107

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 107 Error Hand ling 12.2 Parity Errors The 21555 ch ecks, forwards , and generat es parity on both the pr imary and s econdary buses . When forwar ding transactions, the 21555 forwards the data parity cond itio n as queued, whether it is bad parity or good par ity . Ta b l e 2 9 describes the ...

  • Intel 21555 - page 108

    108 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual Error Hand ling Data P ar ity Error on Primary Bus Downstream Delayed Write 0 | — • Queues and forwards transac tion with parity error . • Sets primary Pa rity Error D etected bit. 1 | — • Returns TRDY# (and STOP # when multiple data phases requested). • T ransaction not forwarde ...

  • Intel 21555 - page 109

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 109 Error Hand ling Dat a Pari ty Error on Secondary Bus Downstream Posted Write — | 0 T ransaction complet es normally on secondary bus . — | 1 • Transaction completes on secondary bus. • Sets secondary Data Parity Detect ed bit when s_perr_l is asserted. 1 | 1 • T ransaction c ompl ...

  • Intel 21555 - page 110

    110 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual Error Hand ling 12.3 System Error (SERR#) Reporting The 21555 has two sys tem error pins . Signal p_serr_l r eports system erro rs on the pr imary interface, and s_serr_l reports s ystem errors on the secondary interface. For the 215 55 to assert the SE RR # signal for th at interface, the S ...

  • Intel 21555 - page 111

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 111 JT AG T est Port 13 This chapter presents the theory of operatio n information about the 215 55 JT AG interface. See Chapt er 16 for specific information about the JT AG registers. The 21555 ’ s implementation of the JT AG test port is according to IEEE S td. 1 149.1, I EEE Standard T es ...

  • Intel 21555 - page 112

    112 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual JT AG Test Port 13.2 T est Access Port Co ntroller The test access port con troller is a finite-state machine that interp rets IEEE 1 149.1 pro tocols received t hrough th e tms signal. The s tate transitions in the contr oller are caused by the tms signal on the rising edge of tck . In each ...

  • Intel 21555 - page 113

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 113 I2O Support 14 This chapter presents the theory of operatio n information about the 2 1555 I20 suppo rt. See Chap ter 16 f or specific informati on about I20 registers. The 21555 imp lements an I2O mes saging unit to allow passing of I2O messages between th e host system and the local subs ...

  • Intel 21555 - page 114

    114 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual I2O Support The 21555 implements the following hardware for t he Inbound Q ueue: • T able 85, “ I2O Inbo und Queue ” on page 166 register at C SR offs et 40h. • T able 87, “ I2O Inbo und Free_Lis t Head Pointer ” on page 167 at CSR offs et 48h. • T able 88, “ I2O Inbound Post ...

  • Intel 21555 - page 115

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 115 I2O Support processor removes the mes sage from the Inbound Pos t_List, i t must writ e bit 31 of the Inbou nd Post_List counter with a 0, which causes the 2 1555 to decrement the In bound Post_List counter by 1. When the counter decr ements to zero, the 215 55 deasserts s_inta _l , indica ...

  • Intel 21555 - page 116

    116 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual I2O Support and asserts p_inta_l to indicate to the host pr ocessor that one or more MF A s exist in the Outb oun d Post_List . Signal p_ inta _l remains asserted until either the Outbound Post_List Counter is zero and the outbound prefetch buffer empties, or the Outbound Post_List Mask bit ...

  • Intel 21555 - page 117

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 117 I2O Support • All MF A coun ters m aintained by the 21555 may be individually lo aded with any data value by writing a 1 to bit 31 of the corresp onding cou nter Dword of fset. When either the Inbound Free_List Coun ter or the Outbou nd Post_List Counter is loaded, the 21 555 discards an ...

  • Intel 21555 - page 118

    ...

  • Intel 21555 - page 119

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 119 VPD Support 15 This chapter presents th e theor y of oper ation in for m atio n about the 21555 V ital Product Data (VPD) support. See Chapt er 16 fo r specific information about the VPD registers. The 21555 pro vides VPD supp ort thr oug h its serial ROM interf ace. Note that VPD support ...

  • Intel 21555 - page 120

    120 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual VPD Support 15.2 W riting VPD Inform ation A write can occur on ly to the last 2 Kb (256 bytes) of VPD Space. V alid VPD byte addresses fo r write operations are 17F:080h. T o wr ite VPD in formation from the serial RO M, the following steps m ust be taken : 1. The VPD data register is writt ...

  • Intel 21555 - page 121

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 121 List of Registers List of Registers 16 This chapter contains r eference infor mation abou t all of the 215 55 regist ers. Ta b l e 3 1 is a cross reference between the sections in this chap ter to there accompanying th eory of oper ation chapters. 16.1 Reg ister Summary This chapter lists ...

  • Intel 21555 - page 122

    122 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers • “ Vi a S e t u p ” refers to the base ad dress setup regist er corresponding to that BAR 16.2 Configu ratio n Registers Ta b l e 3 2 lists the configuration space addres s registers. T able 32. Configuration Sp ace Address Register (Sheet 1 of 5) Byte Offset (Hex) R ...

  • Intel 21555 - page 123

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 123 List of Registers 2F: 2E 6F: 6E Subsystem ID R egister , page 154 0000 Y Secondary Y 33:30 (P) 73:70 (S) Primary Expansion ROM BAR, page 175 00000000 Via Setup Via Setup Y 34 74 Enhanced Capabilities Pointer Register , page 154 DC — NY 37:35 (P) 77:75 (S) Reserved 000000 — NY 3B: 38 ( ...

  • Intel 21555 - page 124

    124 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 7D (P) 3D (S) Primar y and Secondary Interrupt Pin Registers, page 155 00 — NY 7E (P) 3E (S) Primary a nd Secondary Minimum Grant Registers, p age 155 00 Y N Y 7F (P) 3F (S) Primary a nd Secondary Maximum Latency Register s, page 155 00 Y N Y 83:80 Downstream and Upstream ...

  • Intel 21555 - page 125

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 125 List of Registers C7: C4 Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers, page 138 0000000 0 Y Secondary Y CB:C 8 Downstream Memor y 0, 2, 3, and Upstream Memory 1 Setup Registers, page 139 00000000 Y Secondary Y CD: CC Chip Control 0 Regist er , page 156 0y00 y = 0 ...

  • Intel 21555 - page 126

    126 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 16.3 Control and St atus Registers The control and status registers are memory mapp ed in the Primary CSR and Memory 0 Base Address window and the Secondary C SR Base Address window . These registers are I/O mapped in the Primary CSR I/O BAse Addr ess window and the Secon d ...

  • Intel 21555 - page 127

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 127 List of Registers 01B:018 Downs tream I/O Data and Upstream I/O Data Registers, p age 145 Downstream I/O Data Indeterminate Primary P rimary 01F:01C Downstream I/O Address and Upstream I/O Address Registers , page 144 Upstream I/O Address Indeterminate Secondary Y 023:020 Downstream I/O Da ...

  • Intel 21555 - page 128

    128 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 057:054 I2O Out bound Post_List Head Pointer , page 167 I20 Outbound Post Head Pointer Indeterminate Y Y 05B:058 I2O Inbound Post_List Counter , p age 168 I20 Inbound Post Counter 00000000 Second ary Y 05F:05C I2O Inbound Free_List Counter , page 168 I20 Inbound Free Counte ...

  • Intel 21555 - page 129

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 129 List of Registers 093:090 Upstream Page Boundary IRQ M ask 0 Register , page 172 Upstream Page Boundary IRQ M ask 0 FFFFFFFF Y Y 097:094 Upstream Page Boundary IRQ M ask 1 Register , page 172 Upstream Page Boundary IRQ M ask 1 FFFFFFFF Y Y 099:098 Primary Clear IRQ and Secondary Clea r IRQ ...

  • Intel 21555 - page 130

    130 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 16.4 Address Deco ding 16.4.1 Primary and Secondary Address This secti on covers pages 16-130 throug h 16-140 and includes tables Ta b l e 3 4 throug h Ta b l e 6 0 . See Chapter 4 for theory of operation inform ation. 0FF:0D0 Reserved 00000000 N Y 1FF:100 Upstream Memory 2 ...

  • Intel 21555 - page 131

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 131 List of Registers 3 Prefetchable R Indicates whether the region is prefetchable. Acces ses to the 21555 r egisters are disconnected after the f irst data phase. • When 0, nonprefe tchable memory is request ed. • When 1, prefetchable mem ory is requested. • Reset value is 0 11 : 4 — ...

  • Intel 21555 - page 132

    132 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 3 Prefetchable R Indicates if this space is pr efetchable. • When a 0, do not use pref etching when reading the 21555 registers. 11 : 4 — R Returns zero. 31:12 Base Address R/W Indicate to configuration software the size of the requested memory address range and set the ...

  • Intel 21555 - page 133

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 133 List of Registers T able 37 . Downstream I/O or Memory 1 and Upstream I/O or Memor y 0 BAR Bit Name R/W Description 0 S pace Indicator R • When a 0 , this BAR is disabled or memory space is requested memory spa ce. • When a one (1), I/O space is requested. • Reset value is 0 2:1 T yp ...

  • Intel 21555 - page 134

    134 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 3 8. Downstr eam Memory 2 and 3 BAR , and Upstream Me mory 1 BAR Bit Name R/W Description 0 Space Indicator R Reads only as 0 to indicate that me mory space is requested. 2:1 T ype R Indicates size and location of this address space. Reset value is 00 to indicate tha ...

  • Intel 21555 - page 135

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 135 List of Registers T abl e 39. Up per 32 Bits Downstrea m Memory 3 Bar • Primary byte offset: 27:24h • Secondary byte offset: 67:64h Bit Name R/W Description 31:0 B ase Addres s R/W This register defines t he upper 32 bits of a memory range for downstream forwarding of memory transactio ...

  • Intel 21555 - page 136

    136 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers Ta b l e 4 1 . Downst ream I/O or Memo ry 1 and Up stre am I/O or Memor y 0 T ran slate d Base Regist er Bit Name R/W Description 5:0 Reserved R Res erved. Returns 0 when read. 31:6 XLA T _BASE R/W Contains the translated base address for downstream or upstream transactions ...

  • Intel 21555 - page 137

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 137 List of Registers Ta b l e 4 2 . Downstream Memory 0, 2, 3, and Up strea m Memory 1 T ran slated Bas e Regist er These registers contain the translated base addresses for their respective downstream and upstream BARs. The base address of the transaction on the ini tiator bus is replaced by ...

  • Intel 21555 - page 138

    138 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 4 3. Downstr eam I/O o r Memory 1 and Upstream I/O or Me mory 0 S etup Regist ers These register s may be preloaded by serial ROM or p rogrammed by the local process or before host con figu rat ion. Bit Name R/W Descri ption 0 T ype Selector R/(WS) • When 0, t he B ...

  • Intel 21555 - page 139

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 139 List of Registers T abl e 44. Do wnstre am Memory 0, 2, 3, an d Up stream Memory 1 Setup Re gisters These registers are u sed to program the type and size of their respective ups tream and downstream BA Rs . Bit Name R/W Description 0 T ype Selec tor R Read only as 0 to indicate memory spa ...

  • Intel 21555 - page 140

    140 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 16.4.2 C onfiguratio n T ransaction G eneration Registers All of these reg isters are mapped in to the 21555 configuration s pace and described in Section 16.4.2 . Note that the 21555 initiates a transaction only when the Conf ig uration Data registers are accessed at these ...

  • Intel 21555 - page 141

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 141 List of Registers . T abl e 46. Do wnstre am and Upstream Configu ration A ddress Regis ters This section describes both the downst ream and upst ream versions of the registers. Th ese registers are also map ped in memory and I /O space. Bit Name R/W Description 31: 0 CFG_ADDR (CA) DCA: R/ ...

  • Intel 21555 - page 142

    142 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 47. Downstream Configuration Data and Up stream Configuration Dat a Registers These registers are also mapped in memory and I /O space. This register is treated as a reserved register for all memory accesses. Bit Name R/W Descri ption 31:0 CFG_DA T A (CD) DCD: R/(WP) ...

  • Intel 21555 - page 143

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 143 List of Registers 7:1 Reserved R Read only as 0. 8 Upstream Configuration Own Bit R0TS (S) R(P) Indicates ownership of the U pstream Configuration Addres s and Upstream Configuration Data registers. • When 0, u pstream Configuration Address and Upstream Configuration Data registers are n ...

  • Intel 21555 - page 144

    144 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 9 Upstream Configuration Control R/W Enables the 21555 to perform upstream indirect configuration transactions. • Whe n 0, t he 21555 will not initiate a configuration transaction on the primary interface when the Upstream Configuration Data regist er is accessed. The Ups ...

  • Intel 21555 - page 145

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 145 List of Registers T abl e 51. Do wnstre am I/O Data and Upstream I/O Da t a Regist ers The Downstream I/O Data register is used for I/O transacti ons to be initiat ed on the secondary bus, and the Ups tream I/O Data register is used for I/O transactio ns to be initiated on the primary bus. ...

  • Intel 21555 - page 146

    146 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers Ta b l e 5 3 . I / O C S R • Byte Offset: 027:026h Bit Name R/W Description 0 Downstream I/O Own Bit S tatus R This bit reflects the status of the Secondary Own bit used for generating I/O transaction on the secondary bus. • When 0, t he Downstream I/O Address and Downs ...

  • Intel 21555 - page 147

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 147 List of Registers 16.5 PCI R egisters This sectio n covers p ages 16-147 through 16-165 and Ta b l e 5 7 through Ta b l e 8 0 . S ee Chapter 3 or Cha pter 5 for theory of operation in formation. 16.5.1 Co nfigu ration Registers The registers d escribed in this section are s hared between t ...

  • Intel 21555 - page 148

    148 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 5 7. Pri mary Int erface Con figuration Sp ace Addre ss Map Byte 3 Byte 2 Byte 1 Byte 0 Primary Offset Secondary Offset De vice ID 1 V endor ID 1 00h 40h Primar y S t atus P rimary C ommand 04h 44h Primary Class Code 2 Revisi on ID 1 08h 48h BIST 1 , 2 Header T ype 1 ...

  • Intel 21555 - page 149

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 149 List of Registers 16.5.2 Primary and Secondary Command Register s The register types in this section have s eparate regist ers for the primary and secondary interf aces. However , the register des cription is given once, and applies t o both the pri mary and secon dary configura tion regi ...

  • Intel 21555 - page 150

    150 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 7 Wa i t C y c l e Control R Reads as zer o to indicate the 21555 does not p erform address or data stepping. 8 SERR# Enable R/W Controls the enable for SERR# on the corresponding interface. • When 0, SERR# cannot be driven by the 21555. • When 1, SERR# may be driven lo ...

  • Intel 21555 - page 151

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 151 List of Registers 8 Data P arity Det ect ed R/ W1 TC This bit is set to a 1 when all of the following are true: • The 21555 is a master on t he corresponding bus. • PERR# is detected asser ted for writes or a parity error is detected for reads. • Parity Error Response bit is set in t ...

  • Intel 21555 - page 152

    152 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 64. Primary and Secondary Class Code Registers These registers may be preloaded through the serial ROM. The Primary Class Code register may also be programmed by the local processor before host configuration . Bit Name R/W Description 7:0 Prog IF (PIF) PPIF: R/( WS) ...

  • Intel 21555 - page 153

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 153 List of Registers T abl e 66. Primary La tency an d Secon dary Mas ter Latenc y Timer Register s Bit Name R/W Description 7:0 Master Latency Ti m e r R/W Master latency timer for the corresponding interface. Indicate s the number of PCI clock cycles from the assertion of FRAME # to the exp ...

  • Intel 21555 - page 154

    154 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers Pr T able 69. Subsystem V endor ID Register • Primary byt e offset: 2D:2Ch and 6D:6Ch • Secondary byt e offset: 6D:6Ch and 2D:2Ch Bit Name R/W Description 15:0 Subsystem V endor ID R/ (WS ) Identifies the vendor of the add - in card or sub system. This register is initi ...

  • Intel 21555 - page 155

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 155 List of Registers T able 73. Primary and Secondary Interrupt Pin Registers Bit Name R/W Descriptio n 7:0 Interr upt Pin R Thi s register indicates which P CI interrupt pin the 21555 uses on the corresponding bus. This is a read - only r egister and a lways returns 1 when read indicating th ...

  • Intel 21555 - page 156

    156 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 16.5.3 De vice - S pecific Control and S t atus Regist ers This section contains information about the device-s pecific control and status registers. T able 7 6. Devic e - S pecific Control and St atus Address Map Byte 3 Byte 2 Byte 1 Byte 0 Primary Offset Secondary Offset ...

  • Intel 21555 - page 157

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 157 List of Registers 3 Secondary Master Timeout R/ W Sets the maximum number of PCI clock cycles that the 21555 wait s for an initiator on the secondary bus to repeat a delayed transaction request. The counter starts when the de layed transaction com pletion is ready to be returned to the ini ...

  • Intel 21555 - page 158

    158 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 8 Upstream DAC Prefetch Disable R/W Controls prefetching for upstream dual address transacti ons using the memory read b us comm and. Whe n 0, prefetching is perform ed for upstream DAC memo ry reads. When 1, upstream DACs using the memory read bus command are not prefetche ...

  • Intel 21555 - page 159

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 159 List of Registers 12 LUT Page Size Extension Bit R/ W Allows selection of larger p age sizes when programming the page size field in the Chip Control 1 configuration register . • When 0, page sizes 256 bytes through 4 MB are available in t he p age size field. • When 1, page sizes 8 MB ...

  • Intel 21555 - page 160

    160 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 7 8. Chip Control 1 R egister (Sheet 1 of 3) This register may be preloaded by serial ROM or programmed by the local proces sor before hos t configuration. • Prima ry b yte o ffset: CF:C Eh • Secondary byt e offset: CF:CEh Bit Name R/W Description 0 Primary Poste ...

  • Intel 21555 - page 161

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 161 List of Registers 7:6 Subtractive Decode Enable R/W Controls subtractive dec oding for downstream and upstream I/O transactions. When the 21555 is enabled to perform subtractive decoding in one direction, those transactions are forwarded to the opposite bus with no address translation. Pos ...

  • Intel 21555 - page 162

    162 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 12 I 20_ENA R/W Enables the I20 message unit. • When 0, the I20 message unit is disabled. Memory accesses to the Inbound and Outbound FIFO registers at CSR offset s 40h and 44h result in TRDY# and discarded data on writes, and TRDY# wi th a return of FFFFFFFFh on r eads. ...

  • Intel 21555 - page 163

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 163 List of Registers 3 Downstream Posted Write Data Discarded R/W1 TC This bit is set t o a 1 an d p_serr_l is conditionally asserted when the 21555 discards a downstream posted writ e transaction after receiving 2 24 target retries from the secondary bus target (Retry counters must not be di ...

  • Intel 21555 - page 164

    164 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 80. Generic Own Bits Register The 21555 implem ents two generic own bits that can be accessed in either memory or I/O space fro m either the primary or secondary interface. These bits may be used as an aid to lock resources in software. When a bus master reads the Ow ...

  • Intel 21555 - page 165

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 165 List of Registers 16.6 I2O Registers This section contains a description of the I2O registers. See Chapter 14 for theory of operation information . T able 81. I2O Outbound Post_List S t atus Byte Offset: 33:30h Bit Name R/W Descriptio n 2:0 Reserved R Reserved. Read only as 0. 3 Outbound P ...

  • Intel 21555 - page 166

    166 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 84. I2O Inbound Post_List Interrupt Mask Byte Offs et: 3F : 3 C h Bit Name R/W Description 2:0 Reserved R Reserved. Read only as 0. 3 Inbound Post Mask R/W Interrupt mask for Inbound Post_List S tatus. • When 0, the 21555 asserts s_int a_l when the Inbound Post_Lis ...

  • Intel 21555 - page 167

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 167 List of Registers T able 87. I2 O Inbound Free_List Head Pointer Byte Offsets: 04B:048h Bit N ame R/W Description 1:0 R eserved R Reserved. Returns 0 when read. 31: 2 Inbound Free Head Ptr R/W S pecifies the local me mory Dword addr ess of the Inbound Free_List Head Pointer . Increments wh ...

  • Intel 21555 - page 168

    168 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 91. I2O Inbound Post_List Counter Byte Offsets: 05B:058h Bit Name R/ W Description 15:0 I nbound Post Ctr R/(WS) When read, returns the number of entries in the Inbound Post_List. Decrements by 1 when this location is writt en from the secondary interface wit h any d ...

  • Intel 21555 - page 169

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 169 List of Registers T able 93. I2 O Outbound Post_List Counte r Byte Offsets: 063:060h Bit Name R/W Description 15:0 Outbound Post Ctr R/(WS) When read, returns the number of entries in t he Outbound Post_List. Increments by 1 when this location is writ ten from the secondary interfac e with ...

  • Intel 21555 - page 170

    170 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 16.7 Interrupt Registers This section contains informatio n about inter rupt registers. See Chapt er 1 1 for theory of operation information . T abl e 95. Chip St atus CS R Byte Offsets: 083:082h Bit Name R/W Description 0 PM_D0 R/W1 TC Power Management Tr ansi tion to D0. ...

  • Intel 21555 - page 171

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 171 List of Registers T abl e 97. Ch ip Clear IRQ Mask Register Byte Offsets: 087:086h Bit Name R/W Descri ption 0 Clr_D0M R/W1 TC • When 0, signal s_inta_l is asserted on the 21555 ’ s secondary interface when the corr esponding chip event bit is a 1, indicating a return of power state to ...

  • Intel 21555 - page 172

    172 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 9 9. Upstream Page Bo undary IRQ 1 Regist er Byte Offs et: 08F : 08C h Bit Name R/W Description 31:0 P AGE1_IRQ R/W1 TC Each bit in this register corresp onds to a page entry in the upper ha lf of the Upstream Memory 2 range. Bit 0 corresponds to the 33 rd page, and ...

  • Intel 21555 - page 173

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 173 List of Registers T abl e 102. Primary Clear IRQ a nd Sec ondary Clear IRQ Reg isters These registers affect primary and secon dary interrup ts in the same way and are des cribed together. Bit Name R/W Descri ption 15 :0 CL R_IR Q R/W 1 TC This register controls the state of the P rimary o ...

  • Intel 21555 - page 174

    174 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 16.8 Scratchp ad Registers See Chapte r 1 1 for theory of operation i nformatio n. T able 104. Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers Bit Name R/W Description 15:0 CLR_IRQM R/W1 TC • When 0, an interrupt is generated on the 21555 ’ s primary or se ...

  • Intel 21555 - page 175

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 175 List of Registers 16.9 PROM Registers This secti on describes the six PR OM registers. See Chapt er 8 for theor y of operati on informat ion. . 31:0 S CRA TCH3 R/W 0B7:0B4h 3 2-bit scratchpad register 3. 31:0 S CRA TCH4 R/W 0BB:0B8h 32-bit scratchpad register 4. 31:0 S CRA TCH5 R/W 0BF:0BC ...

  • Intel 21555 - page 176

    176 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 108. Primary Exp ansion ROM Setup Register This register may be preloaded by serial ROM or programmed by the local proces sor before hos t configuration. • Primary byt e offset: C3:C0h • Secondary byt e offset: C3:C0h Bit Name R/W Descri ption 1 1:0 Reserved R R ...

  • Intel 21555 - page 177

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 177 List of Registers T abl e 109. ROM Se tup Reg ister Byte Offsets: 0C9:0C8h Bit Name R /W Descri ption 1:0 Acc ess Time R/W Number of p_clk cycles that pr_cs_l asserts low (in default mode) or pr_ale_l drives high (in multiple device mode ) for a PROM or other ext ernal device access. Possi ...

  • Intel 21555 - page 178

    178 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 1 1 1. ROM Add ress Reg ister Byte Offs ets: 0C E: 0 C C h Bit Name R/W Description 23:0 ROM_A DDR R/W Contains the byte address of the PROM read or write access us ed when the PR O M Start bit is set to a 1. Contains the byte address and Opcode us ed when the Serial ...

  • Intel 21555 - page 179

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 179 List of Registers 16.10 SROM Registers This sections describes the SROM re gisters. See Chapter 9 for theory of operation informatio n. 2 Read/Write Control R/W PROM read/write control bit. This bit may be written with the same CSR access that sets the PROM S tart bit. • When 0, the 2155 ...

  • Intel 21555 - page 180

    180 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 3 s_clk_o Enable R Indicates whether s_clk_o is enabled, determined by sampling pr_ad[5] during reset. • When 0, signal p r _ad [5] was s ampled low , causing s_clk_o to be disabled. • When 1, signal p r _ad [5] was sampled high, causing s_clk_o to be enabled. 4 Seconda ...

  • Intel 21555 - page 181

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 181 List of Registers 09h Subsyste m ID [ 7:0] 0Ah Subsystem ID [15:8] 0Bh Primary Minimum Grant 0Ch Primary Maxim u m Laten cy 0Dh Secondary Progr amm ing Interface 0Eh Secondary Sub - Class Code 0Fh Second ary Base Class Code 10h Second ary Minimum Grant 1 1h Secondary Maximum Late n cy 12h ...

  • Intel 21555 - page 182

    182 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 2Bh Upstream I/O or M emory 0 S etup [31:24] 2Ch Upstream Memory 1 Setup [7:0]. Bits [0, 7:4] are not loaded and should be 0. 2Dh Upstream Memory 1 Setup [15:8]. Bits [1 1:8] are not loaded and should be 0. 2Eh Upstream Memory 1 Setup [23:16] 2Fh Upstream Memor y 1 Setup [3 ...

  • Intel 21555 - page 183

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 183 List of Registers 16.1 1 Arbiter Contro l This chapter describes the arbitration contro l registers. See Ch apter 1 0 for theory of operation information. 16.12 Error Registers This section describes the primary and se condary SERR# disabl e registers. See Ch apte r 12 for th eory of opera ...

  • Intel 21555 - page 184

    184 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 1 16. Primar y SERR # Disable Register This register may be preloaded by serial ROM or programmed by the local proces sor before hos t configuration. This register controls the ability of the 21 555 to assert p_serr_l for a particular condition. When the bit is a 0, ...

  • Intel 21555 - page 185

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 185 List of Registers 16.1 3 Init Registers This section describes the Power management, Reset, and Hot-swap registers. See Chap ter 2 for theory of operatio n informati on. 1 Upstream Delayed Read T ransaction Discarded R/W Disables s_serr_l assertion when t he 215 55 discards an upstream del ...

  • Intel 21555 - page 186

    186 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers . T able 1 19. Power Ma nagement Capabilities Registe r Bits [14:9,5,2:0] are loadable through t he serial ROM or are program mable by the local processor . • Prima ry b yte o ffset: DF:D Eh • Secondary byt e offset: DF:DEh Bit Name R/W Description 2:0 PM V ersion R /(W ...

  • Intel 21555 - page 187

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 187 List of Registers T able 120. Power Management Control and S t atus Register Bits [14:13] are loadable by serial ROM or are programmable by the local processor . • Primary byte offset: E1:E0h • Secondary byte offset: E1:E0h Bit Name R/W Descripti on 1:0 PWR S t at e R/W Power S tate. R ...

  • Intel 21555 - page 188

    188 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers T able 1 22. Pow er Mana gement Data Register • Primary byt e offset: E3h • Secondary byt e offset: E3h Bit Name R/W Descri ption 7:0 PM Data R P ower Managem ent Data register . Reflect s one of eight bytes loaded by serial ROM, or reads as 0. Bytes a re selected by th ...

  • Intel 21555 - page 189

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 189 List of Registers T abl e 124. CompactPCI Hot - Swap C ap ability Iden tifier and Next Pointer Re gister Bit Name R/W Description 7:0 H S ECP ID R Enhanc ed capabilities ID. Reads only as 06h to indi cate that these are CompactPCI Hot - Swap registers. 7:0 HS NX T PTR R Pointer to next set ...

  • Intel 21555 - page 190

    190 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers 16.14 JT AG Registers This chapter presents the theory of operation information about the 21 555 JT AG registers. See Chapt er 1 3 for theory of operation informatio n. 5:4 Reserved R Returns 0 when read. 6R E M S T A T R/ W1 TC Signal p_enum_l Removal S tatus. The 21555 se ...

  • Intel 21555 - page 191

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 191 List of Registers T able 129. Boundary Scan Ord er TBD ta ble lists the boundary- scan regist er order and the group di sable control s. The group disable con trol either enables or tristates i ts correspondi ng group of bi-dir ectional dri vers. When the val ue of a gro up disable con tro ...

  • Intel 21555 - page 192

    192 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual List of Registers The grou p disable n umb er column in TBD shows w hic h group dis able bi t co ntro ls the c orr espo ndin g out put dr ive r . Group disable bits do not af fect in put-only p ins, so those p ins have a bl ank rather t han a group number in t hat column. The group disab le ...

  • Intel 21555 - page 193

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 193 List of Registers T able 131. Vi tal Pr oduct Data (VPD) Address Register • Primary byte offset: E7:E6h • Secondary byte offset: E7:E6h Bit Name R/W Description 8:0 VPD Add r R/W Vit al Product Data Address. Contains the VPD byte address of the serial ROM location to be accessed. V ali ...

  • Intel 21555 - page 194

    ...

  • Intel 21555 - page 195

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 205 Acronyms A • 1D – One-dimensiona l • 2D – T wo- dim ens i onal • AGP – Accelerated Graphics Port • ANS I – American National Standards Institute • API – Application Prog ramming Interface • BAR – Bas e Addre ss Regi ster • BiST – Built-In S e lf-T est • CLS ? ...

  • Intel 21555 - page 196

    206 21555 Non-Tr ansparent PCI-to -PCI Bridge User Manual Acronyms • MF As – Message Frame Addresses • MPEG – Moving Pictures Exp erts Group • MV – Motion vector • MVC – Part C ontrol Number • MWI – Memory W rite and Invalidate • OBMC – Overlapped block motion compensatio n • OS – Operating system • PPB – PCI -to- PC ...

  • Intel 21555 - page 197

    21555 No n-Transparent PC I-to-PCI Bridg e User Ma nual 197 Index 3-V 1 5 5-V 1 5 Primary loc k ou t bit on the PROM_AD 82 A Add-i n c ard ve ndor s 15 address 33 Addre ss range l ocat ions Primary B AR s 33 Second a ry BAR s 33 Addre ss spac e 34 64-bit 35 expa nsion ROM d ecoding 34 type of 13 0, 132 type of f or se conda ry 131 Addre ss tra nsla ...

  • Intel 21555 - page 198

    198 21555 Non-Tra nsparent PCI-to-PCI Bridge U ser Manual Prima ry Lock out b it action befo re cl eari ng the 130 powe r mana gement 71 with serial Prelo ad 69 with SROM o peration 69, 70 Primary lo ckout bit type 0 access 44 Processor domains 15 processor 15 Q Queue em pt y condit ion 50 R Read and wri te acc ess Y, N, Primary, Secon dary, Specia ...

Manufacturer Intel Category Network Router

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A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Intel 21555 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Intel 21555.

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