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Bedienungsanleitung LSI LSI53C875A

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  • LSI LSI53C875A - page 1

    ® S14047 LSI53C875A PCI to U ltra SCSI Controller TECHNIC AL MANU AL Dece mber 200 0 Ve r s i o n 2 . 0 ...

  • LSI LSI53C875A - page 2

    ii This doc ument co ntains prop rietary inf ormation o f LSI Logic Corpor ation. The inf ormation c ontain ed herei n is not to b e used b y or di sclo sed to third par ties withou t the e xpre ss written pe r miss ion of a n officer of L SI Log ic Corporatio n. LSI Log ic produc ts are no t intended f or use i n lif e-su ppor t appli ances , de v ...

  • LSI LSI53C875A - page 3

    Pref ace iii Preface This book is th e pri mar y re f er ence an d technical manual for the LSI53C 875A PCI to Ultra SCSI Co ntrolle r . It co ntains a com plete functiona l desc rip tion f or th e prod uct and als o incl udes comp lete physical and elec tric al specifi catio ns. A udie nce This m anual provides reference infor mation o n the LSI53 ...

  • LSI LSI53C875A - page 4

    iv Preface • Chap ter 6, Electr ical Sp ecifi cation s contains t he e lectr ica l character is tics and A C timin g diagrams. • Appen dix A, Regi ster Summ ary i s a r egiste r su mmar y . • Appen dix B , External Memory Interface Dia gram Examples con tains se veral e xample i nterface dra wings f or conn ecting the LSI 53C875A to e xter na ...

  • LSI LSI53C875A - page 5

    Pref ace v PCI Spe cial Interest Gr oup 2575 N.E . Kather ine Hillsbo ro , OR 97214 (800) 433- 5177; (5 03) 693-623 2 (Inter nati onal); F AX (503) 69 3-8344 Con ventions Used in This Manual The word asser t m eans t o dri v e a sig nal tr ue or active . Th e word deass er t mea ns to dr ive a signa l f alse or inac tive . He xadec imal nu mbers ar ...

  • LSI LSI53C875A - page 6

    vi Preface ...

  • LSI LSI53C875A - page 7

    Contents vii Contents Chapter 1 General Description 1.1 New F e atures i n the LSI53 C875A 1-3 1.2 Benefits of Ultra S CSI 1-3 1.3 T olerANT ® Te c h n o l o g y 1 - 4 1.4 LSI53C 875A Bene fits S ummar y 1-4 1.4.1 SCSI P erf or m ance 1-5 1.4.2 PCI P erfor mance 1-6 1.4.3 Inte gra tion 1-6 1.4. 4 Eas e of Use 1-6 1.4.5 F le xibili ty 1-7 1.4.6 Rel ...

  • LSI LSI53C875A - page 8

    viii Cont ents 2.2.11 P ar ity Optio ns 2-24 2.2.12 DMA FIFO 2-27 2.2.13 SCSI B us Int erf ace 2-3 2 2.2.14 Select/R esele ct Dur ing S elect ion/Resel ection 2-33 2.2.15 Synchr onous Opera tion 2-34 2.2.16 Interr upt Ha ndling 2-37 2.2.17 Chained B lock Mov es 2-44 2.3 P ara llel ROM Interface 2-48 2.4 Ser ial E EPROM Interface 2-50 2.4.1 Def ault ...

  • LSI LSI53C875A - page 9

    Contents ix Chapter 4 Registers 4.1 PC I Confi gur atio n Regis ter s 4-1 4. 2 SC SI Regis ters 4-18 4.3 64-Bit SCRIP TS Selec tors 4-99 4.4 Phase Mi smatch Jump Regist ers 4-10 3 Chapter 5 SCSI SCRIPTS Instruction Set 5.1 Low Lev el Reg ister In terface Mode 5-1 5.2 High Lev el SCS I SCRIP TS Mode 5-2 5.2.1 Sample O peration 5-3 5. 3 Bl o ck M ove ...

  • LSI LSI53C875A - page 10

    xC o n t e n t s 6.3 A C Character istic s 6-9 6.4 PCI and Exter nal Mem or y Interface Timing Diagrams 6 -11 6.4.1 T arget Timing 6-13 6. 4.2 In iti ato r Timi ng 6-19 6.4.3 Exter n al Memor y T iming 6-35 6.5 SCSI Timi ng Diagrams 6-5 2 6.6 P ackage Di agr ams 6-58 Appendix A Register Summary Appendix B External M emory Inter face Dia gram E xamp ...

  • LSI LSI53C875A - page 11

    Contents xi 6. 9 PCI Co nfig ura tio n Regis ter Re ad 6- 13 6.10 PCI Con figuration Re giste r Wri te 6-14 6.11 32-Bit Op erating R egister /SCRIPTS RAM Rea d 6-15 6.12 64-Bit A ddre ss Operatin g Re gister/S CRIPTS R AM Read 6-16 6.13 32-Bit Op erating R egister /SCRIPTS RAM W rite 6-17 6.14 64-Bit A ddre ss Opera ting Re gister/S CRIPTS R AM Wri ...

  • LSI LSI53C875A - page 12

    xii Co ntent s B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 M byte Interface with 150 ns Mem or y B-3 B.4 512 Kbyte Inter f ace with 15 0 ns Memo r y B-4 Ta b l e s 2.1 PCI Bus C ommand s and E ncoding T ypes for the LSI53C 875A 2-4 2.2 PCI Cac he Mod e Alignm ent 2-12 2.3 Bits Us ed f or P a rity Con trol and Generation 2-25 2.4 SCSI Parity Co ntr ...

  • LSI LSI53C875A - page 13

    Contents xiii 5. 2 SCSI I nf or mat ion T r ansf er Phase 5- 12 5.3 Rea d/Wr ite Instr uctions 5-24 5.4 T ransfer Control In stru ctions 5-26 5. 5 SCSI P hase Co mpa risons 5-29 6.1 Abs olu te Maxim um Stress Rat ings 6-2 6.2 Operat ing Condit ions 6-2 6.3 Inp ut Capacit ance 6-2 6.4 Bidi rectional Signals —MAD[7: 0], MAS/[1: 0], MCE/ , MOE /, MW ...

  • LSI LSI53C875A - page 14

    xiv Co ntent s 6.30 Exter n al Memor y Wr ite 6-38 6.31 Nor mal/F as t Memo r y ( ≥ 1 28 Kbytes) Sing le Byte Access R ead Cycle 6-42 6.32 Nor mal/F as t Memo r y ( ≥ 1 28 Kbytes) Sing le Byte Acce ss Write Cycle 6-43 6.33 Slow Memo r y ( ≤ 128 K b ytes) Rea d Cycle 6-48 6.34 Slow Memo r y ( ≤ 128 K b ytes ) Wr ite C ycle 6-4 9 6.35 ≤ = 6 ...

  • LSI LSI53C875A - page 15

    LSI53C8 75A PCI to Ultra SCSI Controll er 1-1 Chapter 1 General D escri ption Chapter 1 is di vided in to the following secti ons: • Secti on 1.1, “New F eatures in the LSI 53C875A” • Section 1.2, “ Benefi ts of Ultra S CSI” • Secti on 1.3, “T o lerANT ® T ec hnolo g y ” • Secti on 1.4, “L SI53C875A Be nefits Su mmar y” The ...

  • LSI LSI53C875A - page 16

    1-2 Gen eral De scription Figure 1.1 T ypical LSI53C875A Sys tem Application Figure 1 .2 T ypical LSI53C8 75A B oard Appl ication PCI Bus Interf ace Controller LSI53C875A P C It oW i d eU l t r a SCSI Controller PCI Graphic Accelerator PCI F a st Ethernet Memory Controller Memo ry Fixed Disk, Optical D isk Printer , T ape, and Ot her P er ipherals ...

  • LSI LSI53C875A - page 17

    Ne w F eatu res in the LSI 53C875A 1-3 1.1 Ne w Features in the LSI53 C875A The LSI53C87 5A is a dro p-in replac ement f or the LSI53C875 PCI to Ultra SCSI C ontrolle r , with these addi tional be nefits: • Suppo r ts 32- bit PCI Int erf ace with 64-bi t addres sing . • Hand les SC SI phas e m isma tches in SC RIPTS w ithou t inter rupti ng the ...

  • LSI LSI53C875A - page 18

    1-4 Gen eral De scription synchr onous ne gotiation s f or Ultra SCSI rates and to enable the c loc k quadr upler . Chapte r 2, “F unctiona l De scri ption,” contains m ore inf or m ation on U ltra SCSI desi gn. 1.3 T olerANT ® T echn olo g y The LSI5 3C875 A f eatu res T oler ANT tec hnolo g y , whi ch incl udes ac tive negati on on th e SCSI ...

  • LSI LSI53C875A - page 19

    LSI53C8 75A Bene fits Summary 1-5 • Ease of Use • Fle xibilit y • Relia bility • T estabi lity 1.4. 1 SCSI P erf ormance T o improve SCSI perfor mance, the LSI53C8 75A: • Has integrated SE transc eivers. • Bursts up to 512 bytes ac ross th e PCI bus through i ts 944 byte FIFO. • P erforms wide, Ultra SCS I synchro nous transfers as f ...

  • LSI LSI53C875A - page 20

    1-6 Gen eral De scription • Suppo r ts a dditional ar ithme tic ca pability with the Exp anded Reg ister Mo v e instructi on. 1.4.2 PCI P erf ormance T o improve PCI perform ance, the LSI53 C875A: • Compli es with P CI 2.2 spec ific ation. • Suppo r ts 32- bit 33 MHz PCI in terface with 64-bit address ing. • Suppo r ts dual addr ess cycles ...

  • LSI LSI53C875A - page 21

    LSI53C8 75A Bene fits Summary 1-7 • Up to on e megabyte of add -in memo r y suppor t for BIOS and SCR IPTS storag e. • Redu ced SC SI de v elop ment e ff or t. • Comp iler- compa tible with existin g LSI53 C7X X and L SI53C8X X f amily SC RIPT S. • Direct c onnecti on to PC I and SC SI SE. • De v elop ment too ls and s ample SCS I SCRIPT ...

  • LSI LSI53C875A - page 22

    1-8 Gen eral De scription • SCSI clock quad rupl er bits enable Ultra SCSI transfer r ates with a 20 or 40 MHz SCSI cl oc k input. • Selec table IRQ pin disable bit. • Abil ity to route sy stem cl ock to SCSI clock. • Compatible with 3.3 V and 5 V PCI. 1.4. 6 Reliability Enhan ced reli ability f eature s of the LS I53C875 A inclu de: • 2 ...

  • LSI LSI53C875A - page 23

    LSI53C8 75A PCI to Ultra SCSI Controll er 2-1 Chapter 2 Funct ional Desc ription Chapter 2 is di vided in to the following secti ons: • Secti on 2.1, “P CI Func tional Descr iption ” • Secti on 2.2, “SCSI Functiona l Desc rip tion” • Sec tion 2. 3, “P ar alle l RO M Int erf ace” • Secti on 2.4, “Ser ial EE PROM Interface” ? ...

  • LSI LSI53C875A - page 24

    2-2 Funct ion al De scr ipt ion Figure 2.1 LSI53C875A Bl oc k Dia gram 2.1 PCI Functional D escription The LS I53C 875 A impl ement s a PCI-to -Wid e Ult ra SCSI co ntr olle r . 2.1. 1 PCI Addres sing There a re three physical PCI- define d addres s space s: • PCI Con figuration s pace. • I/O spac e f or operati ng registe rs. • Memor y space ...

  • LSI LSI53C875A - page 25

    PCI Functio nal Description 2-3 2.1.1.1 Configuration Space The host proces sor uses the PCI config uration sp ace to initialize the LSI53C 875A through a defi ned set of configu r atio n space regi sters. The Config uration reg isters ar e acces sible only by sys tem BIOS duri ng PCI confi guration c ycles. The configura tion s pace is a contigu o ...

  • LSI LSI53C875A - page 26

    2-4 Funct ion al De scr ipt ion 2.1.2.1 Interrupt Ac knowledge Command The LSI5 3C875A does not r espond t o this command a s a slav e and it ne v er gen erates this comm and as a master . 2.1.2.2 Special C yc le Comma nd The LSI5 3C875A does not r espond t o this command a s a slav e and it ne v er gen erates this comm and as a master . T able 2.1 ...

  • LSI LSI53C875A - page 27

    PCI Functio nal Description 2-5 2.1.2.3 I/O Read Command The I/O Read co mmand re ads data fr om an agen t mappe d in I/O address s pace. All 32 addre ss bits are dec oded. 2.1.2.4 I/O Write Comma nd The I/O Wr ite comm and wr ites dat a to an agent ma pped in I/O addr ess spac e. All 32 a ddress bits a re decod ed. 2.1.2.5 Reser ved Command The LS ...

  • LSI LSI53C875A - page 28

    2-6 Funct ion al De scr ipt ion 2.1.2.10 Memor y Read Mult iple Command This c ommand is ide ntica l to the Me mor y Re ad comman d e xcept that i t additi onally ind icates that the mas ter ma y intend to f etch more than one cach e lin e before disc onnect ing. The LSI5 3C875A suppo r ts PCI M emor y Read Mu ltiple fun ction ality and is sues M e ...

  • LSI LSI53C875A - page 29

    PCI Functio nal Description 2-7 line. This com mand i s intende d for use wit h bulk sequentia l data tran sf ers where the me mor y s ystem and th e request ing master might g ain some performa nce ad v antage by read ing to a ca che line b oundar y rather tha n a single memo r y cycle. The Read Line functi on in the LSI53C 875A takes advantage of ...

  • LSI LSI53C875A - page 30

    2-8 Funct ion al De scr ipt ion 2.1.2.13 Memor y Write and In validate Command The Memo r y Wr ite a nd Inv alidate c omman d is iden tical to t he Memo r y Write co mma nd, e xcept t hat it add iti onall y guar an tees a mi nim u m transfer of one c omplete ca che line; that is to say , the maste r intends to writ e all bytes w ithin t he addres s ...

  • LSI LSI53C875A - page 31

    PCI Functio nal Description 2-9 After each data transfer , the chip re-ev alu ates the burst size based on the amount of rem aining dat a to transf er and again selec ts the highe st possible multipl e of the cac he line si ze , and n o larger tha n the DM A Mode (DMO DE) burst si ze . The mo st likely sce nar io of thi s schem e is that the chip s ...

  • LSI LSI53C875A - page 32

    2-10 Func tional Desc ription software e nabled or d isabled to allow the us er fu ll flexibility in usin g these comm ands. 2.1.3.1 Enabling Cache Mo de In orde r to enable the cache l ogic to i ssue PCI cache comm ands (Memor y Read Li ne, Memor y Read Mu ltiple, and Me mor y W rit e and Inv al idate) o n any given PCI master ope ration the follo ...

  • LSI LSI53C875A - page 33

    PCI Functio nal Description 2-11 • T o issue Memor y Read M ultiple c omman ds , the R ead Mul tiple enable bit i n the DMA M ode (DMODE) regi ster mu st be set. • T o issu e Memor y Wr ite a nd In validate comm ands, both the Wr ite and Inv al idate en ab les i n the Chip T est Three (CTEST3) regis ter and the PCI configurat ion command re gis ...

  • LSI LSI53C875A - page 34

    2-12 Func tional Desc ription • Multiple Me mor y Wr ite and Inv alidate s. • A singl e data res idual Me mor y W rit e to co mplete t he transf er . Ta b l e 2 . 2 descr ibes P CI cache m ode align ment. T able 2.2 PCI Cache Mode Alignment Host Memor y A0 0 h B0 4 h 08h C0 C h D1 0 h 14h 18h 1Ch E2 0 h 24h 28h 2Ch F3 0 h 34h 38h 3Ch G4 0 h 44h ...

  • LSI LSI53C875A - page 35

    PCI Functio nal Description 2-13 2. 1.3. 5 Exa mpl es: MR = M emor y Rea d, MRL = Me mor y R ead Line, MRM = M emor y Read Multiple, MW = Mem or y Wr ite, MWI = Memor y W rite and Inv alidate. Re ad Exam ple 1 – B u r s t=4D w o r d s ,C a c h e L i n eS i z e=4D w o r d s : Re ad Exam ple 2 – B u r s t=8D w o r d s ,C a c h e L i n eS i z e=4D ...

  • LSI LSI53C875A - page 36

    2-14 Func tional Desc ription Re ad Exam ple 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords: Write E xample 1 – B u r s t=4D w o r d s ,C a c h e L i n eS i z e=4D w o r d s : Ct oE : MRM (21 byte s) Dt oF : MRM (31 bytes ) MR (1 byte ) At oH : MRM (31 byte s) MRM (32 byte s) MRM (18 byte s) At oG : MRM (31 byte s) MRM (32 byte s) MR (3 byte ...

  • LSI LSI53C875A - page 37

    PCI Functio nal Description 2-15 Write E xample 2 – B u r s t=8D w o r d s ,C a c h e L i n eS i z e=4D w o r d s : Dt oF : MW (1 5 bytes) MWI (16 byt es) MW (1 byte) At oH : MW ( 15 bytes ) MWI (16 byt es) MWI (16 byt es) MWI (16 byt es) MWI (16 byt es) MW (2 bytes) At oG : MW (1 5 bytes ) MWI (16 byt es) MWI (16 byt es) MWI (16 byt es) MW (3 by ...

  • LSI LSI53C875A - page 38

    2-16 Func tional Desc ription Write E xample 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords: 2.1.3.6 Memor y-to-Me mory M o ves Memor y -to-Me mor y Mov es a lso sup por t P CI cache commands, as descr ibed a bov e, wit h one li mitation . Memor y Wr ite and Inv a lidate on Memor y -to-Me mor y Mov e wr it es are on ly suppor ted if the sou rc ...

  • LSI LSI53C875A - page 39

    SCSI Functio nal Description 2-17 acce ssed as a regi ster- orie nted device . Er ror recov er y a nd/or diag nostic procedu res use the abili ty to sam ple and/or ass er t any signal on the SCSI bus. In supp or t o f SCSI lo opback diagn ostics, the SCS I core may perform a self-sel ection an d operate as both an initiator and a tar get. The LS I5 ...

  • LSI LSI53C875A - page 40

    2-18 Func tional Desc ription The Pha se Mi smatch Jump l ogic powers up disabled a nd must be enabled by setting the Pha se Mism atch Jump Enable bit (ENP MJ , bit 7 in the Chip Con trol 0 (CCNTL0) register). Utilizin g the infor mation supplied i n the P h a s eM i s m a t c hJ u m pA d d r e s s 1( P M J A D 1 ) and P hase M ismatc h Jump Addre ...

  • LSI LSI53C875A - page 41

    SCSI Functio nal Description 2-19 2.2.3 64- Bit Addre ssing i n SCRIPT S The LSI5 3C875A has a 32- bit PCI in terface which provide s 64-bi t address capa bility in th e init iator mod e. D ACs can be generated for all SCRIP TS operation s. There are s ix sele ctor regis ters wh ich hold the upper Dword of a 64-b it address. All but one of th ese i ...

  • LSI LSI53C875A - page 42

    2-20 Func tional Desc ription 2.2.5 Des igning an Ultra SCSI Syst em Since U ltra SCSI is ba sed on existing SCSI stan dards, it can use e xi sting dri v er pro grams as lon g as the s oftware is able to n egotiat e f or Ult r a SCS I synchr onous transfer rates. Additio nal software m odifica tions are needed to take adv antag e of the new f e atu ...

  • LSI LSI53C875A - page 43

    SCSI Functio nal Description 2-21 S t e p3 . H a l tt h eS C S Ic l o c k b ys e t t i n gt h eH a l tS C S IC l o c kb i t ( SCSI T est Three (STEST3) ,b i t5 ) . Step 4. Se t the clock c onv ers ion f a ctor using the SCF and CC F fiel ds in the SCSI Co ntrol Three ( SCNTL3) register . Step 5. Set the SCL K Quadr upler Selec t bit ( SC SI T es t ...

  • LSI LSI53C875A - page 44

    2-22 Func tional Desc ription • On ev e r y Store instr ucti on. The S tore ins tr uction m a y also be use d to place modifi ed code di rectly into m emor y . T o av oi d inad v e r t ently flushin g the pr ef etch unit conten ts use the No Flus h optio n f or all Store operati ons that do not modify code within the next 8 Dwords. • On ev er y ...

  • LSI LSI53C875A - page 45

    SCSI Functio nal Description 2-23 Load an d Store i nstruc tions, refer to Chapter 5, “SCSI S CRIPTS Instr uction S et.” 2.2.9 J T A G Boundary Scan T esting The LSI5 3C875A include s suppor t for JT A G bo undar y sc an test ing in acco rdance wi th the IEEE 1 149.1 sp ecifica tion with on e e xcept ion, whic h is e xpla ined in this secti on. ...

  • LSI LSI53C875A - page 46

    2-24 Func tional Desc ription 2.2.11 P arity Opt ions The LSI5 3C875A impleme nts a fl e xible par ity sche me that a llows contr ol of the pari ty sense, allows parity che c king to be tur ned on or o ff , an d has the ability to deliberately sen d a b yte wi th bad par ity ov er the SCSI bus to test par ity error recov er y p roce dures. Ta b l e ...

  • LSI LSI53C875A - page 47

    SCSI Functio nal Description 2-25 T able 2.3 Bits Used f or Parity Control and Gen eration Bit Name Locatio n Description Asser t SA TN/ on P ar ity Errors SCSI Control Zer o (SCNTL0) ,B i t1 C au ses th e LS I53C 875 A to aut omat ical ly as ser t S A TN / when it detects a SCSI parity error while ope ratin g as an initia tor . Enab le Pa rity Che ...

  • LSI LSI53C875A - page 48

    2-26 Func tional Desc ription T ab le 2.4 SCSI P a rity Contr ol EPC 1 1. EPC = Ena ble P ar ity Ch ecking (bi t 3 SCSI C ontrol Zero (SCNTL0) ). ASEP 2 2. ASEP = Assert SCSI Even P arity (bit 2 SCSI C ontr ol O ne (S CNT L1) ). Descrip tion 0 0 Does n ot che ck f or parity errors . P arity is g ener ated when sending SCSI data . Asser ts od d pari ...

  • LSI LSI53C875A - page 49

    SCSI Functio nal Description 2-27 Figure 2.2 P arity Checki ng/Generation 2.2. 12 DMA F IFO The DMA FIF O is 8 bytes wid e by 118 transfers deep. The DMA FIFO is illu strated i n Fi gure 2.3 . Th e def aul t DMA FI FO size is 11 2 bytes to assu re compa tibil ity wi th olde r produ cts in the LSI53 C8XX family . The DMA FIFO size ma y b e set to 94 ...

  • LSI LSI53C875A - page 50

    2-28 Func tional Desc ription Figure 2.3 DMA F IFO S ections The LSI5 3C875A aut omatical ly suppo r ts misa ligned DMA tran sf ers. A 944-byte FIFO all ows the LSI53C 875A to s uppor t 2, 4, 8, 16, 32, 6 4, or 128 Dword bursts across t he PCI bus interf ace. 2.2.12.1 Data Paths The data pa th through the L SI53C8 75A is depe ndent on whethe r data ...

  • LSI LSI53C875A - page 51

    SCSI Functio nal Description 2-29 Figure 2.4 LSI53C87 5A Host Interface SCS I Data P at hs The following steps deter mine if any bytes remain i n the data p ath when the chip halts an operation : Asynch ro nous SCSI Send – Step 1. If the DM A FIFO s ize is set to 112 bytes (bit 5 of th e Chip T est Fiv e (CTEST5) register c leared) , look at t he ...

  • LSI LSI53C875A - page 52

    2-30 Func tional Desc ription bits of the DBC r egister fr om the 10-bi t v alue of the DMA F IFO Byte Offset Cou nter , whi ch consists of bi ts [1:0] in the CTEST 5 registe r and bi ts [7:0] of th e DMA FI FO reg ister . A ND the res ult with 0x 3FF for a b yte c ount bet ween zero and 94 4. Ste p 2. Re ad b it 5 i n th e SC SI Stat us Zer o (SST ...

  • LSI LSI53C875A - page 53

    SCSI Functio nal Description 2-31 then the lea st significa nt b yte or the mos t significan t byte in the SODR register i s full, res pectively . Asynchr onous SCSI Receive – Step 1. If the DM A FIFO s ize is set to 112 bytes (bit 5 of th e Chip T est Fiv e (CTEST5) register c leared) , look at t he DMA FIFO (DFIFO) and DMA Byte C ounter ( DBC) ...

  • LSI LSI53C875A - page 54

    2-32 Func tional Desc ription AND the r esult with 0x 3FF f or a byte count be tween zero and 944. Ste p 2. Re ad th e SCSI Status One (S ST A T1) regist er and examine bits [7:4], th e binar y r eprese ntation of the number of valid b y tes in the SCSI FIFO , to deter m ine if any b yte s are left in the SCSI FIFO . Ste p 3. If an y wide tr an sf ...

  • LSI LSI53C875A - page 55

    SCSI Functio nal Description 2-33 Figure 2.5 Regulated T e rmination f or Ultra SCSI 2.2. 14 Select /Resele ct During Sel ection/Re selec tion In multit hreaded S CSI I/O environm ents, it is no t unco mmon to be sele cted or resel ected while tr ying to perfor m selecti on/res electio n. This TERM L1 TERM L2 TERM L3 TERM L4 TERM L5 TERM L6 TERM L7 ...

  • LSI LSI53C875A - page 56

    2-34 Func tional Desc ription situa tion may occur whe n a SCS I control ler (op erating in the initia tor mode ) tries to sele ct a tar get and is r esele cted b y anothe r . The Sele ct SCRIPT S ins truc tion ha s an alt er nate ad dress to w hich the SCR IPTS w ill jump w hen thi s situati on occur s. The anal ogous si tuatio n for target de vic ...

  • LSI LSI53C875A - page 57

    SCSI Functio nal Description 2-35 Figure 2.6 Determining the Sync hron ous T ransfer Rate SCLK Clock Quadrup ler QCLK SCF Di vi der CCF Divider Synchronous Divider Asynchronous SCSI Logic Divide b y 4 SCF2 SCF1 SCF0 SCF Divisor 00 1 1 01 0 1 . 5 01 1 2 10 0 3 00 0 3 10 1 4 11 0 6 11 1 8 TP2 TP1 TP0 X FER P Divisor 00 0 4 00 1 5 01 0 6 01 1 7 10 0 8 ...

  • LSI LSI53C875A - page 58

    2-36 Func tional Desc ription 2.2.15.2 SCSI Control Thr ee (SCNTL3) Regi ster , Bits [6: 4] (SCF[2 :0]) The SCF[2: 0] bits s elect the factor by which the freque ncy of S CLK is divided before being p resented to the sy nchronou s SCSI c ontrol logi c. The outpu t from this d ivider control s the rate a t which dat a can be rece iv ed; thi s rate m ...

  • LSI LSI53C875A - page 59

    SCSI Functio nal Description 2-37 • Ultra SCSI Enab l e bit, SCSI Control Thr ee (SCNTL 3) register bit 7. Settin g this bit enables Ultra SCSI sync hronous transfers in systems that u se the in ternal SCSI cl oc k quadrupl er . • T oler ANT Enable bit , SCSI T est Thre e (STEST 3) r egist er bit 7. A ctive negation must b e enabled for the LSI ...

  • LSI LSI53C875A - page 60

    2-38 Func tional Desc ription polle d when polled int errupts ar e used. It is also the first regi ster that shoul d be read after the I RQ/ pi n is ass er te d in ass ociation with a hardware in terrupt. The IN TF (In terr upt-on-the- Fly) bi t should b e the firs t interr upt ser viced. It must be wr itten to one t o be cle ared. This inte rru pt ...

  • LSI LSI53C875A - page 61

    SCSI Functio nal Description 2-39 condi tions ca used the DMA -typ e interr upt, and c lears t hat DMA inte rru pt condi tion. Bi t 7 in D ST A T , DFE , is pure ly a s tatus bit ; it wi ll not generate an interr upt under any circum stances a nd will not be clear ed when rea d. DMA inter rupt s flush nei ther the DM A nor SCSI FIFOs before generat ...

  • LSI LSI53C875A - page 62

    2-40 Func tional Desc ription Pur po se Time r Expire d (GEN), an d Handsha k e- to-Handsh ake Timer Expir ed (HTH) inter rup ts are no nf atal. When o perating in the T ar get mode, CMP , SEL, RSL, T arget mode: SA TN/ act ive (M/A) , GEN, and HTH ar e nonf atal. Refer to the descr iption f or the Disa bl e Halt on a P arity Er ror or SA TN/ acti ...

  • LSI LSI53C875A - page 63

    SCSI Functio nal Description 2-41 Interr upts c an be disa b led by setting SYNC_IR QD bit 0 in the Inte rru pt Status O ne (IST A T1) r egister . If an i nterr upt is a lready as ser ted and SYNC_I RQD is then set, the in terrupt wi ll remain as ser ted until ser viced. At thi s point, th e IRQ/ pin is block ed for future in terrupt s unti l this ...

  • LSI LSI53C875A - page 64

    2-42 Func tional Desc ription generates a n interr upt, th e bit c orrespond ing to the ear lier m asked nonf atal inter rupt is st ill set. A relate d situation t o interr up t stacking is wh en two interr upts oc cur simulta neously . Sinc e stacking do es not oc cur unti l the SIP o r DIP bits are set, there is a sma ll tim ing win dow in wh ich ...

  • LSI LSI53C875A - page 65

    SCSI Functio nal Description 2-43 • If the i nstruc tion is a JUMP/ CALL W HEN/IF <p hase>, th e DMA SCR IPTS P o inter (D SP) is upd ated to t he transfer address bef ore halting. • All othe r instruc tions may halt bef o re comp letion. 2.2.16.7 Sample I nterrup t Ser vice Rou tine The following is a s ampl e of an inte rru pt ser v ice ...

  • LSI LSI53C875A - page 66

    2-44 Func tional Desc ription 2.2. 17 Chaine d Bloc k Mo ves Since th e LSI53 C875A has the capab ility to transf er 16-bi t wide S CSI data, a unique situatio n occ urs when dealing w ith odd bytes. T he Chained Mov e (CHMO V ) SCRIPTS instr ucti on along with the Wide S CSI Send (W SS) and Wide SCSI Re ceive (WSR) bi ts in the SCSI Contr ol T wo ...

  • LSI LSI53C875A - page 67

    SCSI Functio nal Description 2-45 Figure 2.7 Block Mo ve and Chained Block Mo ve Instructions 2.2.17.1 Wide S CSI Send B it The WS S bit is set whenev er th e SCSI control ler is sen ding data (Data-O ut f or initia tor or Data- In f or ta rget) and the control ler detects a par t ial transf er at the end of a chained Block Mov e SCRIPTS in struct ...

  • LSI LSI53C875A - page 68

    2-46 Func tional Desc ription two b ytes are se nt out ac ross the bus, rega rdless of the type of Blo ck Mov e ins truc tion (nor mal or chain ed). Th e flag is automat ically cleare d when the “ma rri ed” word is sent. The flag is alter nate ly cleared through SCRIPT S or by the m icroproc esso r . Also, the micr oproces sor or SCRIPT S can u ...

  • LSI LSI53C875A - page 69

    SCSI Functio nal Description 2-47 2.2.17.5 Chained Bloc k Mo ve SCRIPTS Instruction A chai ned Block Move SCRIPTS instr uction is pr imar ily use d to t ransf er cons ecutive data send or data receive b locks. Using the chained Bl ock Mov e ins truc tion facilita tes par tial r eceive transfers and all ows correc t par t ial send beh a vio r withou ...

  • LSI LSI53C875A - page 70

    2-48 Func tional Desc ription send c ommand, th e first byte of th e data send command is ass umed t o be the high-o rder byte and is “marr ied” with th e low-order byte stored in the lower byte of the SC SI Out put Data L atch (S ODL) regi ster bef ore the two bytes are sen t across th e SCSI bus. F or “N” consecuti v e wide data send B lo ...

  • LSI LSI53C875A - page 71

    P arallel R OM Interfa ce 2-49 The LSI5 3C875A su ppor ts a v ar iety of sizes and sp eeds of expansio n R OM, using pull-d own resistors on the M AD[3:0] pins. The en coding o f pins MAD[3:1 ] allows the user to define how much e x ter nal memo r y is a vailable to the LSI53C8 75A. Ta b l e 2 . 6 sh ows the memor y s pace associate d with the poss ...

  • LSI LSI53C875A - page 72

    2-50 Func tional Desc ription 2.4 Serial EE PROM Inte rface The LS I53 C875 A impl eme nts an in ter f ace th at al low s att achme nt of a ser ial E EPROM device to t he GPIO 0 and G PIO1 pi ns. There a re two modes of opera tion rela ting to the se r ial EEP R OM a nd the S ubsyst em ID and Subs ystem V en dor ID register s . Thes e modes are pro ...

  • LSI LSI53C875A - page 73

    P ow er Man ageme nt 2-51 2.4.2 No Do wnload Mode When M AD7 is pu lled u p through an e xter n al resi stor , the auto matic download i s disabled and no data is autom aticall y loaded into chip registe rs at power-up. The Subsystem ID and S ubsyst em V endor ID registe rs are read onl y , pe r the PCI s pecific ation, w ith a default v a lue of 0 ...

  • LSI LSI53C875A - page 74

    2-52 Func tional Desc ription The LS I53 C875 A po wer s tate s sho wn in Ta b l e 2 . 8 are ind ependen tly control led through two power state bits tha t are located in the PCI Po w e r Ma nagem ent C ontr ol /St atus (P MCS R) regis ter 0x44. Altho ugh the PCI Bus P ower Manag ement Inter f a ce Spec ificatio n does not allow pow er state transi ...

  • LSI LSI53C875A - page 75

    P ow er Man ageme nt 2-53 2.5. 3 P ow er State D2 P ower state D2 is a lower power state than D1 . In this state the LSI53C 875A cor e is pla ced in the co ma mode. The following PCI Config uration Space co mmand reg ister enable bits are suppr essed: • I/O Spac e Enable • Memor y Space E nable • Bus M aster ing En able • SERR/Enable • En ...

  • LSI LSI53C875A - page 76

    2-54 Func tional Desc ription ...

  • LSI LSI53C875A - page 77

    LSI53C8 75A PCI to Ultra SCSI Controll er 3-1 Chapter 3 Signal D escript ions This c hapter pres ents the LSI 53C875A pi n configu ration an d signal defini tions usin g tables and illu strations. This c hapter co ntains the f ollowin g sec tions: • Secti on 3.1, “LSI53C8 75A Func tional S ignal Grouping” • Sec tion 3 .2, “ Sign al De scr ...

  • LSI LSI53C875A - page 78

    3-2 Signa l Descripti ons 3.1 LSI53C875A Functional Signal Grouping Figure 3.1 present s the LSI53C87 5A si gnals by func tional group . Figure 3.1 LSI53C875A Functional S ignal Gr ouping LSI53C875A CLK RST/ AD[31:0] C_BE[3:0 ]/ PA R FRAM E/ TRD Y/ IRD Y/ ST OP/ DEVS EL/ IDS EL REQ/ GNT/ PERR/ SERR/ IRQ/ GPIO0 _FETCH/ GPIO 1_MASTER / GPIO2 GPIO3 GP ...

  • LSI LSI53C875A - page 79

    Signa l Descripti ons 3-3 3.2 Signal Descriptions The Sig nal Descr ipti ons are d ivided i nto P CI Bus Interface Signal s , SCSI Bus Inte rf ace Si gnals , GPIO Sign als, ROM Fla sh an d Memo r y Int erf ace Signa ls , T est In terface Sign als ,a n d Po wer and Gr ound Sig nals . The PCI B us Int erf ace Signals are sub divi ded into Sy stem Si ...

  • LSI LSI53C875A - page 80

    3-4 Signa l Descripti ons 3.3 PCI Bus Interface Signal s The PCI Bus Int erf ace Signa ls sect ion conta ins tables descr ibin g the sign als for the f o llowing sig nal groups : Syst em Signals , Addres s and Data Signa ls , Inter f a ce Con trol Signal s , Arbi tration Signa ls , Error Repor ting S ignals , and Inte rru pt Signal . 3.3. 1 System ...

  • LSI LSI53C875A - page 81

    PCI Bus In terf ace Sig nals 3-5 3.3. 2 Address and Data Signals Ta b l e 3 . 3 descr ibes Addr ess and Data si gnals. T able 3.3 Address and Data Signals Name PQF P B GA T ype Strength Desc ription AD[31:0] 150, 151, 153, 15 4, 156, 15 7, 1 5 9 ,1 6 0 ,3 , 5, 6, 7, 9, 11–13, 28– 30, 32, 34– 36, 38, 40, 41, 43, 44, 46, 47, 49, 50 B5, C5, A4, ...

  • LSI LSI53C875A - page 82

    3-6 Signa l Descripti ons 3.3.3 I nterface Control Signals Ta b l e 3 . 4 descr ibes th e In terf ace Control s ignals. T able 3.4 Interface Contr ol Signals Name PQFP BG A T ype Str ength Descr iption FRAME/ 16 F2 S/T/S 8 mA PCI Cycle Frame is driv en by t he curr ent maste r to indi cate th e begin ning a nd durat ion o f an acces s. FRAME / is a ...

  • LSI LSI53C875A - page 83

    PCI Bus In terf ace Sig nals 3-7 3.3.4 Arbitration Signals Ta b l e 3 . 5 de scribe s Arbit rat ion si gnals . 3.3.5 Error Repor ting Signals Ta b l e 3 . 6 descr ibes th e Error Re por t ing signa ls. T able 3.5 Arbit ration Signals Name PQFP BGA T ype Strength Descriptio n REQ/ 148 E6 O 8 mA PCI Request i ndicates t o the system arbiter t hat thi ...

  • LSI LSI53C875A - page 84

    3-8 Signa l Descripti ons 3.3.6 Interrupt Signal Ta b l e 3 . 7 descr ibes th e Inter rupt signa l. 3.4 SCSI Bus Interf ace Signals The SCS I Bus Interface sig nals secti on contai ns tables descr ibing th e sign als f or the f ollowing sig nal groups : SCSI Bus Inter f ace Sign als , SCSI Signa ls ,a n d SC SI Cont rol Sig nals . 3.4. 1 SCSI Bus I ...

  • LSI LSI53C875A - page 85

    SCSI Bus Interf ace Signals 3-9 3.4.2 SCSI Signals Ta b l e 3 . 9 descr ibes th e SCSI signals. 3.4.3 S CSI Contr ol Signals Ta b l e 3 . 1 0 des cr ibes t he SCSI Control s ignals. T ab le 3.9 SCSI Signa ls Name PQFP BGA T ype Stren gth Descripti on SD[15:0] 113, 115–17, 85 –87, 89, 102, 10 3, 105–108, 1 10, 111 D13, E10, C13, D11, J9, L13, ...

  • LSI LSI53C875A - page 86

    3-10 Signa l Descriptions 3.5 GPIO Si gnals Ta b l e 3 . 1 1 des cr ibes t he SCS I GPIO s ignals. T able 3.11 GPIO Signals Name PQFP BGA T ype Strength Description GPIO0_FETCH / 53 N 5 I/O 8 mA SCSI General Purpose I/O pin. Opt ionally , when d r iven LO W , indica tes t hat the n e xt bus requ est w il l be for an o pcod e fetch. T his p in is pr ...

  • LSI LSI53C875A - page 87

    ROM Fla sh a nd M emor y In terface S ig nals 3- 11 3.6 ROM Flash and Memor y Interface Signals Ta b l e 3 . 1 2 des cr ibes t he ROM Fla sh and Memor y In terface sign als. T a ble 3 .12 R OM F las h and Mem ory Int erfa ce Sig nal s Name PQFP BGA T ype Strength Descrip tion MWE/ 139 C7 O 4 mA Me mor y Wr ite En able . T h i sp i ni su s e da sa w ...

  • LSI LSI53C875A - page 88

    3-12 Signa l Descriptions 3.7 T e st In terf ace Sig nals Ta b l e 3 . 1 3 des cr ibes T e st Inte rf ace s ignal s . MAD[7:0 ] 59–6 2, 64–6 7 L7, M7, N7, K7, M8, N8, L8, K8 I/O 4 mA Memory Address/Data Bus. This b us is used in conjun ction wi th the m emory address str obe pins and e xternal address latche s to assemb le up to a 20-bit ad dre ...

  • LSI LSI53C875A - page 89

    P ow er and Ground Signals 3-13 3.8 P ow er and Ground Signals Ta b l e 3 . 1 4 des cr ibes t he P ower and Gr ound sig nals. T able 3.14 P ower and Gr ound Signals Name PQFP BGA T ype Strength Description VSS_I/O 4, 10, 14, 18, 23, 27, 31, 37, 42, 48, 69, 79, 88, 9 3, 99, 104, 1 09, 114, 123, 1 33, 152, 158 A 9 ,B 1 1 ,D 1 2 , E13, F 12, G11, J13 ...

  • LSI LSI53C875A - page 90

    3-14 Signa l Descriptions 3.9 MAD Bus Programming The MAD[7 :0] pins, in ad ditio n to ser vin g as the ad dress/d ata bus f o r the loca l memor y inter f ac e, also are used t o program power-up opti ons for the chip. A par ti cular opti on is programmed allowing the int er nal pull-down c urrent s ink to pu ll the pin LOW at reset or by connecti ...

  • LSI LSI53C875A - page 91

    MAD Bus Progr amming 3-15 • The MAD[ 0] pin i s the slow ROM pin. When pu lled up, it enables two e xtra cycles of dat a acces s time to a llow use of sl ow er m emor y de vices. • All MAD pin s hav e i nter nal pull-dow n resis tors. ...

  • LSI LSI53C875A - page 92

    3-16 Signa l Descriptions ...

  • LSI LSI53C875A - page 93

    LSI53C8 75A PCI to Ultra SCSI Controll er 4-1 Chapter 4 Regi sters This chap ter descr ib es all LSI53 C875A regis ters and is divi ded into th e f ollowin g sec tions: • Secti on 4.1 “PCI Configuration Reg isters ” • Section 4.2 “S CSI Register s” • Secti on 4.3 “64- Bit SCRIPT S Selecto rs” • Secti on 4.4 “Phase Misma tch Ju ...

  • LSI LSI53C875A - page 94

    4-2 Re gist ers bits that are cur rently suppor ted by the L SI53C875A are des cri bed i n this chapt er . Reser ved bits sho uld not be accessed . Regist er s: 0x00–0 x01 V endor ID Read Only VID V e ndor ID [15:0] This 16 -bi t regis ter id entif ie s the man uf actur er of the de vice. The V endor ID is 0x1 000. T able 4.1 PCI Configuration Re ...

  • LSI LSI53C875A - page 95

    PCI Con fi gura tio n Reg ist ers 4-3 Regist er s: 0x02–0 x03 Device ID Read Only DID Device ID [15:0] This 16 -bi t r egister id entif ie s the par ticu lar de vice . The LSI53C 875A Device ID is 0x00 13. Regist er s: 0x04–0 x05 Command Read/Write The Command regi ster provide s coar se contro l ov er a device’ s ab ility to generate and res ...

  • LSI LSI53C875A - page 96

    4-4 Re gist ers R Reser ved 5 WIE Write and In validate Enable 4 This b it allows the L SI53C875A to gene r ate w rit e and inv alidat e command s on th e PCI bus. The W IE bit i n the DMA Contr ol (DCNTL) regi ster must a lso be se t for the de vice to generate Wr ite a nd Inv alida te comman ds. R Reser ved 3 EBM E nable Bus Mastering 2 This bit ...

  • LSI LSI53C875A - page 97

    PCI Con fi gura tio n Reg ist ers 4-5 Regist er s: 0x06–0 x07 Statu s Read/Write Reads to this r egister b ehav e nor mal ly . Writes ar e slightly di ff erent in that bits can be cl eared, but not set. A bit is clear ed whenev er the register is writ ten, and the data in the cor respon ding bit loc ation is a one. F or insta nce, to clear bi t 1 ...

  • LSI LSI53C875A - page 98

    4-6 Re gist ers These b its are read onl y and sho uld indi cate th e slowest time th at a device asser ts DEVS EL/ for any b us comm and e xcept Configu ration Re ad and Co nfiguratio n Wri te. The LSI53 C875A sup por ts a value of 0b01 . DPR Da ta P arity Error Reported 8 This bit is s et when all o f the f ollowing co nditio ns are met: • The ...

  • LSI LSI53C875A - page 99

    PCI Con fi gura tio n Reg ist ers 4-7 Regist er s: 0x09–0 x0B Class Code Read Only CC Class Code [23:0] This 24-bi t registe r is used to identi fy the gen eric func tion of the d e v ice. The upper byte of this reg ister i s a base class c ode, the mid dle byte is a sub class code, and th e lower b yte iden tifies a sp ecific re gister lev el pr ...

  • LSI LSI53C875A - page 100

    4-8 Re gist ers Regist er: 0x0D Latenc y Timer Read/Write L T Latency Ti mer [7 :0] The Late ncy Ti mer reg ister spe cifie s, in units o f PCI bus clocks, the value of th e Latency Timer f o r this P CI bus maste r . The LS I53C875 A suppor ts this timer . All ei ght bits ar e wri table , allowing l atency values of 0 –255 PCI clocks. Use the f ...

  • LSI LSI53C875A - page 101

    PCI Con fi gura tio n Reg ist ers 4-9 Regist er s: 0x10–0 x13 Base Address Register Zero (I/O) Read/Write B A R0 Base Address Regist er Zero - I/O [31:0] This ba se addres s regis ter is u sed to ma p the ope r atin g reg ist er set i nto I/ O space . Th e LSI 53C8 75A r equir es 256 bytes of I/O spac e f or this base address regis ter . It has b ...

  • LSI LSI53C875A - page 102

    4-10 R egist er s Regist er s: 0x18–0 x1B Base Address Register T w o (SCRIPTS RAM) Read/Write B A R2 Base Address Regist er T wo [31:0] This b ase reg ister is us ed to map the S CRIP TS RA M into memor y space. Th e def ault v alue of th is regis ter is 0x000000 00. The LSI53 C875A poi nts to 4096 bytes of addre ss space with this reg ister . T ...

  • LSI LSI53C875A - page 103

    PCI Con fi gura tio n Reg ist ers 4- 11 contro ller instal led on them (and the ref ore the sa me V endor ID and Device ID). If the exter nal s eria l EEPROM in terf ace is enabled (MAD [7] LOW), this r egister is autom atica lly loa ded at pow er -up from the e xter n al seri al EEP R OM and w ill conta in the value download ed fro m the s eria l ...

  • LSI LSI53C875A - page 104

    4-12 R egist er s v alue that s hould b e stored in the exter nal ser ial EEPROM i s vendor s pecifi c. Pl ease s ee the Section 2.4 “Ser ial EE PROM Inter f ace” in Chapter 2 f or a dditio nal inf or m ation on downlo ading a value f or thi s registe r . Regist er s: 0x30–0 x33 Expansion RO M Base Address Read/Write ERB A Ex pansion ROM Bas ...

  • LSI LSI53C875A - page 105

    PCI Con fi gura tio n Reg ist ers 4- 13 Regist er: 0x34 Capabilities P o inter Read Only CP Capabilities P ointer [7:0] This reg ister i ndica tes that the first extend ed capabi lity registe r is locate d at offset 0x40 in the PCI Co nfiguration . Regist er s: 0x35–0 x3B Rese rved Regist er: 0x3C Interrupt Line Read/Write IL Interrupt Line [7:0] ...

  • LSI LSI53C875A - page 106

    4-14 R egist er s Regist er: 0x3D Interrupt Pin Read Only IP Interrupt Pin [7:0] This reg ister indica tes which in terr upt pin the de vice uses. Its v a lue is set to 0x01 f o r the INT A / signal. Regist er: 0x3E Min_Gnt Read Only MG MIN_GNT [7:0] This re gist er is used to sp ecify th e desir ed settin gs f or latenc y timer values. Min_Gn t is ...

  • LSI LSI53C875A - page 107

    PCI Con fi gura tio n Reg ist ers 4- 15 Regist er: 0x40 Capability ID Read Only CID Cap_ID [7:0] This regi ster indi cates th e type of data str uctur e curre ntly being used. It is set to 0x01, in dicating the P ow er Manage ment Dat a Str ucture. Regist er: 0x41 Next Item P o inter Read Only NIP Ne xt_Item_Ptr [7:0] Bits [7:0] c ontain the offs e ...

  • LSI LSI53C875A - page 108

    4-16 R egist er s D2S D2_Support 10 The LSI5 3C875A sets this bit to in dicate s uppor t f or power manage ment st ate D2. D1S D1_Support 9 The LSI5 3C875A sets this bit to in dicate s uppor t f or power manage ment st ate D1. R Reser ved [8:6] DSI De vice Specific Initialization 5 This b it is cleared to indic ate that t he LSI5 3C875A requir es n ...

  • LSI LSI53C875A - page 109

    PCI Con fi gura tio n Reg ist ers 4- 17 DSCL Data_ Scale [14:13] The LSI5 3C875A does not s uppor t the d ata regist er . Therefore, these two bits are alway s c leared. DSL T Data_Sel ect [12:9] The LSI5 3C875A does not s uppor t the d ata regist er . Therefore, these four bits are a lwa y s cleared. PEN PM E_ Enabl e 8 The LSI5 3C875A alwa ys ret ...

  • LSI LSI53C875A - page 110

    4-18 R egist er s Regist er: 0x47 Data Read Only D A T A Data [7:0] This reg ister provides an o ptional m echanism for the function to repor t state -depende nt operating data. T he LSI53C 875A do es not use this regi ster and always returns 0x00. 4.2 SCSI Register s The contr ol re gisters for the S CSI cor e are directly acces sible from the PCI ...

  • LSI LSI53C875A - page 111

    SCSI Registers 4-19 T able 4.2 SCSI Re gister A ddress Map 31 16 15 0 SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 GPREG0 SDID SXFER SCID 0x 04 SBC L SSI D SOCL SFBR 0x08 SST A T 2 SST A T1 SST A T0 DST A T 0x0C DSA 0x1 0 MBO X1 MBO X0 I ST A T1 IST A T0 0x 14 CTEST3 CTEST2 C TEST1 C TEST0 0x 18 TEMP 0x1C CTEST6 CTES T5 CTEST 4 DFIFO 0 x20 DCMD DBC 0x24 DNAD 0 ...

  • LSI LSI53C875A - page 112

    4-20 R egist er s Regist er: 0x00 SCSI Contr ol Zer o (SCNTL0) Read/Write ARB[1:0] Arbitration Mode Bits 1 and 0 [7:6] Sim ple Ar bitr ation 1. Th e LSI53C875A waits f or a bus free con dition to occu r . 2. It as ser ts SBSY / and i ts SCSI ID (contain ed in t he SCSI Chip ID (SCID) register ) onto the SCSI bus. If the S SEL/ signa l is ass er t e ...

  • LSI LSI53C875A - page 113

    SCSI Registers 4-21 Full Ar bitration , Selection/R eselect ion 1. Th e LSI53C875A waits f or a bus free con dition . 2. It as ser ts SBS Y/ and its S CSI ID ( the highes t pr iori ty ID stored i n the SCSI Chip ID (SCID ) registe r) onto the SCSI b us . 3. If the S SEL/ si gnal is asser ted by anothe r SCSI device or if th e LSI53 C875A dete cts a ...

  • LSI LSI53C875A - page 114

    4-22 R egist er s W A TN Select with SA TN/ on a Start Sequence 4 When thi s bit is set and the LS I53C875A is i n the initiato r mode, the SA TN/ s ignal is asse r ted d urin g selecti on of a SCS I targ et de vic e . This is t o inf orm the tar get th at th e LSI5 3C87 5A has a messa ge to se nd. If a select ion time-ou t occurs whi le attempti n ...

  • LSI LSI53C875A - page 115

    SCSI Registers 4-23 ( SET TARGE T or CLEAR TA RGET ). When this bit is se t, the chip is a target device by def ault. Whe n this bit is cl eared, the LS I53C8 75A is a n initiato r device by default. Caution : Wri ting this b it whil e not connec ted may cause the lo ss of a selec tion or re sele ction due to the cha nging of tar get or initi ator ...

  • LSI LSI53C875A - page 116

    4-24 R egist er s ma y transfer up to three addit ional bytes before halting to synchr onize be tween inter n al core cells. Du ring synchr onous op eration, the LSI 53C8 75A tr ansfers data until the re are no outsta nding synchr onous offs ets. If the LSI53C 875A is rec eiving data, any data r esidin g in the DMA FIFO is sent to memo r y before h ...

  • LSI LSI53C875A - page 117

    SCSI Registers 4-25 SCSI Co ntrol Zer o (SCNTL0) regis ter are s et for full arbitration a nd sele ction b ef o re setti ng this bi t. Arb itr at ion is re tried un til w on. At that p oint , the LSI53C 875A holds SB SY and SS EL ass er te d, and waits f o r a select or res elect seq uence. The Imme diate Arbitration bi t is cleared auto matic ally ...

  • LSI LSI53C875A - page 118

    4-26 R egist er s Caution : Wri ting to thi s regis ter wh ile not co nnecte d may cause th e loss of a sele ction /resele ction by clear ing the Connec ted bit. Regist er: 0x02 SCSI Contr ol T wo (SCNTL2) Read/Write SDU S CSI Disconnect Unexpected 7 This bit is valid in the i nitiator m ode only . When thi s bit is set, the SCSI core is not e x pe ...

  • LSI LSI53C875A - page 119

    SCSI Registers 4-27 combi ned with t he firs t byte from the subsequ ent transfer so that a wide transfer is complet ed. SLPMD S LP A R Mode 5 If this bit is cle ared, the SCS I Longitu dinal Parity (SLP AR ) registe r functions as a byte-wide long itudi nal pari ty registe r . If this bi t is set, the SLP AR func tions as a word-wide longit udinal ...

  • LSI LSI53C875A - page 120

    4-28 R egist er s group codes. If this bit is set , the de v ice does not rel oad the Block Move b yte cou nt, regardl ess of th e group cod e. WSR Wide SCSI R eceive 0 When re ad, this bit retu rn s the value of th e Wide SCSI Receive (WSR) flag. Set ting this bit c lears the WSR fl ag. This cle ar ing func tion is s elf-cl eari ng. The WSR fl ag ...

  • LSI LSI53C875A - page 121

    SCSI Registers 4-29 SCF[2:0] Synchr onous Cloc k Con v er sion F actor [6:4] These b its sel ect a factor by which t he fre quency of SCLK i s divi ded before being p resented to the synchr onous S CSI co ntrol log ic. W rite these to th e same v alue as t he Clock Conv er sion F actor bits bel ow unless f a st SCS I operation is desi red. See the ...

  • LSI LSI53C875A - page 122

    4-30 R egist er s Regist er: 0x04 SCSI Chip ID (SCID ) Read/Write R Reser ved 7 RRE Enable Response to Reselection 6 When t his bi t is s et, the LSI53C 875A is enabled to respond to bus-initi ated res election at the chi p ID in th e Respo nse ID Zero (R ES PID0) and Respon se ID One (RES PID1 ) registe rs. Note that th e chip do es not automa tic ...

  • LSI LSI53C875A - page 123

    SCSI Registers 4-31 Regist er: 0x05 SCSI T ransfer (SX FER ) Read/Write Note: Wh en using T ab le Ind irect I/ O comma nds, bits [7: 0] of th is registe r are loade d from the I/O da ta str ucture. TP[2:0] SCSI Synch ronous T rans fer P eriod [7:5] These b its det er mine the S CSI syn chro nous transfer peri od us ed by the LSI53C 875A when send i ...

  • LSI LSI53C875A - page 124

    4-32 R egist er s (This SCSI s ynchrono us core c loc k is deter m ined in SCNTL3 b its [6:4], E xtCC = 1 i f SCNTL1 b it 7 is as ser ted and the LSI53C 875A is sen ding da ta. ExtCC = 0 if th e LSI53C 875A is r eceiv ing data.) SXFER P = 1 00 ÷ 25 = 4 Where: Ta b l e 4 . 3 shows e xa mples of sy nchrono us transf er peri ods and rates f or SCSI- ...

  • LSI LSI53C875A - page 125

    SCSI Registers 4-33 Ta b l e 4 . 4 s hows e xampl e transf er per iod s and rates for f ast SCSI-2 a nd Ultra SCSI. MO[4:0] Max SCSI Synchr onous Offset [4:0] These bi ts des cribe the max imum SCS I synchro nous offset used by the LSI 53C8 75A when transferri ng synchr onous SC SI data in eit her the initiato r or target mode. Ta b l e 4 . 5 d esc ...

  • LSI LSI53C875A - page 126

    4-34 R egist er s T able 4.5 Maxim um Synchr onous Offset MO4 MO3 MO2 MO1 MO0 Synchrono us Offset 00000 0 - A s y n c h r o n o u s 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 1 0 01011 1 1 01100 1 2 01101 1 3 01110 1 4 01111 1 5 10000 1 6 10001 1 7 10010 1 8 10011 1 9 10100 2 0 10101 2 1 10110 2 2 10111 2 3 11000 ...

  • LSI LSI53C875A - page 127

    SCSI Registers 4-35 Regist er: 0x06 SCSI Dest ination ID (SDID) Read/Write R Reser ved [7:4] ENC Encoded Dest ination S CSI ID [3:0] Wri ting th ese bits se t the SCSI ID of the in tended i nitiator or targe t dur ing SC SI resel ectio n or sel ection ph ases, respectively . When ex ec uting SCRI PTS, the SCRIPTS proces sor wr ites the des tination ...

  • LSI LSI53C875A - page 128

    4-36 R egist er s is als o poss ible to pro gr am these sign als as l ive inputs and sense them th rough a SCRIPT S regist er to register Mo ve I nstruc tio n. GPI O4 ma y be used t o enab le or disa b le V PP , the 12 V ol t power supply to the ex ter nal flash memor y . This bit powers up with the po wer to e x ter nal memor y dis abled. GPIO[3 : ...

  • LSI LSI53C875A - page 129

    SCSI Registers 4-37 ab y t es t o r e di ns y s t e mm e m o r y ,t h eb y t em u s tf i r s tb e mov ed to an in ter mediate LS I53C87 5A regis ter (such as a SCRA TC H regist er), and then to the S FBR. This regi ster als o contains t he state o f the lower eigh t bits of the S CSI data bus dur ing t he Sel ection ph ase if the COM bit in the DMA ...

  • LSI LSI53C875A - page 130

    4-38 R egist er s Regist er: 0x0A SCSI Se lector ID (SSI D) Read Only V AL SCSI V alid 7 If V AL i s asser te d, then the two SCS I IDs are d etected on the bus durin g a b us-ini tiated sele ction or re selecti on, and the encod ed destinati on SCSI ID bits below are v alid . If V AL i s deasser ted, on ly one ID i s prese nt and t he conte nts of ...

  • LSI LSI53C875A - page 131

    SCSI Registers 4-39 REQ SREQ/ Stat us 7 AC K S AC K / S t a t u s 6 BSY SBSY/ Status 5 SEL SS EL/ Statu s 4 AT N S A T N / S t a t u s 3 MSG SMSG/ St atus 2 C_D SC_D/ Status 1 I_O SI_O/ St atus 0 Regist er: 0x0C DMA Status (DST A T) Read Only Readin g this re gister cle ars any bits tha t are set at t he time the r egister is read, but does not nec ...

  • LSI LSI53C875A - page 132

    4-40 R egist er s MDPE Master D ata P arity E rror 6 This b it is set wh en the LS I53C 875A as a mas ter de tect s a data par ity err or , or a targe t de vice sig nals a par ity erro r duri ng a data phase. This bit is co mpletely di sabled b y th e Mast er P ari ty Err or E nab le bit ( bit 3 of Chi p T es t F our (CTEST4) ). BF Bus Fault 5 This ...

  • LSI LSI53C875A - page 133

    SCSI Registers 4-41 • Duri ng a T ransfer Control i nstruc tion, t he Compare Data (bit 18 ) and Co mpare Pha se (bit 17 ) bits ar e set in the DMA Byte Coun ter (DBC) reg ister whil e the LSI53C 875A is i n tar get mode. • Duri ng a T ransfer Control i nstruc tion, t he Carr y T e st bit (bit 2 1) is se t and eit her the Comp are Data ( bit 18 ...

  • LSI LSI53C875A - page 134

    4-42 R egist er s Regist er: 0x0D SCSI Sta tus Zer o (SST A T0) Read Only ILF SIDL Least S ignifican t Byte Full 7 This bit is set whe n the least sign ificant byte in the SCSI In put Dat a Latch (S IDL ) regi ster con tains dat a. Data i s transferred from the SCSI bus to the SCS I Input Da ta Latch registe r before bein g sent to th e DMA FI FO a ...

  • LSI LSI53C875A - page 135

    SCSI Registers 4-43 AIP Arbitration in Pr ogress 4 Arbitration in Progre ss (AIP = 1) indica tes that the LSI53C 875A has de tected a Bus F ree cond ition, as ser ted SBSY , and as ser ted its SCSI ID ont o the SCSI bus. LO A Lost Arbitr ation 3 When set , LO A indicat es that the LSI53C 875A has de tecte d a b us fr ee cond it ion, ar bitr ated f ...

  • LSI LSI53C875A - page 136

    4-44 R egist er s synchr onous da ta transfers, or up to 31 wo rds f or wide. V alue s ov er 31 will not occ ur . T able 4.6 SCSI Synch ronous Data FIFO W ord Count FF4 (SST A T2 bit 4) FF3 FF2 FF1 FF0 Bytes or W ords in th e SCSI FIFO 0 0000 0 0 0001 1 0 0010 2 0 0011 3 0 0100 4 0 0101 5 0 0110 6 0 0111 7 0 1000 8 0 1001 9 0 1010 1 0 0 1011 1 1 0 ...

  • LSI LSI53C875A - page 137

    SCSI Registers 4-45 SDP0 L La tc hed SCSI P arity 3 This bit r eflects the SCSI p arity signal ( SDP0/), corre sponding to th e data latched i n the SCSI Inpu t Data Latch ( SIDL) . It cha nges whe n a ne w byte is latched i nto the lea st signi ficant byte of the SIDL registe r . Th is bit is active HIGH , in other words, it is s et when t he par ...

  • LSI LSI53C875A - page 138

    4-46 R egist er s Regist er: 0x0F SCSI Status T w o (SST A T2) Read Only ILF1 SIDL Most Significant Byte Full 7 This bit i s set when t he mos t signifi cant byte in the SCSI In put Da ta Latc h (SID L) cont ains d ata. Data i s transferred from the SCS I b us to the SCS I Input Data La tch register bef ore being se nt to the DMA FIFO and then to t ...

  • LSI LSI53C875A - page 139

    SCSI Registers 4-47 fi eld, s ee the d efi nit ion f or SCSI Stat us One (SST A T1) bits [7:4] . SPL1 Latched SCSI P arity f or SD[15:8] 3 This a ctiv e HIGH bi t reflec ts the SCS I odd pa rity s ignal corre sponding to the da ta latched into th e most s i g n i f i c a n tb y t ei nt h e SC SI Input Data Latch (S IDL) registe r . R Reser ved 2 LD ...

  • LSI LSI53C875A - page 140

    4-48 R egist er s Regist er: 0x14 Interrup t Status Zero (IS T A T0) Read/Write This r egister is acces sible by the host CP U whil e a LSI5 3C875A is e x ecuting SCRIP TS (without inte rf eri ng in the operation of the function ). It is use d to poll for interr upts if har dware interr upts a re disabled. Re ad this re gister a fter ser v icing an ...

  • LSI LSI53C875A - page 141

    SCSI Registers 4-49 clea r the ID Mod e bit or a ny of the PCI co nfigura tion registe rs. This bit is no t self- clear in g; it must be c leared to clear the reset cond ition (a hardware rese t also clears this bit). SIGP Si gna l Proce ss 5 SIGP i s a R/W b it that is wr itable at any tim e, and pol led and res et using C h i p Te s t Tw o ( C T ...

  • LSI LSI53C875A - page 142

    4-50 R egist er s the SCRIPTS pr ocesso r is s til l e xecuting a SCRIPTS program. If this bit is set when th e Interr upt Sta tus Zero (IST A T0) or Interr upt Stat us One ( IST A T1) regi sters ar e read th e y are n ot automat ically c leared. T o c lear this b it, writ e it to a one. The res et operatio n is sel f-clear ing. Note: If th e INTF ...

  • LSI LSI53C875A - page 143

    SCSI Registers 4-51 • A bus f ault i s dete cted • An abo r t c ondition i s detect ed • A SCRIPT S instr uction i s ex ecuted in si ngle step mode • A SCRIPT S inter rupt i nstr uction is e xecuted • An ille gal instr ucti on is detected T o deter mi ne e xac tly whic h condit ion(s) caused the interr upt , read the DMA Status ( DST A T) ...

  • LSI LSI53C875A - page 144

    4-52 R egist er s additi on, this bit ma y be read and wr itten while SCR IPTS are ex e cuting. Regist er: 0x16 Mailbox Zero (MBO X0) Read/Write MBO X0 Mail bo x Zer o [7:0] These are general pu r pose bits that may be read or writ ten whil e SCRIP TS are r unnin g. They also may be read or writt en b y the SCRIPT S processor . Note: The h ost an d ...

  • LSI LSI53C875A - page 145

    SCSI Registers 4-53 Regist er: 0x18 Chip T est Ze r o (CTEST 0) Read/Write FMT Byte E mpty in DM A FIFO [7:0] These bits iden tify the bottom bytes in the DM A FIFO that are empty . E ach bit cor respond s to a byte lane in the DMA FIFO . For example, if byte lane three is empty , then FMT3 will be set. Sinc e the FMT flags ind icate the stat us of ...

  • LSI LSI53C875A - page 146

    4-54 R egist er s Regist er: 0x1A Chip T est T w o (CTEST2) Read Only (bit 3 write) DDIR Data T ransfer Di rection 7 This st atus bit indic ates whic h direc tion d ata is being transferred. When th is bit is s et, the d ata is transferred from the S CSI bus to the host bus. Whe n this bit i s clear , th e data i s tr ans f erred from th e hos t b ...

  • LSI LSI53C875A - page 147

    SCSI Registers 4-55 Base Addr ess Re gister One (M EMOR Y) .T h i si st h e memor y mapped o perating register base addr ess. Bits [9:0] wi ll be 0. The SCRA TCHB r egister contains bits [31:13] of the RA M Base Addr ess value from the PCI Base Addre ss Regis ter T wo (S CRIP TS RAM) .T h i si st h e base addr ess for the inter nal 4 Kbytes RAM. Bi ...

  • LSI LSI53C875A - page 148

    4-56 R egist er s Regist er: 0x1B Chip T est Th ree (CT EST3) Read/Write V C h i pR e v i s i o nL e v e l [ 7 : 4 ] These b its iden tify th e chip revision lev el for software pur pos es. It sho uld hav e the same value as t he lower nibble of the PCI Re vis ion ID (Re v ID) re gister , at a ddress 0x08 in t he con figuration spa ce. FLF Flush DM ...

  • LSI LSI53C875A - page 149

    SCSI Registers 4-57 WRIE Write and Inv alidate Enable 0 This b it, when set, caus es the is suing of Wr ite and Inv al idate comma nds on the PCI b us whenev er legal. The Wr ite an d Inv a lidat e Enable bit in the PCI Config uration Comm and reg ister must al so be set i n order for the chip to gene rate Wr ite an d Inv a lidate comm ands. Regist ...

  • LSI LSI53C875A - page 150

    4-58 R egist er s while data is be ing transferred between t he two cor es. Once the chip has stop ped transferring data, thes e bits ar e s tabl e. The DMA F IFO (D FIF O) regist er counts th e number of b yte s transf erred between the DMA c ore and th e SCSI cor e. The DMA Byte C ounter (DBC) regis ter coun ts the n umber of by tes tr ansf err e ...

  • LSI LSI53C875A - page 151

    SCSI Registers 4-59 Regist er: 0x21 Chip T est Four (CTEST4) Read/Write BDIS Bur st Disable 7 When set , this bit caus es the LSI5 3C875A to perf or m bac k-to-b ac k cyc les f or al l tra nsf ers . Whe n thi s bit is clea red, back-to-back transf ers for opc ode f e tches and b ur st tr ans f e rs f or data mov es are per f or med. FBL3 FIFO Byte ...

  • LSI LSI53C875A - page 152

    4-60 R egist er s LSI53C 875A is inf or med of the error by the PERR/ pin being asser ted by the t arget. Whe n this bi t is clea red, th e LSI53C 875A does not in terr upt if a master parit y error occu rs. This bit is clea red at power-u p . FBL[2:0] FIFO Byte Contr ol [2:0] These b its stee r the cont ents of the Chip T est S ix (CTEST6) registe ...

  • LSI LSI53C875A - page 153

    SCSI Registers 4-61 the curr ent DBC value. This bit auto matic ally cle ars itse lf after inc rementi ng the DNAD register . BBCK Cloc k Byte Counter 6 Settin g this bi t decrem ents th e byte count co ntaine d in the 24-bi t DBC r egister . It is d ecremen ted based o n the DMA Byte Co unter (DB C) cont ents and the curr ent DMA Ne xt Addr ess (D ...

  • LSI LSI53C875A - page 154

    4-62 R egist er s BO[9:8] DMA FIFO Byte Offset Counter , Bits [9:8] [1:0] These a re the upp er two bits of the DFBO C . The DFB OC cons ists of th ese bits, and the DMA FIFO (DFIFO) registe r , b its [7 :0]. Regist er: 0x23 Chip T est Six (CTE ST6) Read/Write DF DMA FI FO [7:0] Wri ting to this reg ister wr ites data to the ap propr iate byte lane ...

  • LSI LSI53C875A - page 155

    SCSI Registers 4-63 LSI53C 875A. Th e DBC c ounter is decr emente d each time da ta is transferred on the PCI bus. It is de cremente d b y a n amount equal to th e number of bytes that are transf erred. The maximum numbe r of b ytes that ca n be transf erred in any one Blo ck Mov e c ommand is 16,7 77,215 bytes. The maxi mum v alue th at can b e lo ...

  • LSI LSI53C875A - page 156

    4-64 R egist er s Regist er s: 0x28–0 x2B DMA Next Address (DNA D) Read/Write DNAD DMA Next Ad dress [31:0] This 32- bit regis ter contai ns the general pur pose addr ess pointer . At the s tar t of some S CRIPTS operations, i ts v alue is copi ed from the DMA SCRIPTS P ointer Sa ve (DSP S) regi ster . Its v al ue ma y n ot be v alid e xce pt in ...

  • LSI LSI53C875A - page 157

    SCSI Registers 4-65 Regist er s: 0x30–0 x33 DMA SCRI PTS P oin ter Save (D SP S) Read/Write DSPS DMA SCRI PTS P ointer S ave [31:0] This register c ontains the second Dword of a SCRIPTS instr uct ion. It i s ov erwr itten each time a S CRIPT S instr uct ion is f etched . When a SCRIPTS interr upt instr uct ion is ex ecute d, this regi ster hol ds ...

  • LSI LSI53C875A - page 158

    4-66 R egist er s Regist er: 0x38 DMA Mode (DMODE) Read/Write BL[1:0] Burs t Length [7:6] These b its cont rol th e maximum numb er of D words transf erred per bus ownership , regardl ess of whether the transfers are back-to-b ack, b urst, o r a comb inatio n of both. The L SI53C8 75A as ser ts the Bus Requ est (REQ /) output whe n the DMA FIFO c a ...

  • LSI LSI53C875A - page 159

    SCSI Registers 4-67 SIOM Source I/O Me mory En able 5 This bit is defined as an I/O Memor y Enable bit f or the sour ce addr ess of a Memo r y Move or Blo c k Mov e Comman d. If this bit i s set, then the s ource ad dress is in I/O space; and if clear ed, then the source add ress is in memor y s pace. This func tion is usefu l f or r egister -to-me ...

  • LSI LSI53C875A - page 160

    4-68 R egist er s ERMP Enable Read Multiple 2 If this bi t is set a nd cache mode i s enabled, a Rea d Multi ple comm and is used on a ll read c ycles w hen it is legal . BOF B urst Opcode Fetc h Enable 1 Settin g this bit caus es the LSI53C 875A to f etch ins tructions in burs t mode . Speci fical ly , the chip b urst s in t h ef i r s tt w oD w o ...

  • LSI LSI53C875A - page 161

    SCSI Registers 4-69 Regist er: 0x39 DMA Interrupt Enable (DIEN) Read/Write R Reser ved 7 MDPE Master D ata P arity E rror 6 BF Bus Fault 5 ABRT Aborted 4 SSI Sin gle Step Interrupt 3 SIR SC RIPTS In terru pt Inst ruction Receive d 2 R Reser ved 1 IID Ille gal Instructi on Detected 0 This reg ister conta ins the interr upt ma sk bits cor respondi ng ...

  • LSI LSI53C875A - page 162

    4-70 R egist er s F or more informat ion on interr upts, see Chapter 2, “Functi onal Descrip tion” . Regist er: 0x3A Scratch By te Register (SBR) Read/Write SBR Scratch Byte Re gister [7:0] This i s a ge neral pur pose re gister . Apar t fr om CPU acce ss, only r egister Read/Wr ite and Memor y Mov es i nto this re gister a lter its co ntents. ...

  • LSI LSI53C875A - page 163

    SCSI Registers 4-71 the LSI53C 875A to make more efficient use of the syst em PCI b us, t hus imp ro vin g ov eral l syste m performa nce. The unit wi ll flush whene v er th e PFF bit is set, as well as on all transfer control ins truc tions whe n the transfer conditi ons are met, on ev er y wr ite to the DMA SCRIPTS P oin ter (DSP) , on e ver y re ...

  • LSI LSI53C875A - page 164

    4-72 R egist er s STD S tart DM A Operation 2 The LSI5 3C875A fetches a SCS I SCRIPT S inst r uction from the a ddress containe d in the DMA S CRIPTS P ointer (DSP) regis ter when thi s bit is set. Th is bit is req uired if the LS I53C8 75A is in o ne of the f ollowin g modes : • M a n u a ls t a r tm o d e–B i t0i nt h e DMA Mode (DMODE) regis ...

  • LSI LSI53C875A - page 165

    SCSI Registers 4-73 Regist er s: 0x3C– 0x3F Adder Sum Outpu t (ADDER) Read Only ADDER Adder Sum Output [31:0] This reg ister c ontains th e outpu t of t he inte rn al add er , and is used pr imar ily f or test pur pose s. The power-up v alue f or thi s regis ter is i ndeter m inate. It is used t o deter mi ne if the corre ct memor y addr ess was ...

  • LSI LSI53C875A - page 166

    4-74 R egist er s CMP Fun ction Complete 6 Indicate s full arbi tration and s electio n sequenc e is compl eted. SEL S ele cted 5 Indicate s the LSI53C 875A is s elected b y a SCSI initiato r de vice. Set th e Enable Res ponse to Selec tion bit in the SCSI Chip ID (SCI D) reg ist er f or thi s to occur . RSL Reselec ted 4 Indicate s the LSI53C 875A ...

  • LSI LSI53C875A - page 167

    SCSI Registers 4-75 RST SCSI Reset Condition 1 Indicate s ass er tion of th e SRST/ s ignal by t he LSI53C 875A or any othe r SCSI device. This condi tion is edge-tr ig gered, s o multiple i nterru pts canno t occu r because of a si ngle SRS T/ pulse. PA R S C S I P a r i t y E r r o r 0 Indicate s detecti on by the LSI53C 875A of a par ity err or ...

  • LSI LSI53C875A - page 168

    4-76 R egist er s HTH Handshake-to- Handshake Timer Expire d 0 The han dshake-to-h andsh ak e t imer is expire d. The ti me measu red is the S CSI Req uest-to-Req uest (tar get) or Acknowledge-to- Acknowledge (ini tiator) peri od. Se e the descr ip tion of t he SCSI Ti mer Zero (S TIME 0) register , bits [7:4] , fo r more i nf or matio n on the han ...

  • LSI LSI53C875A - page 169

    SCSI Registers 4-77 target . In target mode, this bi t is set wh en the S A T N/ sign al is asser ted by the initiator . CMP Fun ction Complete 6 This b it is set whe n an ar bitration o nly or fu ll arbitration seque nce i s comple ted. SEL S ele cted 5 This b it is se t when the LSI53C 875A i s selected by anothe r SCSI device. The Enable Resp on ...

  • LSI LSI53C875A - page 170

    4-78 R egist er s • Residual data in the synchr onous da ta FIFO – a transfer other tha n syn chronou s data receive is star ted wi th data l eft in the s ynchr onous data FIFO . UDC Unexpected Disconnect 2 This bit is set when the LSI53C 875A is operating in the initi ator mode and the targe t de v ice unexpectedly discon nects from t he SCSI ...

  • LSI LSI53C875A - page 171

    SCSI Registers 4-79 (SIEN1) register or not. E ach bit tha t is set indicate s an occ urrence of the corres ponding con ditio n. Readin g the S IST1 cl ears the inter rupt c onditio n. R Reser ved [7:3] ST O Se lection or Rese lection Time -out 2 The SCSI device which the LSI 53C875A i s attempti ng to sele ct or re selec t does no t respond within ...

  • LSI LSI53C875A - page 172

    4-80 R egist er s check byte are rec eived from the S CSI bus (all signals are shown ac tiv e HIG H): A one in any bit po sition of the fi nal SLP AR value would i n d i c a t eat r a n s m i s s i o ne r r o r . The SLP AR re gister is also use d to generate the check b yte s f or SCSI send o peration s. If the SL P A R regist er conta ins all zer ...

  • LSI LSI53C875A - page 173

    SCSI Registers 4-81 W h i c hb y t ei sa c c e s s e di sc o n t r o l l e db y t h eS L P H B E Nb i t in the SCSI Control T wo (SCNTL2) register . Regist er: 0x45 SCSI Wide Residue (SW IDE) Read/Write SWIDE SCSI Wide R esidue [7:0] After a wi de SCS I data rec eiv e ope ration, this regis ter conta ins a residu al data byte if the last byte recei ...

  • LSI LSI53C875A - page 174

    4-82 R egist er s DW R D a t a W r i t e 3 This bi t is used t o defin e if a data write is c onside red t o be a lo cal m emor y acce ss. DRD Data Read 2 This bit is used to define if a data r ead is consi dered to be a lo cal m emor y acce ss. PSCPT P ointer SCRIPTS 1 This b it is used t o define if a po inter t o a SCRIPT S indire ct or table in ...

  • LSI LSI53C875A - page 175

    SCSI Registers 4-83 LEDC LED_CNTL 5 The inte rn al con nected si gnal (bi t 3 of the Inte rrupt S tat us Zero (IST A T0 ) reg ist er) wi ll be pres ente d on GP IO0 i f th is bit is s et and b it 6 of GP CNTL0 is cleare d and the c hip is no t in progress of perfor ming a n EEP R OM autodownlo ad regar dless of the sta te of bi t 0 (GPI O0). This p ...

  • LSI LSI53C875A - page 176

    4-84 R egist er s SEL[ 3:0] Select ion Time-Ou t [ 3:0] Thes e bits sel ect t he SCSI s elect ion/r e sel ectio n time- out pe riod. When th is timi ng (plu s the 200 µ s sel ection a bor t time) is e xceede d, the S T O bi t in the SC SI Inter rup t Status O ne (SIST1 ) registe r is set. For a mo re det ailed e xplanati on of in terrup ts, ref er ...

  • LSI LSI53C875A - page 177

    SCSI Registers 4-85 Regist er: 0x49 SCSI Timer One (STIME1) Read/Write R Reser ved 7 HTHB A Hands hake-to-Handshake Timer Bus Activity Enable 6 Settin g this bit caus es this time r to begin tes ting for SCSI REQ/, ACK/ activ ity as soon as SBSY/ is as ser ted, regard less of the agents par ticipat ing in the transfer . GENSF General Purp ose Timer ...

  • LSI LSI53C875A - page 178

    4-86 R egist er s Regist er: 0x4A Re spon se ID Zer o (RES PID0 ) Read/Write RESPIO0 Response ID Zero [7:0] RESPID0 a nd Respon se ID One (RESPID1) contain the sele ction or resele ction IDs. In ot her words, these two 8-bit r egister s contain the I D that the c hip respo nds to o n the SCSI bus. Each bit repres ents one p ossible ID with the most ...

  • LSI LSI53C875A - page 179

    SCSI Registers 4-87 c h i pc a na r b i t r a t ew i t ho n l yo n eI Dv a l u ei nt h eS C I D registe r . Regist er: 0x4C SCSI T est Zero ( STEST0) Read Only SSAID SCSI Sele cted As ID [7:4] These bi ts contai n the encoded value o f the SCSI ID th at the LSI53C 875A is selec ted duri ng a SCSI selectio n phase. Th ese bit s work i n conju nctio ...

  • LSI LSI53C875A - page 180

    4-88 R egist er s SOM SCSI Synchr onous Offset Maxim um 0 This bi t ind icate s that the cu rren t synch ronou s SREQ/ , SA CK/ of fse t is the maxi mum specifi ed by bits [3:0 ] in the SCSI T ran sfer (SXFER ) reg ister . This bit is not la tched and may change at any time. It is us ed in low lev el synchr onous SCSI ope rations. When this bit is ...

  • LSI LSI53C875A - page 181

    SCSI Registers 4-89 QSEL SCLK Qua drup ler Select 2 This bit , when s et, sel ects the output of the in ter nal cl oc k quadr upler f or use a s the inte r nal SCS I clock. Whe n clea red, this b it selects the c lock presente d on SCLK for use as th e inter n al SCSI c loc k. R Reser ved [1:0] Regist er: 0x4E S C S I Te s t Tw o ( S T E S T 2 ) Re ...

  • LSI LSI53C875A - page 182

    4-90 R egist er s SZM SCSI Hi gh Imp edance Mode 3 Settin g this bi t place s all th e open drain 48 mA SCSI dri v ers in to a high impedan ce st ate. This is to allow inter na l loopback mo de operation wit hout affecting the SCSI bus. A W S A l w a y sW i d eS C S I 2 When t his bit i s set, all SCSI inform ation t ransf ers ar e done in 16 -bit ...

  • LSI LSI53C875A - page 183

    SCSI Registers 4-91 Regist er: 0x4F SCSI T est Three (STE ST3) Read/Write TE T oler ANT Enable 7 Settin g this bi t enables th e active negatio n por tion of LSI Lo gic T oler ANT tec hnology . Ac tiv e neg ation c auses the SCSI Re quest, Ackno wledg e, Data, and P a r ity sign als to b e act ively deasse r ted, inste ad of r elyi ng on e xter nal ...

  • LSI LSI53C875A - page 184

    4-92 R egist er s f o r test pur poses or to lower I DD during a po wer -do wn mode. DSI Dis abl e Sin gl e Ini ti ator Re sp ons e 4 If this bi t is set, the LS I53C875 A ignores a ll bus-initiated sele ction atte mpts that empl o y th e single in itiator opti on from SCS I-1. In ord er to se lect the LS I53C8 75A while t his bit is set, t he LSI5 ...

  • LSI LSI53C875A - page 185

    SCSI Registers 4-93 STW SC SI FIFO T es t Wri te 0 Settin g this bit place s the SC SI core i nto a tes t mode i n which the FIF O is easily read or writ ten. While this bit is set, wr ites to the le ast sign ificant byte of th e SCS I Out put Data Latch (SO DL) regis ter caus e the en tire word conta ined in the SODL to be loaded into the FIFO . T ...

  • LSI LSI53C875A - page 186

    4-94 R egist er s Regist er: 0x52 SCSI T est Four (STEST4) Read Only R Reser ved [7:6] LOCK Frequency Loc k 5 This bi t is use d when en abling the S CSI clock quadr upl er , whic h all o ws the LSI 53C 875A to tr ans f er data at Ul tr a SC SI rates. P oll t his bit for a 1 to d eter mine tha t the clock quadr upler h as locked. F or more infor ma ...

  • LSI LSI53C875A - page 187

    SCSI Registers 4-95 Regist er: 0x56 Chip Contr ol 0 (CCNTL0) Read/Write ENPMJ E na ble Phase Mis match Jump 7 Upon se tting this bit, any phas e misma tches do not interr upt b ut force a jump to an al ter nate l ocation to handl e the phase mism atch. Pr ior to actu ally takin g the jump , the appro pria te rem aining byte co unts a nd addre sses ...

  • LSI LSI53C875A - page 188

    4-96 R egist er s ENNDJ Enable Jump on Nond ata Phase Mismatches 5 This bit con tro ls whe ther or not a jum p is tak en during a no ndata p hase mis match (i.e . messa ge in, mes sage o ut, status, or c omman d). When t his bi t is clear , jump s will only be t aken on Data-In o r Data -Out pha ses and a phase mi smatch inter ru pt will be generat ...

  • LSI LSI53C875A - page 189

    SCSI Registers 4-97 Regist er: 0x57 Chip Contr ol 1 (CCNTL1) Read/Write ZMO DE Hig h Impe dan ce Mod e 7 Settin g this b it ca uses t he LSI53C 875A t o pl ace all ou tput and bidir ecti onal pins e xcep t MAC/_TEST OUT , in to a high im pedance sta te. Also , setti ng this bit causes all I/O pins to bec ome inputs, and al l pull-up s and pull-d ow ...

  • LSI LSI53C875A - page 190

    4-98 R egist er s Inde x Mode 1 (64TIMO D set) table entr y f or mat: EN64TIBMV Ena ble 64-Bit T able Indirect BMO V 1 Settin g this bi t enables 64 -bit addr essin g f or T able Indirec t BMO Vs using th e upper byte (bit [24:31]) of the first Dwor d of the table entr y . When this b it is clear ed table indir ect BMO Vs w ill us e the Static Bl o ...

  • LSI LSI53C875A - page 191

    64-Bit SCRIPTS Selec tors 4-99 Regist er: 0x5A– 0x5B Rese rved Regist er s: 0x5C– 0x5F Scratch Regi ster B (SCRA TCHB) Read/Write SCRA TCHB Scrat ch Register B [31:0] This i s a ge neral pur pose use r defi nable scratch pad registe r . Apa r t fr om CPU a ccess, on ly regi ster Read/Wr ite and Memor y Mov es dir ected at the SCRA TCH reg iste ...

  • LSI LSI53C875A - page 192

    4-100 Reg isters operation i s performed , one of the si x selector regist ers below will be used t o generate a 6 4-bit add ress. If the s elector f o r a par ticul ar device operation is zero , then a s tandard 32-bit a ddress cycle w ill be gen erated. If the se lector value is nonzero , then a D AC will be is sued and the 64-bi t addres s will ...

  • LSI LSI53C875A - page 193

    64-Bit SCRIPTS Selec tors 4-10 1 Regist er s: 0xA4–0x A7 Memor y Move Wri te Selecto r (MMW S) Read/Write MMWS Memor y Move Write Selector [31:0] Suppl ies the upper Dword of a 64-bit addr ess duri ng data writ e operations du rin g Memor y-to- Memor y Moves and absolute addre ss ST O RE operations. A speci al mode of th is registe r can be enabl ...

  • LSI LSI53C875A - page 194

    4-102 Reg isters Write s to the SF S regis ter ar e unaf f ected . Clea ring the PCI Confi guratio n Into En able bit causes the S FS regis ter to retur n to nor m al operatio n. Regist er s: 0xA C–0 xAF DSA Rela tive Selector (DRS ) Read/Write DRS DSA Relative S elector [31: 0] Suppl ies the u pper Dword of a 64- bit add ress du ring table indir ...

  • LSI LSI53C875A - page 195

    Phase M isma tch Jump Re gis ters 4 -1 03 Regist er s: 0xB4–0x B7 Dynamic Blo ck Mo ve Sel ector (DBM S) Read/Write DBMS Dyn amic Block Move Select or [ 31:0] Suppl ies the u pper Dword of a 64- bit add ress du ring b lock mov e operatio ns, reads or wr ites. This reg ister is used only du ring 64 -bit dire ct BMO V ins truc tions and wil l be re ...

  • LSI LSI53C875A - page 196

    4-104 Reg isters Regist er s: 0xC0–0x C3 P h a s eM i s m a t c hJ u m pA d d r e s s1( P M J A D 1 ) Read/Write PMJAD1 Phase Mismat ch J ump A ddress 1 [31:0] This r egister contain s the 3 2-bit address that will be jumpe d to upon a ph ase mism atch. Dep ending upon t he state o f the PM JCT L bit in r egist er Chip Control 0 (CCNTL0) this ad ...

  • LSI LSI53C875A - page 197

    Phase M isma tch Jump Re gis ters 4 -1 05 Regist er s: 0xC8–0x CB Remaining Byte Count (RBC) Read/Write RBC Remaining Byte Count (RBC) [31:0] This regi ster co ntains the byte coun t that re mains for the BMO V th at w as e x ecuti ng when the phase mism atch occu rred. In the cas e of dir ect or in direct BMO V instr uct ions, the up per byte of ...

  • LSI LSI53C875A - page 198

    4-106 Reg isters In the c ase of a S CSI dat a receive, if ther e is a byte in the SCSI Wi de Resid ue (SWI DE) register th en this addre ss will poin t to the location where tha t byte must be stored. The S WIDE byte must be manually wr itten to memor y and th is addr ess must be increm ented pr ior t o updati ng any scatte r/gather entr y . In th ...

  • LSI LSI53C875A - page 199

    Phase M isma tch Jump Re gis ters 4 -1 07 Regist er s: 0xD4–0x D7 Instruct ion Address ( IA) Read/Write IA Instruction Addr ess [31: 0] This r egister alwa ys conta ins th e addres s of the BMO V instr uct ion tha t was ex ecuti ng when the phase m isma tch occu rred. Thi s value will a lwa ys matc h the value in the Entr y Storage Address ( ESA) ...

  • LSI LSI53C875A - page 200

    4-108 Reg isters canno t be counte d f or th is BMO V as it was act ually p ar t of the byte coun t for the pre vious B MO V . Regist er: 0xDB Rese rved Registers: 0x DC–0xDF Cum ulative SCSI Byte Count (CSBC) Read/Write CSBC Cumulative SCSI Byte Count [31:0] This loa dable register co ntains a cumulat ive coun t of the actual numb er of bytes th ...

  • LSI LSI53C875A - page 201

    LSI53C8 75A PCI to Ultra SCSI Controll er 5-1 Chapter 5 SCSI SCRIPTS Instruction Set The LSI5 3C875A co ntains a S CSI SCR IPTS proc essor that per mits bot h DMA an d SCSI com mands to be fetched from host m emor y or inter nal SCRI PTS RAM . Algo rith ms wr itten i n SCSI S CRIPT S contro l the ac tions of the S CSI and DMA cores. The SCRIP TS pr ...

  • LSI LSI53C875A - page 202

    5-2 SCSI SCRIPTS Instruction Set requir e cer tain uni que timings or bus sequence s to operate properl y . Anothe r f eature al lowed at the low le v el is l oopback testin g. In loopback m o d e ,t h eS C S Ic o r ec a nb ed i r e c t e dt ot a l k t ot h eD M Ac o r et ot e s t inter nal data p aths all the way out to the c hip’ s pi ns. 5.2 H ...

  • LSI LSI53C875A - page 203

    High Le v el SCSI SCRIPTS Mode 5-3 Each instr ucti on co nsists of two or thre e 32-bit w ords. The f irst 32-bi t wo rd is alw a ys loaded in to the DMA Command (DCM D) and DMA By te Counter (DBC) regi ster s, the s econd into t he DMA S CRIPTS P o inter Sav e (D SPS ) register . The third word, us ed only by Memor y Mov e instr ucti ons, is loade ...

  • LSI LSI53C875A - page 204

    5-4 SCSI SCRIPTS Instruction Set • The LSI5 3C875 A typic ally fetches two Dwo rds (64 bit s) an d deco des the hig h order byte of the fi rst longword a s a SCRIPTS instr uction. If the instr u ction is a B lock Mov e, the lower three bytes of the f irst longword ar e store d and inter preted as the number of bytes to be mov ed. The s econd l on ...

  • LSI LSI53C875A - page 205

    High Le v el SCSI SCRIPTS Mode 5-5 Figure 5.1 SCRIPTS O verview System Proces sor System Memory SCS I Initiator Write Exam ple × Select A TN 0, alt _addr × Move from iden tify_msg_buf, when MSG_ OUT × Move from dat a_buf when DA T A_OUT × Move from stat _in_buf, when ST A TUS × Mov e SCNTL2 & 7F t o SCNTL2 × Clear ACK × Wail disconnect a ...

  • LSI LSI53C875A - page 206

    5-6 SCSI SCRIPTS Instruction Set 5.3 Bloc k M o ve Instru ction P erformi ng a Bl oc k Move instr uctio n, bit 5, Sou rce I/ O - Memor y Enable (SIOM) a nd bit 4, Des tination I /O - Memor y E nable (DIOM) in the DMA Mode (DMO DE) regi ster dete rm ines whet her the sourc e/destina tion address resid es in memo r y or I/O space. Wh en data is being ...

  • LSI LSI53C875A - page 207

    Bloc k Mo ve Inst ruction 5-7 Direct Addressi ng The b yte count a nd abs olut e addr ess ar e: Indirect Addressing Use the f etched byte count, b ut f e tch the data address from the address in the ins truc tion. Once the data po inter add ress i s loaded, it is e xecuted as when th e chip operates i n the dire ct mod e. This ind ire ct f eatu re ...

  • LSI LSI53C875A - page 208

    5-8 SCSI SCRIPTS Instruction Set the data str ucture. Sign e xtende d v alues of all ones f or negati v e values ar e allowed, but bits [31:24] ar e ignored . Note: Do n ot use indire ct and ta ble indir ect add ressin g simulta neously ; use only one a ddress ing metho d at a time. P r i o rt o t h es t a r to fa nI / O ,t h e Data Str uctur e Add ...

  • LSI LSI53C875A - page 209

    Bloc k Mo ve Inst ruction 5-9 OPC OpCode 27 This 1 -bit OpC ode field d efines th e type of Block Mov e (MO VE ) Instru ction to be p ref or med i n T a rget and Initi ator mode. T arget Mode In T arget mode, the Op Code bit define s the following operations : These i nstruc tions pe rf or m the following st eps: 1. The LSI5 3C875A verifi es that i ...

  • LSI LSI53C875A - page 210

    5-10 SCSI SCRIPTS Instruction Set registe r contai ns 0x000 000, an illegal instr ucti on interr upt is ge nerated. 4. The LSI5 3C875A t r ans f e rs the number of bytes specifi ed in the DBC regist er sta r tin g at the a ddress sp ecified in the DMA Next Address (DNAD) r egist er . If the O pCode b it is set and a data transfer ends on an odd byt ...

  • LSI LSI53C875A - page 211

    Bloc k Mo ve Inst ruction 5-11 registe r . Thes e phase l ines a re latched when SRE Q/ is asse r ted . 4 . I ft h eS C S Ip h a s eb i t sm a t c ht h ev a l u es t o r e di nt h eS C S I SCSI Statu s On e (SST A T1 ) regis ter , th e LSI53C875 A transf ers the number of b ytes s pecifie d in the DMA Byte Counter (DBC) regis ter star tin g at the ...

  • LSI LSI53C875A - page 212

    5-12 SCSI SCRIPTS Instruction Set TC[23:0] T ra nsfer Counte r [23:0] This 24 -bit fi eld speci fies th e number of d ata bytes to be mov ed between the LSI53C8 75A and system mem or y . The fie ld is stor ed in the DMA Byte Cou nter (DBC ) registe r . Wh en the LSI53 C875A t ransf e rs data t o/from memor y , the DBC r egister is dec remente d by ...

  • LSI LSI53C875A - page 213

    I/O Ins tr uc tio n 5- 13 5.3.2 S econd Dw or d Star t Address [31:0] This 32-b it field s pecif ies the sta r tin g addre ss of the data to mov e to/from mem or y . This field is copi ed to the DMA Ne xt Addres s (DNAD) r egister . When th e LSI53 C875A transfers data to or f rom memo r y , the DNAD r egister is increm ented by the num ber of byte ...

  • LSI LSI53C875A - page 214

    5-14 SCSI SCRIPTS Instruction Set 5.4.1 F irst Dw or d IT[1:0] Instruc tion T ype - I/O Instruc tion [31:30] The IT bit co nfiguration (01) de fines an I/O I nstr uction Ty p e . OPC[2:0] Op Code [29:27] The Op Code bi t configuration s define the I/ O operation performe d b ut the OpCode bit meanin gs change in T arget mode com pared to Initiato r ...

  • LSI LSI53C875A - page 215

    I/O Ins tr uc tio n 5- 15 This wa y the SCR IPTS can m o v e on to the ne xt instr uct ion before the r esele ction compl etes. It con tinues e x ecuting SCRIPTS u ntil a SCRIPT th at req uires a respons e from th e Initiator is enc ountered . If the LS I53C875A i s selecte d or resel ected before winni ng arbitratio n, it fetches the next instr uc ...

  • LSI LSI53C875A - page 216

    5-16 SCSI SCRIPTS Instruction Set When t he SACK/ or SA TN/ b its are clear ed, the corre sponding bits a re clea red in the SCSI O utput C ontrol La tch ( SOCL) r egister . Do not s et SA CK/ or S A TN/ e xce pt f or t esti ng pur pos es . When t he target bi t is cle ared, the c orrespon ding b it in the SCSI Control Ze ro (SCNTL0) registe r is c ...

  • LSI LSI53C875A - page 217

    I/O Ins tr uc tio n 5- 17 the LSI53 C875A to Initi ator mode if it is res elected , or to T arget mod e if it is selecte d. If the S elect with SA TN/ fiel d is set, the SA T N/ signal is asse r ted duri ng the s elect ion ph ase. W ait D isconnect Instruction The LSI53 C875A waits for th e T a rget to perform a “ legal” discon nect fr om the S ...

  • LSI LSI53C875A - page 218

    5-18 SCSI SCRIPTS Instruction Set RA Rela tive Addressing Mode 26 When this bit is set , the 24-bit signed value in the DMA Ne xt Addres s (DNAD) r egister is us ed as a relative disp lacement fro m the current DMA SCRI PTS P ointe r (DSP) address. Use this bit only in conju nctio n with the Selec t, Res elect , W ai t Select , and Wait Rese lect i ...

  • LSI LSI53C875A - page 219

    I/O Ins tr uc tio n 5- 19 Use this b it only in con junc tion with the S elect , Rese lect, W ai t Selec t, and Wait Reselec t instr uct ions. Use bits 25 and 26 individ ually or in = co mbinat ion to produce the f o llowin g cond itions: Direct Uses the de vice ID and physical add ress i n the instr u ction . T able Indirect Uses the ph ysical jum ...

  • LSI LSI53C875A - page 220

    5-20 SCSI SCRIPTS Instruction Set T able Rel ative T reats the al ter nate ju mp addres s as a rel ativ e jum p and f e tches the device ID , synchron ous offse t, and synchr onous p er iod indi rectly . The v alue i n bits [23:0] of the firs t f our bytes of th e SCRIP TS instr uctio n is added to the d ata str ucture base addres s to form the fet ...

  • LSI LSI53C875A - page 221

    I/O Ins tr uc tio n 5- 21 R Reser ved [8:7] A C K Set/ Clear SA CK / 6 R Reser ved [5:4] A TN Set/Clear S A TN/ 3 These two bit s are u sed i n conjun ction wi th a Se t or Cle ar instr uct ion to asser t or d easse r t th e corr espon ding SC SI contr ol signa l. Bit 6 contr ols the SCS I SA CK/ si gnal. Bi t 3 control s the SCS I SA TN/ signal . ...

  • LSI LSI53C875A - page 222

    5-22 SCSI SCRIPTS Instruction Set If rela tive or table re lative address ing is used, th is value is a 24- bit sign ed offs et relative to the c urrent DMA SCR IPTS P o inter (D SP) regis ter value. 5.5 Read/Write Instr uctions The R ead/Wr ite ins truc tion supp or ts addit ion, subtra ction, and compa ris on of two sepa rate v alues within th e ...

  • LSI LSI53C875A - page 223

    Read /Wr it e Instr u ctio ns 5- 23 A[6:0] Register Address - A[6:0] [22: 16] It is poss ible to change re gister values from S CRIPTS in read-m odify-wr ite cy cles or move to/from SF BR cycle s. A[6:0] se lects an 8-bit so urce /destinati on registe r within the LSI53C 875A. ImmD Immediate Data [15:8] This 8 -bit value is used a s a se cond opera ...

  • LSI LSI53C875A - page 224

    5-24 SCSI SCRIPTS Instruction Set 5.5.4 M o ve T o/From SFBR Cyc les All opera tions ar e read-modi fy-wr ites. Howe ver , two regis ters are inv o lved, one o f whic h is al wa ys th e SFBR . Ta b l e 5 . 3 sho ws the possi bl e read-m odify-wr ite o peration s. The poss ible function s of this instr uction are: • Wri te one b yte (value contain ...

  • LSI LSI53C875A - page 225

    T rans fer C ontrol Ins tructions 5-25 Misce llaneo us Notes: • Substi tute the desired reg ister nam e or address for “ R egA” i n the syntax e xamples . • dat a8 in dic ate s eigh t bi ts of dat a. • Use SFBR instead o f data8 t o add tw o register v alues. 5.6 T ransfer C ontr ol Instructions This sec tion desc ri bes the T ransfer Con ...

  • LSI LSI53C875A - page 226

    5-26 SCSI SCRIPTS Instruction Set 5.6.1 F irst Dw or d IT[1:0] Instruct ion T ype - T ransfer Contr ol Instruc tion [31: 30] The IT bit con figuration (10) de fines the T ransfer Control Inst ruction T ype. OPC[2:0] Op Code [29:27] This 3 -bit f ield spec ifies t he type of T ransfer Contr ol Instr uction t o e x ecute. All T ran sf er Contr ol Ins ...

  • LSI LSI53C875A - page 227

    T rans fer C ontrol Ins tructions 5-27 DMA SCRIPTS P ointe r Sav e (DSPS) regis ter . T he DSP registe r now contains th e address of the ne xt inst ruct ion. If the compar iso ns are f alse, the LSI 53C875A fetches t he ne xt in stru ction from the addr ess pointe d to by the DMA SCR IPTS P o inter (D SP) regis ter , leaving the ins tructi on poin ...

  • LSI LSI53C875A - page 228

    5-28 SCSI SCRIPTS Instruction Set If the compar iso ns are f alse, the LSI 53C875A fetches t he ne xt inst ruc tion from the add ress poi nted to by the DSP registe r and the instr ucti on pointer is not m odifie d. Interrupt I nstruction The LSI5 3C875A ca n do a tr ue/false co mpar ison of th e ALU c arr y bit , or comp are the ph ase an d/or dat ...

  • LSI LSI53C875A - page 229

    T rans fer C ontrol Ins tructions 5-29 RA Rela tive Addressing Mode 23 When this bit is set , the 24-bit signed value in the DMA SCR IPTS P o inter Sav e (D SPS) regi ster is used a s a relative offset fr om the current DMA SCRIPT S P ointer (DSP ) address ( which is poi nting to the next instr uction, not the o ne current ly ex ec uting). The rela ...

  • LSI LSI53C875A - page 230

    5-30 SCSI SCRIPTS Instruction Set sign ed (2’ s compleme nt), the jump can be f orward or backward. A relati v e transfer can be to any address wi thin a 16 Mbyte segment. The program counte r is combined with the 24-b it signed offset (usi ng addition or subtracti on) to f o r m the new e x ecuti on address. SCRIPTS programs may contain a mixtur ...

  • LSI LSI53C875A - page 231

    T rans fer C ontrol Ins tructions 5-31 CD Compare Data 18 When t his bit i s set, the fi rst byte recei v ed from the S CSI data bus (contained in the SCSI First Byt e Receiv ed (SFBR) register) is compar ed with the Data to be Compared Field i n the T ransfer Control instr uction. The W ai t for V ali d Pha se bit control s when this c ompare occu ...

  • LSI LSI53C875A - page 232

    5-32 SCSI SCRIPTS Instruction Set DCV Data Compare V alue [7:0] This 8-bit f ield is the data comp ared aga inst the regi ster . These bits are use d in conjunction with the D ata Compare M ask Fiel d to test for a par ticular da ta value. 5.6.2 S econd Dw or d J ump A dd ress [31: 0] This 32- bit field con tains the add ress of the next instr uct ...

  • LSI LSI53C875A - page 233

    Memo r y Mov e Ins tr uctio ns 5-33 • Indirec t addres ses a re not all ow ed. A b ur st of da ta is f etch ed from the sour ce address, put in to the DMA FIFO and th en writte n out to the desti nation address. T he mov e conti nues until t he byte count decreme nts to zero , t hen anoth er SCRIPTS i s f etched fr om syste m memor y . The DMA SC ...

  • LSI LSI53C875A - page 234

    5-34 SCSI SCRIPTS Instruction Set 5.7.2 Rea d/Wr ite Sy stem Memo ry f rom SCRIPTS By usin g the Me mor y M ov e instr uction, single o r multip le regis ter values are transferred to or f rom syste m memor y . Beca use the LSI53 C875A r esponds to a ddresse s as define d in the Base Addres s Regist er Zero (I/O ) or Base Ad dres s Regis ter One (M ...

  • LSI LSI53C875A - page 235

    Load and Store Instructio ns 5-35 5.7.4 Third Dw or d TEMP Re gister [31:0] These b its cont ain the destinati on addres s for the Memor y M ov e. 5.8 Lo ad and Store Instructions The Load and Stor e instr uction s pr ovide a more efficien t w ay to mov e data fro m/to memor y to/fr om an inter nal regi ster in the chip wi thout us ing the nor ma l ...

  • LSI LSI53C875A - page 236

    5-36 SCSI SCRIPTS Instruction Set The SIOM and DIOM bits in th e DMA Mode ( DMODE) regi ster deter mine whether the de stinat ion or sourc e address of th e instr uction i s in Memor y spac e or I/O s pace, as il lustra ted in th e f ollowing table. The Load a nd Store util izes the PCI comman ds f or I/O read and I/ O write to acc ess the I/O spac ...

  • LSI LSI53C875A - page 237

    Load and Store Instructio ns 5-37 Note: This b it has no e ff ect unl ess the P ref etch En ab le bit in the DMA Contr ol (DCNTL) re giste r is se t. LS Load and Store 2 4 When t his bit i s set, the instr u ction is a Load . When clea red, it is a Store. R Reser ved 23 RA[6:0] Register Addr ess [22:16] A[6:0] selec ts the re gister to Load a nd St ...

  • LSI LSI53C875A - page 238

    5-38 SCSI SCRIPTS Instruction Set ...

  • LSI LSI53C875A - page 239

    LSI53C8 75A PCI to Ultra SCSI Controll er 6-1 Chapter 6 Electrical Specific ations This s ection s pecifie s the LS I53C87 5A electr ic al and mec hanic al character is tics. It is di vided i nto the following se ctions: • Secti on 6 .1, “ DC Ch aract er isti cs” • Secti on 6.2, “T oler ANT T ec hnology Electr ica l Character ist ics” ? ...

  • LSI LSI53C875A - page 240

    6-2 Elect ri cal Spe cif icati ons T able 6.1 Absolute M aximum Stress R atings 1 1. Stress es be yond thos e listed abo v e ma y cause permanent damag e to the de vice . These are st ress rat ings on ly; funct ional oper ation of the de vice at these or a ny othe r condi tions be yon d those i n d i c a t e di nt h e Oper ating C onditions se ctio ...

  • LSI LSI53C875A - page 241

    DC Characteristi cs 6-3 T able 6.4 Bidirectional Signals—MAD [7:0], MAS/[1:0], M CE/, MOE/, MWE/ Symbol P arameter Min Max Unit T est Conditions V IH Input h igh v oltage 2.0 5.25 V – V IL Input lo w v oltage V SS − 0.5 0.8 V – V OH Output high v oltage 2.4 V DD V − 4m A V OL Output low v oltage V SS 0.4 V 4 mA I OZ 3-sta te leakage − 1 ...

  • LSI LSI53C875A - page 242

    6-4 Elect ri cal Spe cif icati ons T able 6.6 Bidir ectional Signals—AD[31:0 ], C_BE[3:0]/, FRAME/, I RD Y/, TRD Y/, D E V S E L / ,S T O P / ,P E R R / ,P A R Symb ol Pa rameter Min Max Unit T est Conditions V IH Input high v oltage 0.5 V DD 5.25 V – V IL In put low volt age V SS 0.3 V DD V– V OH Output high v oltage 0.9 V DD V DD V − 16 m ...

  • LSI LSI53C875A - page 243

    T olerANT T echn olog y Electrical Char acteristic s 6 -5 6.2 T olerANT T echnolog y Elect rical Characteristi cs The LSI5 3C875 A features T o lerANT techno log y , which in clude s active negati on on th e SCSI d rivers and input s ignal fi lter ing on the SCS I rece iv ers. Active nega tion ac tively drives th e SCSI R equest , Ackno wled ge, Da ...

  • LSI LSI53C875A - page 244

    6-6 Elect ri cal Spe cif icati ons T able 6.11 T oler ANT T echnology Elect rical Ch aracteri stics for SE S CSI Sign als Symbo l P arameter Min 1 1. Thes e va lues are gu aran teed b y periodic char acterizat ion; the y are not 100% tested on e v er y device. Max Uni t T e st Con dit ions V OH 2 2. Activ e negation out puts on ly: Data, P arity , ...

  • LSI LSI53C875A - page 245

    T olerANT T echn olog y Electrical Char acteristic s 6 -7 Figure 6.1 Rise a nd F a ll Time T e st Condition Figure 6.2 SCSI Input Filter ing Figure 6 .3 Hyste resis o f SC SI Receivers + − 2.5 V 47 Ω 20 pF REQ/ or SA CK/ Input t 1 V TH Note: t 1 is the input filtering period. 1 0 Received Logic Le vel Input V oltage (V olts) 1.1 1.3 1.5 1.7 ...

  • LSI LSI53C875A - page 246

    6-8 Elect ri cal Spe cif icati ons Figure 6.4 Input Current a s a Function of Input V olta ge Figure 6.5 Output Current as a Function of Output V oltage +40 +20 0 − 20 − 40 − 4 0 4 8 12 16 − 0.7 V 8.2 V HIGH-Z OUTPUT AC T I V E Input V oltage (V olts) Input Current (milliAmperes) 14.4 V Output Sink Current (milliAmperes) 0 − 200 − 400 ? ...

  • LSI LSI53C875A - page 247

    A C Char acteristi cs 6-9 6.3 A C Character istics The AC character istics d escr ibed in this sec tion appl y ov er the e ntire range of ope rating cond itions (refer to the DC Character istics se ction ). Chip tim ings are ba sed on s imulatio n at worst ca se voltage, temperature, and proces sing. Timi ng was de veloped with a load c apacitanc e ...

  • LSI LSI53C875A - page 248

    6-10 Electrical Sp ecificat ions Ta b l e 6 . 1 3 and F igure 6.7 provide Reset I nput tim ing da ta. Figure 6.7 Reset Input Ta b l e 6 . 1 4 and F igure 6.8 pro vide Interr upt Out put timi ng data. T able 6.13 Reset Input Symb ol P arame ter Min Max Unit t 1 Reset pu lse width 10 – t CLK t 2 Reset d easse r ted setup t o CLK HIGH 0 – ns t 3 M ...

  • LSI LSI53C875A - page 249

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-11 Figure 6.8 Interrupt Output 6.4 PCI and External Memor y Interface Timi ng Diagrams Figure 6.9 throu gh Figure 6.32 represent signal a ctiv ity whe n the LSI53C 875A a ccesse s the PCI bus. This s ection i ncludes timin g diagrams for access to thr ee groups of m emor y c onfigurati ons. ...

  • LSI LSI53C875A - page 250

    6-12 Electrical Sp ecificat ions – Burst Read, 32-Bit A ddress an d Data – Burst Read, 64-Bit A ddress an d Data – Burst Write , 32-Bi t Addr ess a nd Data – Burst Write , 64-Bi t Addr ess and 3 2-Bit D ata • Ext ernal Memo ry T imi ng – Exter nal Memor y Rea d – Exter nal Mem or y Wr ite – Nor mal/F ast M emor y ( ≥ 128 K bytes) ...

  • LSI LSI53C875A - page 251

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-13 6.4. 1 T arget Timing The t ables and figur es in th is sect ion des cr ibe tar get timin gs. Figure 6.9 PCI Configuration Register Read T able 6.15 PCI Configuration Register Re ad Symb ol P arame ter Min M ax Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input h ...

  • LSI LSI53C875A - page 252

    6-14 Electrical Sp ecificat ions Figure 6.10 PCI Conf iguration Register Write T able 6.16 PCI Configuration Regis ter Write Symb ol P arame ter Min M ax Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 CLK to shared signa l output v alid – 11 ns CLK (Driven by System) FRAME/ (Dr iv en by M aster ...

  • LSI LSI53C875A - page 253

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-15 Figure 6.11 32-Bit Operating Register/SCRIPTS RAM Read T able 6.17 32-Bit Operating Register/SCRIPTS RA M Read Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 CLK to shared signa l output v alid – 1 1 ns CLK ...

  • LSI LSI53C875A - page 254

    6-16 Electrical Sp ecificat ions Figure 6 .12 64-Bit Address Operating Register /SCRIPTS RAM Read T able 6.18 64-Bit Addr ess Operat ing Reg ister/SCRI PTS RAM Read Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 CLK to shared signa l output v alid – 11 ns CLK (Driv e ...

  • LSI LSI53C875A - page 255

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-17 Figure 6.13 32-Bit Ope rating Re gister/SCRIPTS RA M Write T able 6.19 32-Bit Operating Regis ter/SCRIPTS RA M Write Symb ol P arame ter Min M ax Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 CLK to shared signa l output v alid – 11 ...

  • LSI LSI53C875A - page 256

    6-18 Electrical Sp ecificat ions Figure 6 .14 64-Bit Address Operating Register /SCRIPTS RAM Write T able 6.20 64-Bit Addr ess Ope rating Re gister/SCRI PTS RAM Write Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 CLK to shared signa l output v alid – 11 ns Bus Addr ...

  • LSI LSI53C875A - page 257

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-19 6.4.2 Initiator Timing The t ables and figures in th is sect ion des cr ibe LS I53C875 A initiat or timin gs. T able 6.21 Nonbur st Opcode Fe tc h, 32-Bit Address and Data Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 ...

  • LSI LSI53C875A - page 258

    6-20 Electrical Sp ecificat ions Figure 6.15 Nonbur st Opcode Fetch, 32-Bit Address and D ata CLK (Driven by System) FRAME/ (Dr iv en b y LSI53C8 75A) AD (Dr iv en b y LSI53C8 75A- C_BE/ (Dr iv en b y LSI53C8 75A) PA R (Dr iv en b y LSI53C8 75A- IRD Y/ (Dr iv en b y LSI53C8 75A) TRD Y/ (Driv en by T arg et) ST OP/ (Driven by T arget ) DEVS EL/ (Dri ...

  • LSI LSI53C875A - page 259

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-21 T able 6.22 Burst Opco de Fetch, 32-Bi t Address and Data Symb ol P arame ter Min Max Unit t 1 Shar ed si gnal in put se tup ti me 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 CLK to shared signa l output v alid 2 11 ns t 4 Side sign al input setup time 10 – ns t 5 Side si g ...

  • LSI LSI53C875A - page 260

    6-22 Electrical Sp ecificat ions Figure 6.16 Burst Opcode Fetch, 32-Bit Address a nd D ata CLK (Driven by System) FRAME/ (Dr iv en b y LSI53C8 75A) AD (Dr iv en b y LSI53C8 75A- C_BE/ (Dr iv en b y LSI53C8 75A) PA R (Dr iv en b y LSI53C8 75A- IRD Y/ (Dr iv en b y LSI53C8 75A) TRD Y/ (Driv en by T arg et) ST OP/ (Driven by T arget ) DEVS EL/ (Driv e ...

  • LSI LSI53C875A - page 261

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-23 T able 6.23 Back-to-Back Read, 32-Bit Address and Data Symbol P arameter Min Max Unit t 1 Shar ed s ign al inp ut set up tim e 7 – ns t 2 Shar ed s ign al inp ut hol d time 0 – ns t 3 CLK to shared signa l output v alid 2 11 ns t 4 Side signal inp ut setup time 10 – ns t 5 Side si g ...

  • LSI LSI53C875A - page 262

    6-24 Electrical Sp ecificat ions Figure 6.17 Back-to-Back Read, 32-Bit Address and Data CLK (Dr iv en by Syst em) FRAM E/ (Dr iven by LSI53C8 75A) AD (Dr iven by LSI53C8 75A- C_BE/ (Dr iven by LSI53C8 75A) PA R (Dr iven by LSI53C8 75A- IRD Y/ (Dr iven by LSI53C8 75A) TRD Y/ (Driven by T arget ) ST OP/ (Dri v e n by T arget) DEVS EL/ (Driven by T ar ...

  • LSI LSI53C875A - page 263

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-25 T a ble 6 .24 Ba ck -to -B ac k Writ e, 32- Bit Ad dr ess an d Data Symb ol P arame ter M in Max Un it t 1 Shar ed si gnal in put se tup ti me 7 – ns t 2 Shared sig nal input hold time 0 – n s t 3 CLK to s har ed s ignal o utpu t valid 2 11 ns t 4 Side sign al input setup time 10 – ...

  • LSI LSI53C875A - page 264

    6-26 Electrical Sp ecificat ions Fig ure 6. 18 Bac k-t o-B ac k W rite, 32-Bi t Add re ss and Dat a CLK (Driven by System) FRAME/ (Dr iv en b y LSI53C8 75A) AD (Dr iv en b y LSI53C8 75A- C_BE/ (Dr iv en b y LSI53C8 75A) PA R (Dr iv en b y LSI53C8 75A- IRD Y/ (Dr iv en b y LSI53C8 75A) TRD Y/ (Driv en by T arg et) ST OP/ (Driven by T arget ) DEVS EL ...

  • LSI LSI53C875A - page 265

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-27 T able 6.25 Burst Read, 32 -Bit A ddress and Da ta Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 CLK to shared signa l output v alid 2 11 ns ...

  • LSI LSI53C875A - page 266

    6-28 Electrical Sp ecificat ions Figure 6.19 Burst Read, 32-Bit Address and Data t 1 t 2 CLK GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_M ASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PA R (Driven by LSI53C875A- IRD Y/ (Driven by LSI53C875A) TRD Y/ (Dr iv en b y T arget) ST OP/ (Dr iv en b y T arget) DEVSEL/ (Dr iv en b y T arget) AD (Dr ...

  • LSI LSI53C875A - page 267

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-29 T able 6.26 Burst Read, 64 -Bit A ddress and Da ta Symb ol P arame ter M in Max Un it t 1 Shar ed si gnal in put se tup ti me 7 – ns t 2 Shared sig nal input hold time 0 – n s t 3 CLK to s har ed s ignal o utpu t valid 2 11 ns t 10 CLK HIGH to GPIO1_MASTER/HIGH – 20 ns ...

  • LSI LSI53C875A - page 268

    6-30 Electrical Sp ecificat ions Figure 6.20 Burst Read, 64-Bit Address and Data t 1 t 2 CLK GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_M ASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PA R (Addr dr vn b y LS I53C875A; IRD Y/ (Driven by LSI53C875A) TRD Y/ (Driven by T arget) ST OP/ (Driven by T arget) DEVSE L/ (Driven by T arget) AD[31:0] ...

  • LSI LSI53C875A - page 269

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-31 T able 6.27 Bur st Write , 32-Bit Address and Data Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 CLK to shared signa l output v alid 2 11 ns t 10 CLK HIGH to GPIO1_MASTER/ HIGH – 20 ns ...

  • LSI LSI53C875A - page 270

    6-32 Electrical Sp ecificat ions Figure 6.21 Burst Write, 32-Bit Addr ess and Data t 1 CLK (Dr iv en by Syst em) GPIO0_FET CH/ (Driven by LSI53C875A) GPIO 1_MASTER / (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PA R (Driven by LSI53C875A) IRD Y/ (Driven by LSI53C875A) TRD Y/ (Driven by T arget ) ST OP/ (Driven by T arget ) DEVS EL/ (Driven by ...

  • LSI LSI53C875A - page 271

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-33 T a ble 6 .28 Bur st Wri te, 64- Bit A ddr ess and 32- Bit D ata Symb ol P arame ter M in Max Un it t 1 Shar ed si gnal in put se tup ti me 7 – ns t 2 Shared sig nal input hold time 0 – n s t 3 CLK to s har ed s ignal o utpu t valid 2 11 ns t 10 CLK HIGH to GPIO1_MASTER/ HIGH – 20 n ...

  • LSI LSI53C875A - page 272

    6-34 Electrical Sp ecificat ions Figure 6.22 Burst Write, 64-Bit Addr ess and 32-Bit Data t 1 CLK (Dri v en b y Syst em) GPIO0_F ETCH/ (Driven by LSI53C875A) GPIO1_M ASTER/ (Driven by LSI53C875A) REQ / (Driven by LSI53C875A) PA R (Driven by LSI53C875A) IRD Y/ (Driven by LSI53C875A) TRD Y/ (Dr iv en by T arget) STOP/ (Dr iv en by T arget) DEVS EL/ ( ...

  • LSI LSI53C875A - page 273

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-35 6.4. 3 External M emory Timing The tables an d figures in th is sect ion des cr ibe LSI 53C875 A e xter na l timin gs. The Ext er nal Me mor y W rit e timin gs st ar t o n page 6 -40 . T a ble 6 .29 Ext ern al Mem ory Read Symbol P a ramete r Min Max Unit t 1 Share d signal input setup ti ...

  • LSI LSI53C875A - page 274

    6-36 Electrical Sp ecificat ions Figure 6.23 External M emory Read 12 3 4 5 6 7 8 9 CLK (Driven by System) PA R (Dr iv en by Master-Addr ; IRD Y/ (Driven by Master) TRD Y/ (Driven by LSI53C875A) ST OP/ (Driven by LSI53C875A) DEVS EL/ (Driven by LSI53C875A) AD (Dr iv en by Master-Addr ; C_B E[ 3:0 ]/ (Driven by Master) FRAM E/ (Driven by Master) LSI ...

  • LSI LSI53C875A - page 275

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-37 Figure 6.23 External Me mory Read (Cont.) MAD (Addr dr iv en by LSI53C875A; Data driven by Memor y) 11 12 13 14 15 16 17 18 19 20 21 10 CLK (Dr iv en by Syst em) PA R (Driven by Master-Addr ; IRD Y/ (Dri v en b y Mast er) TRD Y/ (Driven by LSI53C875A) ST OP/ (Driven by LSI53C875A) DEVS EL ...

  • LSI LSI53C875A - page 276

    6-38 Electrical Sp ecificat ions T a ble 6 .30 Ext erna l Memo ry Write Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 CLK to shared signa l output v alid – 11 ns t 11 Address s etup to MAS/ H IGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse w ...

  • LSI LSI53C875A - page 277

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-39 The Ex ter nal Memor y Wr ite timi ngs star t on pa ge 6-40 . ...

  • LSI LSI53C875A - page 278

    6-40 Electrical Sp ecificat ions Figure 6.24 External M emory Write 12 3 4 5 6 78 9 CLK (Driven by System) PA R (Dr iv en by Master-Addr ; IRD Y/ (Driven by Master) TRD Y/ (Driven by LSI53C875A) ST OP/ (Driven by LSI53C875A) DEVS EL/ (Driven by LSI53C875A) AD (Dr iv en by Master-Addr ; C_B E[ 3:0 ]/ (Driven by Master) FRAM E/ (Driven by Master) LSI ...

  • LSI LSI53C875A - page 279

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-41 Figure 6.24 External M emory Write (Cont.) MAD (Addr dr iv en by LSI53C875A; Data driven by Memor y) 11 12 13 14 15 16 17 18 19 20 21 10 CLK (Dr iv en by Syst em) PA R (Driven by Master-Addr ; IRD Y/ (Dri v en b y Mast er) TRD Y/ (Driven by LSI53C875A) ST OP/ (Driven by LSI53C875A) DEVS E ...

  • LSI LSI53C875A - page 280

    6-42 Electrical Sp ecificat ions Figure 6.25 Normal/Fast Memory ( ≥ = 128 K b ytes) S ingle By te Access Read Cycle T able 6.31 Normal/Fast Memory ( ≥ = 128 Kbytes) Sin gle Byte A ccess Read Cycle Symb ol P arame ter Min Max Unit t 11 Address s etup to MAS/ H IGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse w idth 25 – ...

  • LSI LSI53C875A - page 281

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-43 Figure 6.26 Normal/Fast Memory ( ≥ = 128 K b ytes) S ingle By te Access Writ e Cycle T able 6.32 Normal/Fast Memory ( ≥ = 128 Kbytes) Sin gle Byte Access Write Cycle Symb ol P arame ter Min Max Unit t 11 Address s etup to MAS/ H IGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns ...

  • LSI LSI53C875A - page 282

    6-44 Electrical Sp ecificat ions Figure 6.27 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access R ead Cycle MAD (Addr D riven by LSI53C87 5A; MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A) MWE/ (Driven by LSI53C875A) 02 4 6 8 1 01 2 1 4 1 6 1 7 Data dr iv en by Memor y) CL ...

  • LSI LSI53C875A - page 283

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-45 Figure 6.27 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access R ead Cycle (Cont.) MAD (Addr D riven by LSI53C87 5A ; MAS1 / (Dr iv en b y LSI53C8 75A) MAS0 / (Dr iv en b y LSI53C8 75A) MCE/ (Dr iv en b y LSI53C8 75A) MOE/ (Dr iv en b y LSI53C8 75A) MWE/ (Dr iv en b y LSI53C8 75 ...

  • LSI LSI53C875A - page 284

    6-46 Electrical Sp ecificat ions Figure 6.28 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access W rite Cycle MAD (Dr iv en b y LSI53C8 75A) MAS1 / (Dr iv en b y LSI53C8 75A) MAS0 / (Dr iv en b y LSI53C8 75A) MCE/ (Dr iv en b y LSI53C8 75A) MOE/ (Dr iv en b y LSI53C8 75A) MWE/ (Dr iv en b y LSI53C8 75A) 02 4 6 8 1 0 1 2 1 4 CLK (Driven by ...

  • LSI LSI53C875A - page 285

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-47 Figure 6.28 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access W rite Cycle (Cont.) MAD (Driven by LSI53C875A; MAS1 / (Dr iv en b y LSI53C8 75A) MAS0 / (Dr iv en b y LSI53C8 75A) MCE/ (Dr iv en b y LSI53C8 75A) MOE/ (Dr iv en b y LSI53C8 75A) MWE/ (Dr iv en b y LSI53C8 75A) 15 1 ...

  • LSI LSI53C875A - page 286

    6-48 Electrical Sp ecificat ions Figure 6.29 Slow Me mory ( ≤ = 128 Kbytes) Read Cycle T able 6.33 Slo w Mem ory ( ≤ = 128 Kbytes) Read C ycle Symb ol P arame ter Min Max Unit t 11 Address s etup to MAS/ H IGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse w idth 25 – ns t 14 MCE/ LO W to data c loc ked in 150 – ns t 1 ...

  • LSI LSI53C875A - page 287

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-49 Figure 6.30 Slow Me mory ( ≤ = 128 Kb yt es) Wri te Cyc le T able 6.34 Slo w Mem ory ( ≤ 128 Kb ytes) W rite C yc le Symb ol P arame ter Min Max Unit t 11 Address s etup to MAS/ H IGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse w idth 25 – ns t 20 Data se tu ...

  • LSI LSI53C875A - page 288

    6-50 Electrical Sp ecificat ions Figure 6.31 ≤ 64 Kbytes ROM Re ad Cycle Ta b l e 6 . 3 5 ≤ = 64 Kbytes ROM Read Cycle Symb ol P arame ter Min Max Unit t 11 Address s etup to MAS/ H IGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse w idth 25 – ns t 14 MCE/ LO W to data c loc ked in 150 – ns t 15 Addres s vali d to dat ...

  • LSI LSI53C875A - page 289

    PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-51 Figure 6.32 ≤ 64 Kbyte ROM Write C ycle Ta b l e 6 . 3 6 ≤ = 64 Kbyte ROM Writ e Cycle Symb ol P arame ter Min Max Unit t 11 Address s etup to MAS/ H IGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse w idth 25 – ns t 20 Data se tup to MWE / LO W 30 – ns t 21 ...

  • LSI LSI53C875A - page 290

    6-52 Electrical Sp ecificat ions 6.5 S CSI T iming Diagrams The tables and diagrams in this secti on descr ibe the LS I53C875A SC SI timin gs. Figure 6.33 Initiator Asynchronous Send T able 6.37 Initiator Asynchr onous Send Symb ol P arame ter Min Max Unit t 1 SA CK/ ass er ted from SR EQ/ asse r ted 5 – ns t 2 SA CK/ deas ser ted from SREQ/ deas ...

  • LSI LSI53C875A - page 291

    SCSI Timing Diagr ams 6-53 Figure 6.34 Initiator As ynchr onous Receive T able 6.38 Initiator Asynchronous Receive Symb ol P arame ter Min Max Unit t 1 SA CK/ ass er ted from SRE Q/ asse r ted 5 – ns t 2 SA CK/ deas ser ted from SREQ/ deass er ted 5 – ns t 3 Data se tup to SREQ/ as ser ted 0 – ns t 4 Data hold from SA CK/ asser ted 0 – ns S ...

  • LSI LSI53C875A - page 292

    6-54 Electrical Sp ecificat ions Figure 6.35 T arget Asynchr onous Send T ab le 6.39 T ar get Asynchr onous Send Symb ol P arame ter Min Max Unit t 1 SREQ/ dea sser ted from SA CK/ asse r ted 5 – ns t 2 SREQ/ asse r ted from SA CK/ deasserted 5 – ns t 3 Data se tup to SR EQ/ as ser ted 55 – ns t 4 Data hold from SA CK/ asser ted 0 – ns SREQ ...

  • LSI LSI53C875A - page 293

    SCSI Timing Diagr ams 6-55 Figure 6.36 T arget Asynchr onous Re ceive T able 6.40 T arget Asynchr onous Receive Symb ol P arame ter Min Max Unit t 1 SREQ/ dea sser ted from SA CK/ asse r ted 5 – ns t 2 SREQ/ asser ted from SACK/ de asserted 5 – ns t 3 Dat a setu p to SACK/ asser ted 0 – ns t 4 Data hold from SREQ / deasserted 0 – ns T able ...

  • LSI LSI53C875A - page 294

    6-56 Electrical Sp ecificat ions T able 6.42 SCSI-2 Fast T r ansfers 10.0 Mbytes (8-Bi t T rans f ers) or 2 0.0 Mbytes (16-Bit T ransfers) 40 MHz Cloc k Symb ol P arame ter Min Max Unit t 1 Send SREQ/ or SAC K/ asser tion pul se width 30 – ns t 2 Send SREQ/ or SA CK/ deassertion pulse wi dth 30 – ns t 1 Receive SREQ/ or SA CK/ a sser tion puls ...

  • LSI LSI53C875A - page 295

    SCSI Timing Diagr ams 6-57 Figure 6.37 Initiator a nd T arget Synchronou s T ransfer SREQ/ or SACK/ Send Data SD[15:0]/, SDP[1:0]/ Receiv e Data SD[15:0]/, SDP[1:0]/ t 3 t 4 t 1 t 2 t 5 t 6 nn + 1 V alid n V alid n + 1 V alid n V alid n + 1 ...

  • LSI LSI53C875A - page 296

    6-58 Electrical Sp ecificat ions 6.6 P ac kage Dia grams This s ection o f the manual has a packag e drawing and pino ut for both the PQFP and BGA . Figure 6 .38 LSI5 3C875A 160-Pin PQFP Mechanical Dra wing Important: This drawing may not be the latest version. For board lay out and m anufacturing, obtain the most recent eng ineering drawings fr om ...

  • LSI LSI53C875A - page 297

    P ackage D iagra ms 6- 59 Figure 6.38 160-pin PQ FP (P3) Mechanic al Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board lay out and m anufacturing, obtain the most recent eng ineering drawings fr om your LSI L ogic marketing representati ve by requesting the outline d rawing f o r packa ge code P 3. ...

  • LSI LSI53C875A - page 298

    6-60 Electrical Sp ecificat ions T able 6.44 160 P QFP Pin List b y Location NC 121 NC 122 VSSIO 123 NC 124 NC 125 TE ST_H SC / 126 TE ST_R ST/ 1 27 VDDIO 128 VDD A 129 TCK 130 TRST/ 131 VSSA 132 VSSIO 133 NC 134 NC 135 MASN[1]/ 136 MASN[0]/ 137 VDDIO 138 MEW/ 13 9 MOE/ 14 0 MCE/ 14 1 TDI 142 SERR/ 143 RST/ 144 CLK 145 VSSCORE 146 GNT / 147 REQ/ 14 ...

  • LSI LSI53C875A - page 299

    P ackage D iagra ms 6- 61 Figure 6.39 169-Pin BGA Mechanical Drawing Important: This drawing may not be the latest version. For board lay out and m anufacturing, obtain the most recent eng ineering drawings fr om your LSI L ogic marketing representati ve by requesting the outline d rawing f o r packa ge code G V . ...

  • LSI LSI53C875A - page 300

    6-62 Electrical Sp ecificat ions T able 6.4 5 169 BGA Pin List by L oc ation VSSIO K12 SIO K13 PCI_AD[9] L1 PCI_AD[8] L2 PCI_AD[4] L3 PCI_AD[2] L4 VDDCORE L5 VSSCORE L6 MAD[ 7] L7 MAD[ 1] L8 GPIO[4] L9 MA C_TEST OUT/ L10 VDDIO L11 VDDCORE L12 SD[10] L13 PCI_AD[7] M1 NC M2 PCI_AD[5] M3 NC M4 IRQ/ M5 SCLK M6 MAD[ 6] M7 MAD[ 3] M8 GPIO[3] M9 VDDIO M10 ...

  • LSI LSI53C875A - page 301

    LSI53C8 75A PCI to Ultra SCSI Controller A-1 Appendix A Regi ster S ummar y T able A.1 LSI53C875A PCI Re gister Map Register Nam e Address Read /Write P age Base Addres s Regis ter One (ME MOR Y) 0x14–0 x17 Read /Write 4-9 Base Address Regis ter T wo (SCRIPTS RAM) 0x1 8–0x1B Read/Write 4 -10 Base Addres s Regis ter Zero (I /O) 0x10–0 x13 Read ...

  • LSI LSI53C875A - page 302

    A-2 Register Summ ar y P ow er Manage ment Capabi lities (PM C) 0x4 2–0x4 3 Read Only 4- 15 P ow er Manage ment Con trol/Stat us (PMCSR) 0x44–0 x45 Read /Write 4-16 Reser ved 0x28 –0x 2B – 4-10 Reser ved 0x35 –0x 3B – 4-13 Revision I D (Rev ID) 0x 08 R ead O nly 4-6 Status 0x06–0 x07 Read/Write 4-5 Subsyste m ID 0x2 E–0x2F Read Only ...

  • LSI LSI53C875A - page 303

    Regis ter Summary A-3 DMA C omma nd (DC MD) 0x 27 Read/ Wr ite 4- 63 DMA Control (DCNTL) 0x3B Read/Write 4 -70 DMA FIFO (DFIFO) 0x20 Read/Write 4-57 DMA Interrupt Enab le (DIEN) 0x39 Read/Write 4-69 DMA Mod e (DMODE) 0x38 Read/Write 4-66 DMA Ne xt Address (DN AD) 0x28–0 x2B Read/Write 4-64 DMA Ne xt Address 64 (DNAD64) 0xB8–0x BB Read/Write 4-1 ...

  • LSI LSI53C875A - page 304

    A-4 Register Summ ar y Remai ning Byt e Count (RBC ) 0xC8–0x CB Read/Write 4-105 Reser ved 0x53 – 4-94 Reser ved 0x5A –0x5 B – 4-99 Reser ved 0xBC –0x BF – 4-103 Reser ved 0xDB – 4-108 Reser ved 0xE0–0x FF – 4-108 Response ID One (RESPID1) 0x4B Read/Write 4-86 Response ID Zero (RESPID0) 0x4A Read/Write 4-86 Scra tch Byte Registe r ...

  • LSI LSI53C875A - page 305

    Regis ter Summary A-5 SCS I Inte rr upt E nable Zer o (SI EN0) 0x40 Rea d/W rit e 4-73 SCSI Interrupt Stat us One (SIST1) 0x43 Read Only 4-78 SCSI Interrupt Stat us Zero ( SIST0) 0x42 Read Only 4-76 SCSI Longi tudinal P arity (SLP AR) 0x44 Read/Write 4-79 SCSI Output C ontrol Lat ch (SOCL) 0x09 Read/Write 4-37 SCSI Outp ut Data La tch (SODL ) 0x54? ...

  • LSI LSI53C875A - page 306

    A-6 Register Summ ar y ...

  • LSI LSI53C875A - page 307

    LSI53C8 75A PCI to Ultra SCSI Controller B-1 Appendix B External Memory Interface D iagram Examples Appen dix B has e xamp le e x ter nal mem or y inter f a ce diagrams. Figure B.1 16 Kb yte Interf ace with 200 ns Memory LSI53C875A 27C128 MOE/ OE MCE/ CE D0 8 MAD[7:0] Bus CK Q0 8 A[7:0] QE 6 A[13:8] V DD MAS0 / MAS1 / Note: MAD[3:1] pulled LOW inte ...

  • LSI LSI53C875A - page 308

    B-2 External Memor y Interf ace Diagram Ex amples Figure B.2 64 Kb yte Interf ace with 150 ns Memory LSI53C875A 27C512-15/ MOE/ OE MCE/ CE D0 8 MAD[7:0] Bus CK Q0 8 A[7:0] QE 6 A[15:8] V DD MAS0 / MAS1 / Note: MAD 3, 1, 0 pulled LOW internally . MA D b us sense logic enabled f or 64 Kbyte of f ast memor y (150 ns de vices @ 33 MHz). HCT374 GPIO4 MW ...

  • LSI LSI53C875A - page 309

    External Memory Interf ace Diagr am Example s B-3 Figure B.3 128 Kb yte s, 256 Kb y tes, 512 Kbytes, or 1 Mb yte Interface w ith 150 ns Memor y LSI53C875A 27C020-15/ MOE/ OE MCE/ CE 8 MAD[7:0] Bus 8 A[7:0] 6 A[15:8] V DD MAS0/ MAS1/ Note: MAD[2:0] pulled LOW internally . MAD bus sense logic enabled f or 128, 256, 512 Kbytes, or 1 Mbyte of f ast mem ...

  • LSI LSI53C875A - page 310

    B-4 External Memor y Interf ace Diagram Ex amples Figure B .4 512 Kb yte Interface w ith 150 ns Memory OE WE D[7:0] A0 A16 . . . LSI53C875A MOE/ 8 MAD[7:0] Bus A[7:0] D0 CK Q0 QE 8 A[15:8] V DD MAS0/ MAS1/ Note: MAD2 pulled LOW internally . MAD bus sense logic enabled f or 512 Kbytes of slow memory (150 ns de vices, additional time required f or HC ...

  • LSI LSI53C875A - page 311

    LSI53C8 75A PCI to Ultra SCSI Controller IX-1 Inde x Sym bol s (64T IMOD) 4- 97 (A7) 5-23 (AAP) 4-2 2 (ABRT) 4-40 , 4-48 (ACK) 4-37 , 4- 39 (ADB) 4-23 (ADCK) 4-60 (ADDER) 4-73 (AESP) 4-24 (AIP) 4-43 (APS) 4-1 6 (ARB[1: 0]) 4-20 (ART ) 4-87 (ATN ) 4-37 , 4- 39 (AWS ) 4-9 0 (BAR0) 4-9 (BAR1) 4-9 (BAR2) 4-10 (BBCK) 4-6 1 (BDIS ) 4-59 (BF) 4- 40 , 4- 6 ...

  • LSI LSI53C875A - page 312

    IX-2 In de x (ERBA) 4-1 2 (ERL) 4- 67 (ERM P) 4-68 (ESA) 4-1 06 (EWS ) 4-2 9 (EXC) 4-2 3 (EXT) 4-90 (FBL3) 4- 59 (FE) 4- 82 (FF[ 3:0]) 4- 43 (FF4 ) 4-4 6 (FFL ) 4-5 3 (FLF) 4-56 (FLSH ) 4-51 (FM) 4-5 6 (FMT ) 4-5 3 (GEN) 4- 75 , 4-79 (GEN[ 3:0]) 4-8 5 (GENSF) 4- 85 (GPCNTL0) 4-8 2 (GPIO) 4-35 (GPIO[1: 0]) 4-83 (GPIO[4: 2]) 4-83 (GPREG0) 4- 35 (HSC) ...

  • LSI LSI53C875A - page 313

    Inde x IX-3 (SGE) 4-7 4 , 4-77 (SI) 4-51 (SID) 4-1 1 (SIEN0) 4- 73 (SIEN1) 4- 75 (SIGP) 4- 49 , 4-54 (SIOM) 4-67 (SIP) 4-50 (SIR) 4-4 0 (SIST 0) 4-76 (SIST 1) 4-78 (SLB) 4-8 9 (SLPAR) 4-79 (SLPHBEN) 4- 27 (SLPM D) 4-2 7 (SLT) 4-87 (SOCL ) 4-3 7 (SODL ) 4-9 4 (SOM) 4-88 (SOZ) 4-87 (SPL1) 4-47 (SRE) 4-30 (SRS T) 4-48 (SRT M) 4-59 (SRUN) 4-51 (SSAID) ...

  • LSI LSI53C875A - page 314

    IX-4 In de x burst ( Cont.) length ( BL[1:0]) 4- 66 length b it 2 (B L2) 4-61 opcode fet ch enab le (BOF) 4-6 8 size selection 2-6 bus comma nd and byte enables 3- 5 fault (B F) 4-4 0 , 4-69 byte count 5-37 empty in D MA FIF O (FMT) 4-53 full in DMA F IFO (FFL) 4-53 offset co unter (B O) 4-57 C cache line size 2-7 , 2-9 (CLS) 4- 7 enable (C LSE) 4- ...

  • LSI LSI53C875A - page 315

    Inde x IX-5 DMA interru pt (Con t.) pendin g (DI P) 4-50 mode ( DMOD E) 4-66 SCRIPTS pointer ( DSP) 4-64 pointer save (DSPS) 4- 65 status ( DSTAT) 4- 39 DMA next address (DNAD) 4-64 addre ss 64 (DNA D64) 4-103 DMODE 2-6 regist er 2-22 DSA relativ e 5-36 relative select or (DRS) 4-102 DSPS register 5-34 DSTAT 2-38 , 2-42 , 2-43 dual ad dress cycles ...

  • LSI LSI53C875A - page 316

    IX-6 In de x IDSEL 2-3 , 3-6 signal 2- 5 illega l instructio n detec ted (IID) 4-40 , 4-69 immedia te arbitra tion (IARB) 4-2 4 data 5-23 indirect add ressi ng 5-6 initialization device se lect 3-6 initiator mode 5-16 phase m ismatch 4-7 6 ready 3-6 input 3- 3 capacitance 6-2 instruction addre ss (IA) 4- 107 block mov e 5-6 prefet ch unit flu shing ...

  • LSI LSI53C875A - page 317

    Inde x IX-7 memo ry (Cont .) read li ne co mmand 2- 6 read multiple 2- 10 , 2-11 read multiple comm and 2-6 space 2-2 , 2-3 to me mory 2-16 to me mory move s 2-1 6 write 2-10 , 2-11 write and invalidate 2- 10 write and invalidate co mmand 2-8 write caching 2-11 write command 2-5 write enable 3-11 Min_Gn t (MG) 4-1 4 MOE/ 3-1 1 move to/fr om SFBR cy ...

  • LSI LSI53C875A - page 318

    IX-8 In de x reset 3-4 input 6- 10 SCSI offset (ROF) 4-89 response ID one (RESPID1) 4-86 response ID zero (RESPID0) 4-86 return inst ruction 5-27 revision ID (RID) 4- 6 ROM flash and memory interface signals 3-11 pin 2-49 RST/ 3- 4 S SACK 2-42 SACK/ stat us (ACK) 4-3 9 SACs 2-19 SATN/ status ( ATN) 4-39 SBSY/ status (BSY) 4- 39 SC_D/ status (C_D) 4 ...

  • LSI LSI53C875A - page 319

    Inde x IX-9 SEL 2-39 select 2-17 instruction 5-16 with ATN/ 5- 20 with SA TN/ on a sta rt sequ ence (WAT N) 4-22 selected (SEL) 4-7 4 , 4-77 selection or r eselectio n time-o ut (S TO) 4- 75 , 4-79 selection res ponse lo gic tes t (SLT) 4-8 7 selection time-out (SEL [3:0]) 4-8 4 sema pho re (SEM) 4- 49 serial EEP ROM interface 2-50 SERR/ 3-7 SERR/ ...

  • LSI LSI53C875A - page 320

    IX-10 Inde x Ultra SCSI (Cont.) single-e nded tr ansfer s 20.0 M bytes (16-b it tr ansfers ) quadr upled 4 0 MHz clock 6-56 20. 0 Mbyt es (8-b it tran sf ers) 40 MHz clo ck 6-56 sync hronous dat a trans fers 2- 36 unexpected disco nnect (UDC) 4-74 , 4-78 update d address (U A) 4-1 05 upper re gister ad dress li ne (A7) 5- 23 use data8/ SFBR 5- 22 V ...

  • LSI LSI53C875A - page 321

    Customer Fee dbac k W e would appre ciate your f e edback on this document. P lease copy the f o llowing p age, add your c omments, an d f ax it t o us at the number shown. If approp r iate, please a lso f ax c opies o f any marked-u p pages from this document . Impor tant: Pleas e include your name, phone number , f ax number , and compa ny addres ...

  • LSI LSI53C875A - page 322

    Cust omer Feed back Re ader ’ s Comme nts F ax your comment s to: LSI Logic Co r poration T echni cal P ublicatio ns M/S E-198 F ax: 408 .433.43 33 Please tell us how you rate this do cument : LSI53C875 A PCI to Ultra SCSI Co ntrolle r T ech nical M anual. P lace a c hec k m ark in the appr opr iate b lan k for each ca tegor y . W h a tc o u l dw ...

  • LSI LSI53C875A - page 323

    U .S. D is tribut ors by S t at e A. E. A vnet E lectronics http://www .hh.av net.com B. M. Bell Mic ropro ducts, Inc. (for HAB’ s ) http://www .bellmicro.com I. E. Insight Electro nics http://www .insight-electronics .com W . E. Wyle Electronics http://www .wyle.com Alabam a Daphne I. E. T el: 334.6 26.619 0 Huntsville A. E. T el : 256.837 .8700 ...

  • LSI LSI53C875A - page 324

    U .S. D is tribut ors by S t at e (C onti nue d) New Y ork Hauppa uge I. E. T el: 516.7 61.096 0 Long I sland A. E. T el : 516.434 .7400 W . E. T el: 80 0.861.995 3 Rochester A. E. T el : 716.475 .9130 I. E. T el: 716.2 42.779 0 W . E. T el: 80 0.319.995 3 Smithto wn B. M. T el: 80 0.543.200 8 Syrac use A. E. T el : 315.449 .4927 Nort h Carolina Ra ...

  • LSI LSI53C875A - page 325

    Direct S ales Representati ves by State (Component and HAB) E. A. Earle Associate s E. L. Electrody ne - UT GRP Gro up 2000 I. S. Infinity Sa les, Inc. ION ION Associates, Inc. R. A. Rathsbu rg Ass oci- ates, Inc. SGY Syne rgy Associates, Inc. Arizona Te m p e E. A. T el : 480.921 .3305 California Calabasas I. S. T el: 818.8 80.648 0 Irvin e I. S. ...

  • LSI LSI53C875A - page 326

    Sales Office s and De sign Resource Center s LSI Log ic Corpor ati on Corpo rate H eadqua rters 1551 McCarthy Bl vd Milpitas CA 95 035 T el: 40 8.433. 8000 Fax: 408.433.8 989 NORTH AMERICA California Irvin e 18301 V on Karman Av e Suite 900 Irvine, CA 92612 ♦ T el: 94 9.809.460 0 F a x: 949. 809.4444 Pleasa nton Desi gn Cen ter 5050 Hop yard Road ...

  • LSI LSI53C875A - page 327

    Sales Office s and De sign Resource Center s (C onti nue d) Ko re a Seoul LSI Logi c Corpor ation of Ko re a L td 10th Fl., Haesung 1 B ldg. 942, Daechi- dong, Kangnam-k u, Seoul, 135-283 T el: 82.2 .528.3400 F ax: 82.2.52 8.2250 The Ne ther lands Eind hov en LSI Logi c Eur ope Ltd Wo rld T rade Center Eindho ven Building ‘Rijde r’ Bogert 26 56 ...

  • LSI LSI53C875A - page 328

    International Dis tribut ors Au s tr a l i a New South W a les Rept ec hnic Pty Ltd 3/36 By down Stre et Neutr al Bay , NSW 2089 ♦ T el: 612. 9953. 984 4 F a x: 612. 9953.968 3 Belgium Acal n v/sa Loze nberg 4 1932 Z aven tem T el: 32 .2.720598 3 F a x: 32.2.72 51014 China Beijing LSI Lo gic Inte rnation al Serv ices Inc. Beijing Represe ntative ...

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