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Cypress CY7C1312BV18 - page 1
18-Mbit QDR™-II SRAM 2-W ord Burst Architecture CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05619 Rev . *F Revised June 2, 2008 Features ■ Separate independent read and write data ports ❐ Supports concurrent transac ...
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Cypress CY7C1312BV18 - page 2
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 2 of 29 Logic Block Diagram (CY7C1310BV18) Logic Block Diagram (CY7C1910BV18) 1M x 8 Array CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 8 20 16 8 NWS [1:0] V R ...
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Cypress CY7C1312BV18 - page 3
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 3 of 29 Logic Block Diagram (CY7C1312BV18) Logic Block Diagram (CY7C1314BV18) 512K x 18 Array CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 18 19 36 18 BWS [1: ...
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Cypress CY7C1312BV18 - page 4
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 4 of 29 Pin Configuration The pin configuration for CY7C1310BV18, CY7C1910 BV18, CY7C1312BV18, and CY7 C1314BV18 follow . [1] 165-Ball FBGA (13 x 15 x 1 .4 mm) Pinout CY7C1310BV18 (2M x 8) 123456789 10 11 A CQ NC/72M A WPS NWS 1 K NC/144M RPS A NC/36M CQ B NC N ...
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Cypress CY7C1312BV18 - page 5
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 5 of 29 CY7C1312BV18 (1M x 18) 123456789 10 11 A CQ NC/144M NC/36M WPS BWS 1 K NC/28 8M RPS A NC/72M CQ B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AAA V SS NC Q7 D8 D NC D1 1 Q1 0 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V SS V SS V ...
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Cypress CY7C1312BV18 - page 6
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 6 of 29 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during val id write opera tions. CY7C1310BV18 - D [7:0] CY7C1910BV18 - D [8:0] CY7C1312BV18 - D [17:0] CY7C1314BV18 - ...
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Cypress CY7C1312BV18 - page 7
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 7 of 29 CQ Echo Clock CQ Referenced with Respect to C . This is a free - running clock and is synchronized to the Input clock for output data (C) of the QDR-II. In the single clock mode , CQ is generated wi th respect to K. The timing s for the echo clocks is s ...
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Cypress CY7C1312BV18 - page 8
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 8 of 29 Functional Overview The CY7C1310BV18, CY7C1910BV18, CY7C1312 BV18, and CY7C1314BV18 are synchronous pipelined Burst SRAMs equipped with a read port and a write p ort. The read port is dedicated to read operatio ns and the write port is dedica ted to wri ...
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Cypress CY7C1312BV18 - page 9
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 9 of 29 Programmable Impedan ce An external resistor , RQ, must be connected between the ZQ pin on the SRAM and V SS to allo w the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of th e intended line impedance d riven by the SR ...
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Cypress CY7C1312BV18 - page 10
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 10 of 29 T ruth T able The truth table for CY7C1310BV18, CY7C1910BV 18, CY7C1312BV18, and CY7C1314BV18 follows. [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising ed ge of K ; input write data on K and K rising edges. L-H X L D ...
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Cypress CY7C1312BV18 - page 11
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 1 1 of 29 Write Cycle Descriptions The write cycle description tabl e for CY7C1910BV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the data portion of a write sequence, the single b yte (D [8:0] ) is written into the device. L – L–H Du ring the da ...
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Cypress CY7C1312BV18 - page 12
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 12 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.1-1900. The T AP operates usin g JEDEC standard 1.8V IO log ...
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Cypress CY7C1312BV18 - page 13
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 13 of 29 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also place s the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the Shift ...
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Cypress CY7C1312BV18 - page 14
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 14 of 29 T AP Controller St ate Diagram The state diagram for the T AP controller follows. [9] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 ...
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Cypress CY7C1312BV18 - page 15
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 15 of 29 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 μ A1 ...
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Cypress CY7C1312BV18 - page 16
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 16 of 29 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Setup to ...
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Cypress CY7C1312BV18 - page 17
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 17 of 29 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1310BV18 CY7C1910BV18 CY7 C1312BV18 CY7C1314BV18 Revision Numb er (31:29) 000 000 000 000 V ersion number . Cypress Device ID (28:12) 1 101001 1010000101 1 101001 1010001 ...
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Cypress CY7C1312BV18 - page 18
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 18 of 29 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 1 1H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26 N 2 9 9 G 5 6 6 A 8 3 1 J 3 7P 30 1 1F 57 5B 84 2J 4 7N 31 1 1G 58 5A 85 3K 57 R 3 2 9 F 5 9 4 A 8 6 3 J 6 8R 33 10F 60 5C 8 ...
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Cypress CY7C1312BV18 - page 19
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 19 of 29 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW). ❐ Ap ...
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Cypress CY7C1312BV18 - page 20
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 20 of 29 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ........................ ......... –65°C to +150°C Ambient T empe r at ur e with Power Appl i ed. . ? ...
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Cypress CY7C1312BV18 - page 21
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 21 of 29 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs S tatic 250 MHz (x8) 400 mA (x9) 400 (x18) 400 (x36) 450 200 MHz (x8) 380 mA (x9) 380 (x18) 380 (x36) 400 167 MHz (x8) 360 ...
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Cypress CY7C1312BV18 - page 22
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 22 of 29 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Condition s Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V , V DDQ = 1.5V 5 pF C CLK Clock Input ...
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Cypress CY7C1312BV18 - page 23
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 23 of 29 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [22] 111 m s t CYC t KHKH K Clock and C Clo ...
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Cypress CY7C1312BV18 - page 24
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 24 of 29 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 6, 27, 28 ] K 1 2 34 5 8 10 6 7 K RPS WPS A D READ READ WRITE WRITE WRITE NOP READ WRITE NOP 9 A0 t KH t KHKH t KL t CY C tt HC t SA t HA t SD t HD SC t t SA t HA t SD t HD A6 A5 A3 A4 A1 A ...
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Cypress CY7C1312BV18 - page 25
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 25 of 29 Ordering Information Not all of the speed, package, and temper ature ranges are available. Please cont act your local sale s representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Package T ype ...
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Cypress CY7C1312BV18 - page 26
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 26 of 29 167 CY7C1310BV18-167BZC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1910BV18-167BZC CY7C1312BV18-167BZC CY7C1314BV18-167BZC CY7C1310BV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 m m) Pb-Fre ...
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Cypress CY7C1312BV18 - page 27
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 27 of 29 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BOTTOM ...
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Cypress CY7C1312BV18 - page 28
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 28 of 29 Document History Page Document Title: CY7C1310BV18/CY7C1910BV18/CY7C1312BV18 /C Y7C1314BV18, 18-Mbit QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05619 Rev . ECN No. Submission Date Orig, of Change Description of Change ** 25247 4 See E ...
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Cypress CY7C1312BV18 - page 29
Document #: 38-05619 Rev . *F Revised June 2, 2008 Page 29 of 29 QDR RAMs and Qua d Data Ra te RA Ms comprise a ne w fam i ly of pr od uct s developed by Cypress, Hit a chi, IDT , NE C , an d S am s un g. A l l p r oduct and company names mentioned in this d ocume nt a re the tradem arks of their r es pective hold ers. CY7C1310BV18, CY7C1910BV18 CY ...
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