-
Cypress STK17TA8 - page 1
STK17T A8 128k X 8 AutoS tore™ nvSRAM with Real T ime Clock Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-52039 Rev . ** Revised Marc h 02, 200 9 Features ■ nvSRAM Combined wi th Integrated Real T ime Clock Functions (RTC, W atchdog T imer , Cl ock Alarm, Power Monitor) ? ...
-
Cypress STK17TA8 - page 2
STK17T A8 Document #: 001-52039 Rev . ** Page 2 of 23 Pinout s Figure 1. Pin Diagram - 48-PIn SSOP V SS A 14 A 12 A 7 A 6 DQ 0 DQ 1 V CC DQ 2 A 3 A 2 A 1 V CAP A 13 A 8 A 9 A 11 A 10 DQ 7 DQ 6 V SS A 0 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC X 1 X 2 23 24 A 5 INT NC ...
-
Cypress STK17TA8 - page 3
STK17T A8 Document #: 001-52039 Rev . ** Page 3 of 23 Absolute Maximum Ratings V oltage on Input Rela tive to Gr ound ................ –0.1V to 4.1V V oltage on Input Rela tive to V SS .........–0.5V to (V CC + 0.5V) V oltage on DQ 0-7 or HSB .....................–0.5V to (V CC + 0.5V) T emperature under Bias .............. ................. ...
-
Cypress STK17TA8 - page 4
STK17T A8 Document #: 001-52039 Rev . ** Page 4 of 23 AC T est Conditions Input Pulse Levels ...... ............... .............. ........... ...... 0V to 3V Input Rise and Fall T imes ........... .............. .............. ..... < 5 ns Input and Output T iming Reference Levels ................ .... 1.5V Output Load .............. .......... ...
-
Cypress STK17TA8 - page 5
STK17T A8 Document #: 001-52039 Rev . ** Page 5 of 23 RTC DC Characteristics Figure 4. RTC Recommended Component Configuration Symbol Parameter Commercial Industrial Unit s Notes Min Max Min Max I BAK RTC Backup Current — 300 — 350 nA From either V RTC ca p or V RTC b at V RTC ba t RTC Battery Pin V oltage 1.8 3.3 1.8 3.3 V T ypical = 3.0 V olt ...
-
Cypress STK17TA8 - page 6
STK17T A8 Document #: 001-52039 Rev . ** Page 6 of 23 SRAM READ Cycles #1 and #2 Figure 5. SR AM READ Cycle #1: Address Controlled [3, 4, 6] Figure 6. SRAM READ Cycle #2: E and G Controlled [3, 6] Notes 3. W must be high during SRAM READ cycles. 4. Device is continuously selected with E and G both low 5. Measured ± 200mV from stead y state output ...
-
Cypress STK17TA8 - page 7
STK17T A8 Document #: 001-52039 Rev . ** Page 7 of 23 SRAM WRITE Cycles #1 and #2 Figure 7. SRAM WRITE Cycle #1: W Controlled [7, 8] Figure 8. SRAM WRITE Cycle #2: E Controlled [7, 8] Notes 7. If W is low when E goes low , the outputs remain in the high-impedance state. 8. E or W must be ≥ V IH during address transitions. NO. Symbols Parameter ST ...
-
Cypress STK17TA8 - page 8
STK17T A8 Document #: 001-52039 Rev . ** Page 8 of 23 AutoStore/Power Up Recall Figure 9. Au toStore /Power Up RECAL L Notes 9. t HRECALL starts from the time V CC rises abov e V SWITCH 10. If an SRAM WRITE has not tak en place since the last nonvolatile cycle, no STORE will take place 1 1. Industrial Grade De vices require 15 ms MAX. NO. Symbols P ...
-
Cypress STK17TA8 - page 9
STK17T A8 Document #: 001-52039 Rev . ** Page 9 of 23 Sof tware-Controlled ST ORE/RECALL Cycle In the following table, the soft war e controlled STORE and RECALL cycle para meters are listed. [12, 13] Figure 10. Software STORE / RECALL Cycle: E CONTROLLED [13] Figure 1 1. Software ST ORE / RECALL Cycle: G Controlled [13] NO. Symbols Parameter STK17 ...
-
Cypress STK17TA8 - page 10
STK17T A8 Document #: 001-52039 Rev . ** Page 10 of 23 Hardware ST ORE Cycle Figure 12. Hardware STORE Cycle Sof t Sequence Commands Figure 13. Sof t Sequence Commands NO. Symbols Parameter STK17T A8 Units Notes Stan da r d Alternate Min Max 31 t DELA Y t HLQZ Hardware STORE to SRAM Disabled 1 70 μ s1 4 32 t HLHX Hardware ST ORE Pulse Width 15 ns ...
-
Cypress STK17TA8 - page 11
STK17T A8 Document #: 001-52039 Rev . ** Page 1 1 of 23 MODE Selection E W G A 16 -A 0 Mode I/O Power Notes H X X X Not Selected Output High Z S tandby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Output Data Output Data Outp ...
-
Cypress STK17TA8 - page 12
STK17T A8 Document #: 001-52039 Rev . ** Page 12 of 23 nvSRAM Operation The STK17T A8 nvSRAM i s made up of tw o functional compo- nents paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates like a standar d fast static RAM. Data in the SRAM can be transferred to the nonvo ...
-
Cypress STK17TA8 - page 13
STK17T A8 Document #: 001-52039 Rev . ** Page 13 of 23 atile elements. Once a STORE cycl e is initiated, further memory inputs and outp ut s are disabled until the cycle is completed. T o initiate the Software STORE cycle, the following read sequence must be performed : 1. Read Address 0x4E38 V alid READ 2. Read Address 0xB1C7 V alid READ 3. Read A ...
-
Cypress STK17TA8 - page 14
STK17T A8 Document #: 001-52039 Rev . ** Page 14 of 23 Figure 15. Current versus Cycle Time RTC Operations Real T ime Clock The clock registers maintain time up to 9,999 years in one second increments. The user can set the time to a ny calendar time and the clock automatically keeps track of days of the week and month, leap years, and cent ury tran ...
-
Cypress STK17TA8 - page 15
STK17T A8 Document #: 001-52039 Rev . ** Page 15 of 23 Calibrati ng The Clock The RTC is driven by a quartz controlled oscillator with a nominal frequency of 32.768 KHz. Clock accuracy will depend on the quality of the crystal, specified (usually 35 ppm at 25 C). This error could equate to 1.53 minutes gain or loss per month. The STK17T A8 employs ...
-
Cypress STK17TA8 - page 16
STK17T A8 Document #: 001-52039 Rev . ** Page 16 of 23 Interrupt s The STK17T A8 has a Flags register , Interrupt Register , and interrupt logic that can interrupt a microcontroller o r generate a power-up master reset sig nal. There are three potenti al interrupt sources: the watchd og timer , the power monitor , and the clock alarm. Each can be i ...
-
Cypress STK17TA8 - page 17
STK17T A8 Document #: 001-52039 Rev . ** Page 17 of 23 RTC Register * A binary value, not a BCD value. 0 - Not implemented, reserved for future use. Default Settings of nonvolatile Calibrat ion and Interrupt registe rs from factory Calibration Reg ister=00h Interrupt Register=00h The User should configure to desired valu e at startup or during oper ...
-
Cypress STK17TA8 - page 18
STK17T A8 Document #: 001-52039 Rev . ** Page 18 of 23 Register Map Det ail 0x1FFFF Real Time Clock – Y ea rs D7 D6 D5 D4 D3 D2 D1 D0 10s Y ears Y ears Contains the lower two BCD digits of the year . Lower nibb le contains the value for years; up per nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the r ...
-
Cypress STK17TA8 - page 19
STK17T A8 Document #: 001-52039 Rev . ** Page 19 of 23 0x1FFF7 Watchdo g Timer D7 D6 D5 D4 D3 D2 D1 D0 WDS WDW WDT WDS W atchdog S trobe. Setting this bit to 1 reloads and restarts the watchdog timer . The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only . Reading it always will re turn a 0. WDW W a tchdog Wr ...
-
Cypress STK17TA8 - page 20
STK17T A8 Document #: 001-52039 Rev . ** Page 20 of 23 0x1FFF2 Alarm – Seconds D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Seconds Alarm Seconds Contains the alarm value for the seconds and the ma sk bit to select or desel ect the seconds’ value. M Match. Setting this bit to 0 causes the se conds’ value to be used in the alarm match. Setting this bit ...
-
Cypress STK17TA8 - page 21
STK17T A8 Document #: 001-52039 Rev . ** Page 21 of 23 Ordering Information Ordering Codes Packing Option Blank=T ube TR=T ape and Reel T emperatu re Range Blank=Commercial (0 to +70 C) I= Industrial (-45 to +85 C) Access Time 25=25 ns 45=45 ns Lead Finish F=100% Sn (Matte T in) RoHS Compliant Package R=Plastic 48-pin 300 mil SSOP (25 mil pitch) ST ...
-
Cypress STK17TA8 - page 22
STK17T A8 Document #: 001-52039 Rev . ** Page 22 of 23 Package Diagrams Figure 17. 48-Pin SSOP (51-85061) 51-85061 *C [+] Feedback ...
-
Cypress STK17TA8 - page 23
Document #: 001-52039 Rev . ** Revised Ma rch 02, 2009 Page 23 of 23 AutoS tore and Qu antumT rap are re gistered trademarks of C ypress Semiconducto r Corporation. All product s and compa ny names mentio ned in this document are the trad emarks of th eir respect ive holders. STK17T A8 © Cypress Semiconducto r Corporation, 2 009. The information c ...
¿Tienes una pregunta acerca de Cypress STK17TA8?
Utiliza el formulario que se encuentra abajo
Si con la ayuda del manual de instrucciones encontrado no has podido solucionar tu problema con Cypress STK17TA8, haz una pregunta utilizando el formulario que se encuentra abajo. Si alguno de los usuarios ha tenido un problema parecido con Cypress STK17TA8 probablemente compartirá una forma de solucionarlo.