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Cypress CY7C1576V18 - page 1
72-Mbit QDR™-II+ SRAM 4-W ord Burst Architecture (2.5 Cycle Read Latency) CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-05384 Rev . *F Revised March 6, 2008 Features ■ Separate independent read and write data ports ? ...
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Cypress CY7C1576V18 - page 2
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 2 of 28 Logic Block Diagram (CY7C1561V18) Logic Block Diagram (CY7C1576V18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 16 21 32 8 NWS [1:0] V ...
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Cypress CY7C1576V18 - page 3
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 3 of 28 Logic Block Diagram (CY7C1563V18) Logic Block Diagram (CY7C1565V18) 1M x 18 Array CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 36 20 72 18 BWS [1:0] ...
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Cypress CY7C1576V18 - page 4
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 4 of 28 Pin Configuration The pin configuration for CY7C1561V18, CY7C 1576 V18, CY7C1563V18, and CY7C15 65V18 follow . [2] 165-Ball FBGA (15 x 17 x 1 .4 mm) Pinout CY7C1561V18 (8M x 8) 123456789 10 11 A CQ AA W P S NWS 1 K NC/144M RPS AA C Q B NC NC NC A NC/2 ...
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Cypress CY7C1576V18 - page 5
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 5 of 28 CY7C1563V18 (4M x 1 8) 123456789 10 11 A CQ NC/144M A WPS BWS 1 K NC/288M RPS AA C Q B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AN CA V SS NC Q7 D8 D NC D1 1 Q10 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V SS V SS V DDQ NC D ...
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Cypress CY7C1576V18 - page 6
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 6 of 28 Pin Definitions Pin Name IO Pin Descripti on D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C1561V18 − D [7:0] CY7C1576V18 − D [8:0] CY7C1563V18 − D [17:0] C ...
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Cypress CY7C1576V18 - page 7
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 7 of 28 ZQ Input Output Impeda nce Matching Inpu t . This input is used to tune the dev ice outputs to the system data bus impedance. CQ, CQ and Q [x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground . Alternatel ...
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Cypress CY7C1576V18 - page 8
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 8 of 28 Functional Overview The CY7C1561V18, CY7C1576V18, CY7C1 563V18, and CY7C1565V18 are synchronous pipelined Burst SRAMs equipped with a read port and a write p ort. The read port is dedicated to read operatio ns and the write port is dedica ted to write ...
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Cypress CY7C1576V18 - page 9
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 9 of 28 Depth Exp ansion The CY7C1563V18 has a port select in put for each port. This enables for easy depth e xpansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the s pecified ...
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Cypress CY7C1576V18 - page 10
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 10 of 28 The truth table for CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 follows. [3, 4, 5, 6, 7, 8] T ruth T able Operation K RPS WPS DQ DQ DQ DQ Write Cycle: Load address on the rising edge of K; input write data on two consecutive K and K rising ...
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Cypress CY7C1576V18 - page 11
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 1 1 of 28 The write cycle description t able for CY7C1 576V18 follows. [3, 1 1] Write Cycle Descriptions BWS 0 K K L L–H – During the Dat a portion of a write sequence, the single byte (D [8:0] ) is written into the device . L – L –H During the Data p ...
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Cypress CY7C1576V18 - page 12
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 12 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 14 9.1-2001. The T AP operates using JEDEC standard 1.8V IO l ...
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Cypress CY7C1576V18 - page 13
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 13 of 28 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It a lso places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the Shi ...
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Cypress CY7C1576V18 - page 14
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 14 of 28 The state diagram for the T AP controller follows. [12] T AP Controller St ate Diag ram TEST -LOGIC RESET TEST -LOG IC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 ...
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Cypress CY7C1576V18 - page 15
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 15 of 28 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [13, 14, 15] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 μ A1 ...
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Cypress CY7C1576V18 - page 16
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 16 of 28 T AP AC Switching Characteristics Over the Operating Range [16, 17] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Setup t ...
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Cypress CY7C1576V18 - page 17
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 17 of 28 Identification R egi ster Definitions Instruction Field Va l u e De scription CY7C1561V18 CY7C1576V18 C Y7C1563V18 CY7C15 65V18 Revision Numb er (31:29) 000 000 000 000 V ersio n numbe r . Cypress Device ID (28:12) 1 101 0010001000100 1 1010010001001 ...
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Cypress CY7C1576V18 - page 18
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 18 of 28 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 87 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61 4B 89 1K 6 8R 34 1 1E 62 3A 9 ...
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Cypress CY7C1576V18 - page 19
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 19 of 28 Power Up Sequence in QDR-II+ SRAM QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of st able clock. Power Up ...
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Cypress CY7C1576V18 - page 20
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 20 of 28 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ................ ................. –65°C to +150°C Ambient T emperature with Pow e r App l i ed. . ...
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Cypress CY7C1576V18 - page 21
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 21 of 28 I DD [22] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 333 MHz x8 1200 mA x9 1200 x18 1200 x36 1200 300 MHz x8 11 0 0 mA x9 11 0 0 x18 11 0 0 x36 11 0 0 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ...
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Cypress CY7C1576V18 - page 22
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 22 of 28 AC Electrical Characteristics Over the Operating Range [14] Parameter Description T est Cond itions Min Ty p Max Unit V IH Input HIGH V oltage V REF + 0.2 – V DDQ + 0.24 V V IL Input LOW V oltage –0.24 – V REF – 0.2 V Cap acit ance T ested in ...
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Cypress CY7C1576V18 - page 23
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 23 of 28 Switching Characteristics Over the Operating Range [23, 24] CY Parameter Consor tium Parameter Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Min Max Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [25] 1111 m s t CYC t KHKH K C ...
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Cypress CY7C1576V18 - page 24
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 24 of 28 Switching W aveforms Read/Write/Deselect Sequence [31, 32, 33] Figure 5. W aveform for 2.5 Cycle Read L atency t KH t KL t CYC t KHKH t t t t SA HA SC HC t HD t SC t HC A0 A1 A2 A3 t t SD HD t SD D1 1 D10 D12 D13 D30 D31 D32 D33 D A WPS RPS K K t NOP ...
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Cypress CY7C1576V18 - page 25
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 25 of 28 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Package T ype O ...
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Cypress CY7C1576V18 - page 26
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 26 of 28 333 CY7C1561V18-333BZC 51-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1576V18-333BZC CY7C1563V18-333BZC CY7C1565V18-333BZC CY7C1561V18-333BZXC 51-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free C ...
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Cypress CY7C1576V18 - page 27
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev . *F Page 27 of 28 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-8 5195 ! 0).#/2.%2 ¼ ¼ ...
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Cypress CY7C1576V18 - page 28
Document Number: 001-05384 Rev . *F Revised March 6, 2008 Page 28 of 28 QDR RAMs an d Quad Data R ate RAMs comprise a new family of products devel oped by Cypress, IDT , NEC, Renesas, and Samsung. All pr oduct and comp any names ment ioned in this do cument are the tr ad emarks of their respe ctive hold er s. CY7C1561V18, CY7C1576V18 CY7C1563V18, C ...
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