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Manual de instrucciones Cypress CY7C0833AV

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Summary
  • Cypress CY7C0833AV - page 1

    FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchr onous Dual-Port RAM CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06059 Rev . *S Revised Marc h 03, 200 9 Features ■ T rue Dual-Ported Memory Cell ...

  • Cypress CY7C0833AV - page 2

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 2 of 28 Logic Block Diagram [2] A 0L –A 18L CLK L ADS L CNTEN L CNTRST L Tr u e RAM Array 19 Addr . Read Back CNTINT L Mask Register Counter/ Address Register CNT/MSK L Address Decode Dual-Ported Interrupt Logic INT L Reset Logic JT AG TDO ...

  • Cypress CY7C0833AV - page 3

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 3 of 28 Pin Configurations Figure 1. 144-Ball BGA (T op View) CY7C0837A V / CY7C0830A V / CY7C0831A V / CY7C0832A V / CY7C0833A V 123456789 10 11 12 A DQ17 L DQ16 L DQ14 L DQ12 L DQ10 L DQ9 L DQ9 R DQ10 R DQ12 R DQ14 R DQ16 R DQ17 R B A0 L A ...

  • Cypress CY7C0833AV - page 4

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 4 of 28 Figure 2. 120-Pin Thin Quad Flat Pack (TQFP) (T op View) CY7C0830A V / CY7C0831A V / CY7C0832A V / CY7C0832BV Pin Configurations 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 ...

  • Cypress CY7C0833AV - page 5

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 5 of 28 Pin Definitions Lef t Port Right Port Description A 0L –A 18L [2] A 0R –A 18R [2] Address Inputs . ADS L [8] ADS R [8] Address Strobe Input . Used as an ad dress qualifier . This signal should be asserted LOW for the part using t ...

  • Cypress CY7C0833AV - page 6

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 6 of 28 Master Reset The FLEx18 family devices und ergo a complete reset by taking its MRST input LOW . The MRST input can switch asynchro- nously to the clocks. An MRST initializes the internal burst counters to zero, and the counter mask r ...

  • Cypress CY7C0833AV - page 7

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 7 of 28 Counter Reset Oper ation All unmasked bits of the counter are reset to ‘0.’ All maske d bits remain unchanged. The mirror register is loaded with the valu e of the burst counter . A Mask Reset followed by a Counter Reset resets t ...

  • Cypress CY7C0833AV - page 8

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 8 of 28 Retransmit Retransmit is a feature that allows the Re ad of a block of memory more than once without the nee d to reload the initial a ddress. This eliminates the need for exte rnal logic to store and route data. It also reduces the ...

  • Cypress CY7C0833AV - page 9

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 9 of 28 Figure 3. Counter , Mask, and Mirr or Logic Block Diagram [1] From Mask Register Mirror Counter Address Decode RAM Array Wra p 1 0 Increment Logic 1 0 +1 +2 1 0 Wra p Detect From Mask From Counter To Counter Bit 0 Wra p 17 17 17 17 1 ...

  • Cypress CY7C0833AV - page 10

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 10 of 28 IEEE 1 149.1 Serial Boun dary Scan (JT AG) [21] The FLEx18 family devices inco rporate an IEEE 1 149.1 serial boundary scan test access port (T AP). The T AP controller functions in a ma nner that doe s not confli ct with the operat ...

  • Cypress CY7C0833AV - page 11

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 1 1 of 28 Figure 5. Scan Chain for 9 Mb Device T a ble 4. Identification Register Definitions Instruction Field Va l u e Descriptio n Revision Number (31:2 8) 0h Reserved for version number . Cypress Device ID (27:12) C090h Defines Cypress p ...

  • Cypress CY7C0833AV - page 12

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 12 of 28 Maximum Ratings Exceeding maximum ratings [23] may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature ................. .............. .. –65 ° C to +1 50 ° C Ambient T emper ature ...

  • Cypress CY7C0833AV - page 13

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 13 of 28 Figure 6. AC T est Load and Waveforms Switching Characteristics Over the Operating Range Parameter Descriptio n -167 -133 -100 Unit CY7C0837A V CY7C0830A V CY7C0831A V CY7C0832A V CY7C0837A V CY7C0830A V CY7C0831A V CY7C0832A V CY7C ...

  • Cypress CY7C0833AV - page 14

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 14 of 28 t HCM CNT/MSK Hold T ime 0.6 0.6 NA NA ns t OE Output Enable to Data V alid 4.0 4.4 4.7 5.0 ns t OLZ [28,29] OE to Low Z 0 0 ns t OHZ [28,29] OE to High Z 0 4.0 0 4.4 4.7 5.0 ns t CD2 Clock to Data V alid 4.0 4.4 4.7 5.0 ns t CA2 Cl ...

  • Cypress CY7C0833AV - page 15

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 15 of 28 JT AG Timing and Switching W aveforms Parameter Description CY7C0837A V/CY7C0830A V CY7C0831A V/CY7C0832A V CY7C0832BV/CY7C0833A V Unit Min Max f JT AG Maximum JT AG T AP Controller Frequ ency 10 MHz t TCYC TCK Clock Cycle T ime 100 ...

  • Cypress CY7C0833AV - page 16

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 16 of 28 Switching W aveforms Figure 8. Master Re set Figure 9. Read Cycle [12, 30, 31, 3 2, 33] MRST t RSR t RS INACTIVE ACTIVE TMS TDO INT CNTINT t RSF t RSS ALL ADDRESS/ DATA LINES ALL OTHER INPUTS t CH2 t CL2 t CYC2 t SC t HC t SW t HW t ...

  • Cypress CY7C0833AV - page 17

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 17 of 28 Figure 10. Bank Select Read [34, 35] Figure 1 1 . Read -to-Write-to-Read (OE = LOW) [33, 36, 37 , 38, 39] Switching W aveforms (continued) Q 3 Q 1 Q 0 Q 2 A 0 A 1 A 2 A 3 A 4 A 5 Q 4 A 0 A 1 A 2 A 3 A 4 A 5 t SA t HA t SC t HC t SA ...

  • Cypress CY7C0833AV - page 18

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 18 of 28 Figure 12. Read-to-Write-to-Read (OE Controlled) [33, 36, 38, 39 ] Figure 13. R ead with Add ress Counter Ad vance [38] Switching W aveforms (continued) t CYC2 t CL2 t CH2 t HC t SC t HW t SW t HA t SA A n A n+1 A n+2 A n+3 A n+4 A ...

  • Cypress CY7C0833AV - page 19

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 19 of 28 Figure 14. Write with Address Counter Advan ce [39] Figure 15. Counter Reset [40, 41] Switching W aveforms (continued) t CH2 t CL2 t CYC2 A n A n+1 A n+2 A n+3 A n+4 D n+1 D n+1 D n+2 D n+3 D n+4 A n D n t SAD t HAD t SCN t HCN t SD ...

  • Cypress CY7C0833AV - page 20

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 20 of 28 Figure 16. Readback State of Address Counter or Mask Reg ister [43, 44, 45, 46 ] Switching W aveforms (continued) CNTEN CLK t CH2 t CL2 t CYC2 ADDRESS ADS A n Q x-2 Q x-1 Q n t SA t HA t SAD t HAD t SCN t HCN LOAD ADDRESS EXTERNAL t ...

  • Cypress CY7C0833AV - page 21

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 21 of 28 Figure 17. Lef t_Port (L_Port) Wr ite to Right_Port (R_Port) Read [47, 48, 49] Switching W aveforms (continued) t SA t HA t SW t HW t CH2 t CL2 t CYC2 CLK L R/W L A n D n t CKHZ t HD t SA A n t HA Q n t DC t CCS t SD t CKLZ t CH2 t ...

  • Cypress CY7C0833AV - page 22

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 22 of 28 Figure 18. Counter Interrupt and Retran smit [15, 42, 50, 51 , 52, 53] Switching W aveforms (continued) t CH2 t CL2 t CYC2 CLK 3FFFD 3FFFF INTERNAL ADDRESS Last_Loaded Last_Loaded +1 t HCM COUNTER 3FFFE CNTINT t SCINT t RCINT 3FFFC ...

  • Cypress CY7C0833AV - page 23

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 23 of 28 Figure 19. MailBox Interrupt Timing [54, 55, 56, 57, 58] T a ble 7. Read/Write and Enable Operation (Any Port) [2, 17, 59 , 60, 61] Input s Ou tputs Operation OE CLK CE 0 CE 1 R/W DQ 0 – DQ 17 X H X X High-Z Deselected X X L X Hig ...

  • Cypress CY7C0833AV - page 24

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 24 of 28 Ordering Information 512K × 18 (9M) 3.3V Synchronous CY7C08 33A V Dual-Port SRAM Spee d (MHz) Ordering Code Package Diagram Package T ype Operating Range 133 CY7C0833A V-133BBC 51-85141 144-Ball Grid Ar r ay (13 x 13 x 1.6 mm) with ...

  • Cypress CY7C0833AV - page 25

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 25 of 28 32K × 18 (512K) 3.3V Synchronous CY7C0837A V Dual-Port SRAM Spee d (MHz) Ordering Code Package Diagram Package T ype Operating Range 167 C Y 7C08 37A V-167BBC 51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch Commerci ...

  • Cypress CY7C0833AV - page 26

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 26 of 28 Figure 21. 120-Pin Thin Quad Flatp ack (14 x 14 x 1 .4 mm) (51-85100) Package Diagrams 51-85100-** [+] Feedback ...

  • Cypress CY7C0833AV - page 27

    CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 27 of 28 Document History Page Document Title: CY7C0837A V/CY7C0 830 A V/CY7C0831A V/CY7C0832A V/CY7C0832BV/CY7C 0833A V, FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Document Number: 38-06059 Rev . ECN No. Orig. ...

  • Cypress CY7C0833AV - page 28

    Document #: 38-06059 Rev . *S Revised March 03, 2009 Page 28 of 28 FLEx18 is a tr ademark of Cypress Semiconductor Co rporation. Al l product and co mpany names me ntioned in this document may be the tradem arks of th ei r respec tive holder s. CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V © Cypress Semico nductor Corpo ...

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