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Cypress CY7C1215H - page 1
1-Mbit (32K x 32) Pipelined Sync SRAM CY7C1215H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05666 Rev . *B Revised July 5, 2006 Features • Registered inp uts and outputs for pipelined op er ation • 32K × 32 common I/O architecture • 3.3V core power supply (V DD ) ? ...
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Cypress CY7C1215H - page 2
CY7C1215H Document #: 38-05666 Rev . *B Page 2 of 15 Pin Configuration Selection Guide 166 MHz 133 MHz Unit Maximum Access T i me 3.5 4.0 ns Maximum Operating Current 240 225 mA Maximum CMOS S tandby Cu rrent 40 40 mA A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/18M NC/9M A A A A A NC/2M NC/4M NC DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ ...
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Cypress CY7C1215H - page 3
CY7C1215H Document #: 38-05666 Rev . *B Page 3 of 15 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of th e 32K address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A 1 , A 0 feed the 2-bit counter . BW A , BW ...
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Cypress CY7C1215H - page 4
CY7C1215H Document #: 38-05666 Rev . *B Page 4 of 15 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled b y the rising edge of the clock. The CY7C1215H supports secondary cache in systems utilizing either a linear or interleave ...
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Cypress CY7C1215H - page 5
CY7C1215H Document #: 38-05666 Rev . *B Page 5 of 15 Interleaved Burst Address T able (MODE = Floating or V DD ) First Address A 1 , A 0 Second Address A 1 , A 0 Third Address A 1 , A 0 Fourth Address A 1 , A 0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address T ab le (MODE = GND) First Address A 1 , A 0 Second Address A 1 , A 0 ...
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Cypress CY7C1215H - page 6
CY7C1215H Document #: 38-05666 Rev . *B Page 6 of 15 T ruth T able for Read/W rite [2, 3] Function GW BWE BW D BW C BW B BW A Continue Write Next L H X X X Suspend Write Current L X X X H Suspend Write Current L H X X X Z Z “ S l e e p ” N o n e H XXXX R e a d H HXXXX R e a d H L HHHH Write Byte A – DQ A H L HHH L Write Byte B – DQ B HLH HL ...
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Cypress CY7C1215H - page 7
CY7C1215H Document #: 38-05666 Rev . *B Page 7 of 15 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. ... ... ... ... ....... –65 ° C to + 150 ° C Ambient T e mperature with Power Applied ................. ... ... .. ............ .. ... .. –55 ° C to + 125 ? ...
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Cypress CY7C1215H - page 8
CY7C1215H Document #: 38-05666 Rev . *B Page 8 of 15 Cap acit ance [9] Parameter Description T est Conditions 100 T QF P Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V . V DDQ = 2.5V 5 pF C CLK Clock Input Capacit ance 5 pF C I/O Input/Output Capacit ance 5 pF Thermal Resist ance [9] Parameter Description T est Conditions 10 ...
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Cypress CY7C1215H - page 9
CY7C1215H Document #: 38-05666 Rev . *B Page 9 of 15 Switching Characteristics Over the Operating Range [10, 1 1] Parameter Description 166 MHz 133 MHz Unit Min. Max Min. Max t POWER V DD (T ypical) to the First Access [12] 1 1m s Clock t CYC Clock Cycle T ime 6.0 7.5 ns t CH Clock HIGH 2.5 3.0 ns t CL Clock LOW 2.5 3.0 ns Output Times t CO Data Ou ...
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Cypress CY7C1215H - page 10
CY7C1215H Document #: 38-05666 Rev . *B Page 10 of 15 Switching W aveforms Read Cycle Timing [16] Note: 16. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BW[A:D] D ata ...
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Cypress CY7C1215H - page 11
CY7C1215H Document #: 38-05666 Rev . *B Page 1 1 of 15 Write Cycle T iming [16, 17] Note: 17. Full width Write can be initiated by either GW LOW ; or by GW HIGH, BWE LOW and BW [A:D] LOW . Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW[A :D] D ata Out (Q) High-Z ADV BURST RE ...
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Cypress CY7C1215H - page 12
CY7C1215H Document #: 38-05666 Rev . *B Page 12 of 15 Read/Write Cycle Timing [16, 18, 19 ] Notes: 18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 19. GW is HIGH. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CES BWE, BW ...
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Cypress CY7C1215H - page 13
CY7C1215H Document #: 38-05666 Rev . *B Page 13 of 15 ZZ Mode T iming [20, 21] Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descr iptions t able for all possible signal conditi ons to deselect the device. 21. DQs are in High-Z when exiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INP ...
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Cypress CY7C1215H - page 14
CY7C1215H Document #: 38-05666 Rev . *B Page 14 of 15 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do ...
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Cypress CY7C1215H - page 15
CY7C1215H Document #: 38-05666 Rev . *B Page 15 of 15 Document History Page Document Title: CY7C1215H 1-Mbit (32K x 32) Pipelined Syn c SRAM Document Number: 38-05666 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 343896 See ECN PCI New Data Sheet *A 430678 See ECN NXR Changed address of Cypress Semiconductor Corpor ation on Page ...
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