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Cypress CY7C1324H - page 1
2-Mbit (128K x 18) Flow-Through Sync SRAM CY7C1324H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 001-00208 Rev . *B Revised April 26, 2006 Features • 128K x 18 common I/O • 3.3V core power supply • 3.3V/2.5V I/O supply • Fast clock-to-output times — 6.5 ns (133-MHz ...
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Cypress CY7C1324H - page 2
CY7C1324H Document #: 001-00208 Rev . *B Page 2 of 15 Selection Guide 133 MHz Unit Maximum Access T i me 6.5 ns Maximum Operating Current 225 mA Maximum S tandby Curre nt 40 mA Pin Configurations 100-pin TQFP Pinout A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/9M A A A A A NC/4M A NC V DDQ V SS NC DQP B DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD DQ ...
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Cypress CY7C1324H - page 3
CY7C1324H Document #: 001-00208 Rev . *B Page 3 of 15 Pin Definitions Name I/O Descriptio n A0, A1, A Input- Synchronous Address Inputs used to select one of the 128 K add ress location s. Sampled at the rising edge of the CLK i f ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A [1:0] feed the 2-bit counter . BW A, BW B ...
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Cypress CY7C1324H - page 4
CY7C1324H Document #: 001-00208 Rev . *B Page 4 of 15 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1324H supports secondary cache in systems utilizing either a linear or interleaved burst sequ ...
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Cypress CY7C1324H - page 5
CY7C1324H Document #: 001-00208 Rev . *B Page 5 of 15 ZZ Mode Electrical Characteristics Parameter Description T est Co nd itions Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 40 mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V 2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V 2t CYC ns t ZZI ZZ Active to sleep curr ent ...
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Cypress CY7C1324H - page 6
CY7C1324H Document #: 001-00208 Rev . *B Page 6 of 15 T ruth T able for Read/Write [2, 3] Function GW BWE BW B BW A Read H H X X Read H L H H Write Byte (A, DQP A )H L H L Write Byte (B, DQP B )H L L H Write All Bytes H L L L Write All Bytes L X X X [+] Feedback ...
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Cypress CY7C1324H - page 7
CY7C1324H Document #: 001-00208 Rev . *B Page 7 of 15 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ................ .............. ... –65 ° C to +150 ° C Ambient T e mperature with Power Applied ....................... .............. ........ –55 ° C to +125 ° C Sup ...
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Cypress CY7C1324H - page 8
CY7C1324H Document #: 001-00208 Rev . *B Page 8 of 15 Cap acit ance [8] Parameter Description T est Cond itio ns 100 TQFP Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V . V DDQ = 2.5V 5p F C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Resist ance [8] Parameter Description T est Conditions 100 ...
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Cypress CY7C1324H - page 9
CY7C1324H Document #: 001-00208 Rev . *B Page 9 of 15 Switching Characteristics Over the Operating Range [9, 10] Parameter Description -133 Unit Min. Max. t POWER V DD (T ypical) to the First Access [1 1] 1m s Clock t CYC Clock Cycle T ime 7.5 ns t CH Clock HIGH 2.5 ns t CL Clock LOW 2.5 ns Output Times t CDV Data Output V alid after CLK Rise 6.5 n ...
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Cypress CY7C1324H - page 10
CY7C1324H Document #: 001-00208 Rev . *B Page 10 of 15 Timing Diagrams Read Cycle Timing [15] Note: 15. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH t CDV t OEH ...
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Cypress CY7C1324H - page 11
CY7C1324H Document #: 001-00208 Rev . *B Page 1 1 of 15 Write Cycle T iming [15, 16] Note: 16. Full width Write can be initiated b y either GW LOW; or by GW HIGH, BWE LOW and BW [A:B] LOW. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) ...
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Cypress CY7C1324H - page 12
CY7C1324H Document #: 001-00208 Rev . *B Page 12 of 15 Read/Write T i ming [15, 17, 18] Notes: 17. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 18. GW is HIGH. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WRITE D(A3) A3 A4 BURST R ...
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Cypress CY7C1324H - page 13
CY7C1324H Document #: 001-00208 Rev . *B Page 13 of 15 ZZ Mode T iming [19, 20] Notes: 19. Device must be deselected when entering ZZ mode. See Cycle Descr iptions t able for all possible signal conditions to deselect the device. 20. DQs are in High-Z when exiting ZZ sleep mode. Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS ( ...
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Cypress CY7C1324H - page 14
CY7C1324H Document #: 001-00208 Rev . *B Page 14 of 15 © Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bj ect to ch ange without notice. Cypress S em ic on duct or Corpo ration assu mes no resp onsib ility for th e u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor does i ...
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Cypress CY7C1324H - page 15
CY7C1324H Document #: 001-00208 Rev . *B Page 15 of 15 Document History Page Document Title: CY7C1324H 2-Mbit (128K x 18) Flow-Throu gh Sync SRAM Document Number: 00 1-00208 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 347377 See ECN PCI New Data Sheet *A 428408 See ECN NXR Converted from Preliminary to Final. Changed address o ...
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