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Cypress CY7C1329H - page 1
2-Mbit (64K x 32) Pipelined Sync SRAM CY7C1329H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05673 Rev . *B Revised March 22, 2006 Features • Registered inp uts and outputs for pipelined op er ation • 64K × 32 common I/O architecture • 3.3V core power supply • 2.5 ...
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Cypress CY7C1329H - page 2
CY7C1329H Document #: 38-05673 Rev . *B Page 2 of 16 Pin Configuration Selection Guide 166 MHz 133 MHz Unit Maximum Access T i me 3.5 4.0 ns Maximum Operating Current 240 225 mA Maximum CMOS S tandby Current 40 40 mA A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/18M NC/9M A A A A A A NC/4M NC DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B ...
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Cypress CY7C1329H - page 3
CY7C1329H Document #: 38-05673 Rev . *B Page 3 of 16 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inp ut s used to select one of the 64K address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A 1 , A 0 feed the 2-bit counter . BW A ,BW ...
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Cypress CY7C1329H - page 4
CY7C1329H Document #: 38-05673 Rev . *B Page 4 of 16 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled b y the rising edge of the clock. The CY7C1329H supports secondary cache in systems utilizing either a linear or interleave ...
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Cypress CY7C1329H - page 5
CY7C1329H Document #: 38-05673 Rev . *B Page 5 of 16 Interleaved Burst Address T able (MODE = Floating or V DD ) First Address A 1 , A 0 Second Address A 1 , A 0 Third Address A 1 , A 0 Fourth Address A 1 , A 0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address T able (MODE = GND) First Address A 1 , A 0 Second Address A 1 , A 0 T ...
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Cypress CY7C1329H - page 6
CY7C1329H Document #: 38-05673 Rev . *B Page 6 of 16 T ruth T able [2, 3, 4, 5, 6, 7] Next Cycle Add. Used Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE Unselected None None H X X L X L X X X Unselected None None L L X L L X X X X Unselected None None L X H L L X X X X Unselected None None L L X L H L X X X Unselected None None L X H L H L X X ...
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Cypress CY7C1329H - page 7
CY7C1329H Document #: 38-05673 Rev . *B Page 7 of 16 Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L W r i t e B y t e s D , C , B H LLLL H W r i t e A l l B y t e s H LLLLL W r i t e A l l B y t e s L XXXXX T ruth T able for Read/W rite (continue ...
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Cypress CY7C1329H - page 8
CY7C1329H Document #: 38-05673 Rev . *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guid e- lines, not tested . ) S torage T emperature .. .............. .............. ... –65 ° C to +150 ° C Ambient T emperature with Power Applied.................... .............. ........... –55 ° C to +125 ° C Su ...
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Cypress CY7C1329H - page 9
CY7C1329H Document #: 38-05673 Rev . *B Page 9 of 16 Cap acit ance [10] Parameter Descriptio n T est Con d itions 100 TQFP Max. Unit C IN Input Capacit ance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5p F C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacit ance 5 pF Thermal Resist ance [10] Parameter Description T est Con dition s ...
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Cypress CY7C1329H - page 10
CY7C1329H Document #: 38-05673 Rev . *B Page 10 of 16 Switching Characteristics Over the Operating Range [1 1, 12] Parameter Description 166 MHz 133 MHz Unit Min. Max Min. Max t POWER V DD (T ypical) to the First Access [13] 11 m s Clock t CYC Clock Cycle T ime 6.0 7.5 ns t CH Clock HIGH 2.5 3.0 ns t CL Clock LOW 2.5 3.0 ns Output Times t CO Data O ...
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Cypress CY7C1329H - page 11
CY7C1329H Document #: 38-05673 Rev . *B Page 1 1 of 16 Switching W aveforms Read Cycle Timing [17] Note: 17. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BW[A:D] D ata ...
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Cypress CY7C1329H - page 12
CY7C1329H Document #: 38-05673 Rev . *B Page 12 of 16 Write Cycle T iming [17, 18] Note: 18. Full width Write can be initiate d by either GW LOW; or by GW HIGH, BWE LOW and BW [A : D] LOW. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW[A :D] D ata Out (Q) High-Z ADV BURST RE ...
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Cypress CY7C1329H - page 13
CY7C1329H Document #: 38-05673 Rev . *B Page 13 of 16 Read/Write Cycle Timing [17, 19, 20 ] Notes: 19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 20. GW is HIGH. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CES BWE, BW ...
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Cypress CY7C1329H - page 14
CY7C1329H Document #: 38-05673 Rev . *B Page 14 of 16 ZZ Mode T iming [21, 22] Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descr iptions t able for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPU ...
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Cypress CY7C1329H - page 15
CY7C1329H Document #: 38-05673 Rev . *B Page 15 of 16 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do ...
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Cypress CY7C1329H - page 16
CY7C1329H Document #: 38-05673 Rev . *B Page 16 of 16 Document History Page Document Title: CY7C1329H 2-Mbit (64K x 32) Pipelined Syn c SRAM Document Number: 38-05673 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 347357 See ECN PCI New Data Sheet *A 424820 See ECN RXU Converted from Preliminary to Final. Changed address of Cypre ...
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