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Cypress CYV15G0404RB - page 1
Independent Clock Quad HOTLink II™ Deserializing Reclocke r CYV15G0404RB Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-02102 Rev . *C Revised February 16, 2007 Features • Second-generation HOTLink ® technology • Compliant to SMPTE 292M and SMP TE 259M video standards ? ...
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Cypress CYV15G0404RB - page 2
CYV15G0404RB Document #: 38-02102 Rev . *C Page 2 of 27 Figure 1. HOTLink II ™ System Connecti on s Vide o Coproc es sor 10 10 10 10 Video Coprocessor 10 10 10 10 Serial Links Independ ent CYV15G04 03TB Independent Reclocking Deserializer Serializer Channel CYV15G0404R B Channel Reclocked Outputs Reclocked Outputs CYV15G0404RB Deserializing Reclo ...
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Cypress CYV15G0404RB - page 3
CYV15G0404RB Document #: 38-02102 Rev . *C Page 3 of 27 Reclocking Deserializer Path Block Diagra m INA1+ INA1– INA2+ INA2– INSELA Clock & Data Recovery PLL Shifter LFIA 10 RXDA[9:0] Receive Signal Monitor Output Register RXCLKA+ RXCLKA– ÷ 2 RXPLL PDA SPDSELA ULCA RXRA TEA 10 BIST LFSR 10 RXBIST A[1:0] LDTDEN SDASEL[2..1]A[1:0 ] ROUT A1+ ...
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Cypress CYV15G0404RB - page 4
CYV15G0404RB Document #: 38-02102 Rev . *C Page 4 of 27 Reclocking Deserializer Path Block Diagram (continued) = Internal Signal INC1+ INC1– INC2+ INC2– INSELC Clock & Data Recovery PLL Shifter LFIC 10 RXDC[9:0] Receive Signal Monitor Output Register RXCLKC+ RXCLKC– ÷ 2 RXPLLPDC SPDSELC ULCC RXRA TEC 10 BIST LFSR 10 RXBIST C[1:0] LDTDEN ...
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Cypress CYV15G0404RB - page 5
CYV15G0404RB Document #: 38-02102 Rev . *C Page 5 of 27 WREN ADDR[3:0] DA T A[7:0] Device Configuration and Control Block Diagram = Internal Sign al RXRA TE[A..D] RXBIST[A..D] SDASEL[A..D ][1:0] RXPLLPD[A..D] ROE[2..1][A..D] GLEN[1 1.. 0] FGLEN[2..0] Device Configuration and Control Interface [+] Feedback ...
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Cypress CYV15G0404RB - page 6
CYV15G0404RB Document #: 38-02102 Rev . *C Page 6 of 27 Pin Configuration (T op View) [1 ] Note 1. NC = Do not conne ct. 123456789 10 11 12 13 14 15 16 17 18 19 20 A IN C1– ROUT C1– IN C2– ROUT C2– V CC IN D1– ROUT D1– GND IN D2– ROUT D2– IN A1– ROUT A1– GND IN A2– ROUT A2– V CC IN B1– ROUT B1– IN B2– ROUT B2– B IN C ...
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Cypress CYV15G0404RB - page 7
CYV15G0404RB Document #: 38-02102 Rev . *C Page 7 of 27 Pin Configuration (Bottom V iew) [1] 20 19 18 17 16 15 14 13 12 11 10 987654321 A ROUT B2– IN B2– ROUT B1– IN B1– V CC ROUT A2– IN A2– GND ROUT A1– IN A1– ROUT D2– IN D2– GND ROUT D1– IN D1– V CC ROUT C2– IN C2– ROUT C1– IN C1– B ROUT B2+ IN B2+ ROUT B1+ IN B1+ ...
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Cypress CYV15G0404RB - page 8
CYV15G0404RB Document #: 38-02102 Rev . *C Page 8 of 27 Pin Definitions CYV15G0404RB Quad HOTLink II Deserializing Reclocker Name IO Characteristics Signal Description Receive Path Data and St atus Signals RXDA[9:0] RXDB[9:0] RXDC[9:0] RXDD[9:0] L VTTL Output, synchronous to the RXCLK± output Parallel Data Output . RXDx[9:0] parallel data out puts ...
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Cypress CYV15G0404RB - page 9
CYV15G0404RB Document #: 38-02102 Rev . *C Page 9 of 27 LDTDEN L VTTL Input, internal p ull up Level Detect T ransition Density Enab le . When LDTDEN is H IGH, the Signal Level Detector , Range Controller , and T ransition Density De tector are all enabled to determine if the RXPLL tracks TRGCLKx± or the selected input serial data stream. If the S ...
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Cypress CYV15G0404RB - page 10
CYV15G0404RB Document #: 38-02102 Rev . *C Page 10 of 27 DA T A[7:0] L VTTL input asynchronous, internal p ull-up Control Data Bus . The DA T A[7:0] bu s is the input data bus that configures the device. The WREN input writes the values of the DA T A[7:0] bus into the latch specified by address locati on on the ADDR[3:0] bus. [3] T able 3, “Devic ...
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Cypress CYV15G0404RB - page 11
CYV15G0404RB Document #: 38-02102 Rev . *C Page 1 1 of 27 CYV15G0404RB HOTLink II Op eration The CYV15G0404R B is a highly configurable, indepe ndent clocking, quad-channel reclocking deseria lizer that supports reliable transfer of larg e quantit ie s of di gital video data, using high-speed serial l inks from multiple sources to multiple de sti- ...
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Cypress CYV15G0404RB - page 12
CYV15G0404RB Document #: 38-02102 Rev . *C Page 12 of 27 operates at, or near the rate of the inco ming dat a stream for two primary cases: • When the incoming data stream resumes after a time in which it was “missing.” • When the incoming data stream is outside the acceptable signaling rate range. T o perform this function, periodica lly c ...
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Cypress CYV15G0404RB - page 13
CYV15G0404RB Document #: 38-02102 Rev . *C Page 13 of 27 reclocker serial drivers for a ch annel are in this disabled state, the associated internal reclocker logic also pow ers down. The deserialization logic a nd parallel outputs remain enabled. A device reset (RESET sampled LOW) disables all output drivers. Note When the disabled reclocker funct ...
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Cypress CYV15G0404RB - page 14
CYV15G0404RB Document #: 38-02102 Rev . *C Page 14 of 27 Latch Banks 12, 13, and 14 load values i n the related latch banks in globally . A write opera tion to l atch bank 12 performs a global write to latch banks 0, 3, 6, and 9, depend ing on the value of GLENx in th ese latch banks; l atch bank 1 3 performs a global write to latch banks 1, 4, 7, ...
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Cypress CYV15G0404RB - page 15
CYV15G0404RB Document #: 38-02102 Rev . *C Page 15 of 27 Device Configuration Strategy Follow these steps to load the configuration latches on each channel: 1. Pulse RESET Low after device power up. This operation resets all four channels. Initialize the JT AG state machine to its reset state, as det ailed in “JT AG Support” on page 17 . 2. Set ...
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Cypress CYV15G0404RB - page 16
CYV15G0404RB Document #: 38-02102 Rev . *C Page 16 of 27 T able 4. Device Co ntro l Latch Configuration T able ADDR Channel T ype DA T A7 DA T A6 DA T A5 D A T A4 DA T A3 DA T A2 DA T A1 DA T A0 Reset Va l u e 0 (0000b) A S 1 0 X X 0 0 R X R AT E A G L E N 0 1 0 111111 1 (0001b) A S SDASEL2A[1] SDASEL2A[0] SDASEL1A[1] SDASEL1A[0] X X TRGRA TEA GLEN ...
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Cypress CYV15G0404RB - page 17
CYV15G0404RB Document #: 38-02102 Rev . *C Page 17 of 27 JT AG Support The CYV15G0404RB contains a JT AG port to allow system level diagnosi s of device inte rconnect. Of the avai lable JT AG modes, boundary scan and bypass are supported. This capability is present only o n the L VTTL inputs and outputs and the TRGCLKx± cl ock input. The high-spee ...
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Cypress CYV15G0404RB - page 18
CYV15G0404RB Document #: 38-02102 Rev . *C Page 18 of 27 Figure 2. Receive BIST State Machine Receive BIST Detected LOW Monitor Data Received {BISTSTx, RXDx[0], No RX PLL Out of Lock Y es, {BISTSTx, RXDx[0], RXDx [1]} = BIST_DA T A_COMP ARE (000, 001) Compa re Next Character Auto-Abort Condition Mismatch End-of-BIST St a t e Y es, {BISTSTx, RXDx[0] ...
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Cypress CYV15G0404RB - page 19
CYV15G0404RB Document #: 38-02102 Rev . *C Page 19 of 27 Maximum Ratings Excedding maximum ratings may shorten the device life. User guidelin es are not teste d S torage T emp erature .............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... –55°C to +125°C S ...
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Cypress CYV15G0404RB - page 20
CYV15G0404RB Document #: 38-02102 Rev . *C Page 20 of 27 Differential CML Seri al Outputs: ROUT A1 ± , ROUT A2 ± , ROUTB1 ± , ROUTB2 ±, ROUTC1 ± , ROUTC2 ± , ROUTD1 ± , ROUTD2 ± V OHC Output HIGH V oltage (V CC Referenced) 100 Ω differential loa d V CC – 0.5 V CC – 0.2 V 150 Ω differential load V CC – 0.5 V CC – 0.2 V V OLC Outp ...
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Cypress CYV15G0404RB - page 21
CYV15G0404RB Document #: 38-02102 Rev . *C Page 21 of 27 Notes 14. T ested initially and af ter any design or process changes that may af fect these parameters, but not 100% tested. 15. The ratio of rise time to falling time must not vary by greater than 2:1. 16. For a given operating f requency , neither r ise nor fall speci fic ation can be great ...
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Cypress CYV15G0404RB - page 22
CYV15G0404RB Document #: 38-02102 Rev . *C Page 22 of 27 CYV15G0404RB Device RESET Char acteristics Over th e Ope rating Range t RST Device RESET Pulse Width 30 ns CYV15G0404RB Reclocker Serial Outp ut Characteristic s Over the Operating Range Parameter Description Condition Min. Max. Unit t B Bit T ime 5128 660 ps t RISE [14] CML Output Rise T ime ...
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Cypress CYV15G0404RB - page 23
CYV15G0404RB Document #: 38-02102 Rev . *C Page 23 of 27 Switching W aveforms for the CYV15G0404RB HOTLink II Receiver CYV15G0404RB HOTLink II Bus Configu ration Switching W aveforms RXCLKx+ RXDx[9:0] t RXDV+ t RXCLKP Receive Interface Read Timing RXRATEx = 0 RXCLKx– t RXDV – RXCLKx+ t RXDV+ t RXDV – t RXCLKP Receive Interface Read Timing RXR ...
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Cypress CYV15G0404RB - page 24
CYV15G0404RB Document #: 38-02102 Rev . *C Page 24 of 27 T able 6. Package Co ordinate Signal Allocation Ball ID Signal Name Signal T ype Ball ID Signal Name Signal T ype Ball ID Signal Name Signal T y pe A01 INC1– CML IN C07 ULCC L VTTL IN PU F17 VCC POWER A02 ROUTC1– CML OUT C08 GND GROUND F18 RXDB[0] L VTTL OUT A03 INC2– CM L IN C09 DA T A ...
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Cypress CYV15G0404RB - page 25
CYV15G0404RB Document #: 38-02102 Rev . *C Page 25 of 27 B20 ROU TB2+ CML OUT E18 VCC POWER L04 GND GROUND C01 TDI L VTTL IN PU E19 VCC POWER L17 RXDB[8] L VTTL OUT C02 TMS L VTTL IN PU E20 VCC POWER L18 RXCL KB+ L VTTL OUT C03 INSELC L VTTL IN F01 RXDC[8] L VTTL OUT L19 RXCL KB– L VTTL OUT C04 I NSELB L VTTL IN F02 RXDC[9] L VTTL OUT L20 GND GRO ...
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Cypress CYV15G0404RB - page 26
CYV15G0404RB Document #: 38-02102 Rev . *C Page 26 of 27 © Cypress Semico nductor Corpor ation, 2007. Th e information cont ained herein is subject to chan ge without not ice. Cypress Semico nductor Corporation assumes no resp on sibility for the use of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor does it convey or imp ...
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Cypress CYV15G0404RB - page 27
CYV15G0404RB Document #: 38-02102 Rev . *C Page 27 of 27 Document History Page Document Title: CYV15G0404RB Independent Cloc k Quad HOTLink II™ Deserializing Re clocker Document Number: 38 -02102 REV . ECN NO. ISS UE DA TE ORIG . OF CHANGE DESCRIPTION OF CHANGE ** 246850 See ECN FRE New Data Sheet *A 338721 See ECN SUA Added Pb-F ree package opti ...
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