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Manuel d’utilisation ARM CM940T

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  • ARM CM940T - page 1

    ARM DUI 0125A ARM Integrator/CM940T User Guide ...

  • ARM CM940T - page 2

    ii © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A ARM Integrator/CM940T User Guide © Copyri ght ARM L im ite d 199 9. All rights reserve d. Release information Proprietary notice ARM, the A RM Powe re d lo go, Thumb an d StrongARM are reg istered trad emarks of ARM Limited. The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, Mod ...

  • ARM CM940T - page 3

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. iii Electromagnetic conformity This section contains electromagnetic conformity (EMC) no tices. Federal Communications Commiss ion Notice NOTE: This equipment has been tested and found to comply with the limits for a class A digital device, p ursuant to par t 15 of the FCC r ules. Th ...

  • ARM CM940T - page 4

    iv © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A ...

  • ARM CM940T - page 5

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. v Contents ARM Integrator/CM9 40T Use r Guide Electromagn etic conf ormity ................ ............ ........... ........... ................. ........... ........... ... iii Prefac e About this docume nt ..................... ........... ........... ................. ........... ...

  • ARM CM940T - page 6

    vi © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.5 Reset c ontroller ..................... ........... ............ ........... ........... ................. ......... 3-8 3.6 System bus br idge ...... ........... ................. ........... ........... ............ ................ .. 3-11 3.7 Clock g enerators ........... ...

  • ARM CM940T - page 7

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. vii Preface This preface introdu ces the ARM Integrator/CM940T co re module and its refer ence documentatio n. It contains the following sections : • About this documen t on page viii • Further r eading on page x • Feedback on page xi. ...

  • ARM CM940T - page 8

    viii © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A About this document This documen t desc ribes ho w to se t up and u se th e ARM Integrat or/CM9 40T core module. Intended audience This document has been written for exp erienced hardware and software develope rs to aid the develo pment of AR M-based prod ucts us ing th e ARM I ...

  • ARM CM940T - page 9

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. ix T ypographical conventions The following typo graphical conventio ns are used in this do cument: bold Highlights ARM processor signal names within text, and interface elements such as menu names. May also be used for emphasis in descriptive lists where appr opriate. italic Highlig ...

  • ARM CM940T - page 10

    x © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Further reading This section lis ts related publications by ARM Lim ited and other compan ies th at may provide addit ional in for mation. ARM publications The followi ng publ ications provide i nformat ion ab out rel ated ARM p roducts and toolk its: • ARM740T T echnical Refer ...

  • ARM CM940T - page 11

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. xi Feedback ARM Lim ited welcomes feedback both on the ARM Integrator/CM940T co re mod ule and on the do cumentation. Feedback on this document If you hav e any comment s about this docum ent, please send email to errata@arm.com giving : • the documen t tit le • the docum ent num ...

  • ARM CM940T - page 12

    xii © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A ...

  • ARM CM940T - page 13

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-1 Chapter 1 Introduction This chapter introduces the ARM Integrator/CM940T core mo dule. It contains the follow ing sections: • About the ARM Integ rator/CM940 T cor e module on page 1-2 • ARM In tegrat or/CM94 0T over view on page 1-4 • Links and ind icat or s on page 1-8 ? ...

  • ARM CM940T - page 14

    Introduction 1-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1.1 About the ARM Integrator/CM940T core module The Integrator/CM94 0 T core module provides you with the b asis of a flexible developmen t system whi ch can be used in a number of different ways . With power and a simple connection to a Multi-I CE debugger, the cor ...

  • ARM CM940T - page 15

    Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-3 Figure 1-1 Inte grator/CM940T l ayout Multi-ICE connector Po w e r connector Processor core Reset button DIMM sock et Memory controller and system bus bridge (FPGA) SDRAM DIMM Core module/motherboard connectors HDRA Core module/motherboard connectors HDRB ...

  • ARM CM940T - page 16

    Introduction 1-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1.2 ARM Integrator/CM940T overview The major compo nents on the core mo dule are as follows: • ARM940T m icropr ocessor cor e • core modu le FPGA which implements : — SDRAM controller — sys tem bus b ridge — reset controller — interrupt cont roller — s ...

  • ARM CM940T - page 17

    Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-5 1.2.2 Core module FPGA The FPGA provides system control functions for the core module, enabling it to operate as a standalone development system or attached to a motherboar d. These functions are outlined in thi s section and des cribed in detail in Chapter 3 Hardwar ...

  • ARM CM940T - page 18

    Introduction 1-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Status and configuration space The status and configuration space co ntains status and configuration registers for the core module. These pro vide th e following information and control: • type of processor an d whether it has a cache, MMU, or pr otection unit • ...

  • ARM CM940T - page 19

    Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-7 1.2. 5 Mult i - ICE co nnec to r The Multi-ICE conn ector enables JTAG hardwar e debuggin g equipment, such as Multi-ICE, to be con nected to the core module. It is possible to both dr ive and sense the system- r eset line ( nSR ST ), and to drive JTAG reset ( nTRST ...

  • ARM CM940T - page 20

    Introduction 1-8 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1.3 Links and indi cators The core modu le provides one link an d four su rface-mounted LEDs. Th ese are illustrated in Figure 1-3. Figure 1-3 Li nks and indicato rs 1.3.1 CONFIG link The core modu le has only on e link, marked CONFIG. Th is is left open during norm ...

  • ARM CM940T - page 21

    Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-9 1.3.2 LED indicators The functio ns of the four surface-mo unted LEDs are summarized in Table 1- 1. Table 1-1 LE D funct ional summa ry Name Color Function MISC Green This LED is controll ed via the control regi ster (see CM_C TR L (0x1 00 0000C) on page 4- 1 1). FPG ...

  • ARM CM940T - page 22

    Introduction 1-10 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1.4 T est points The core modu le pro vides two gr ound and f ive signal t est poin ts as an aid to debug . These are illustrated in Figure 1-4 . Figure 1-4 T est points The functions of th e test points are summarized in Table 1 -2. Table 1-2 Test point functions ...

  • ARM CM940T - page 23

    Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-11 1.5 Precautions This section contains safety information and advice on how to avoid damage to the core module. 1.5.1 E nsuring safety Warning To avoid a safety hazard, only Safety Extra Lo w Voltage (SELV) equipment s ho uld be connected to the JTAG interface. 1.5.2 ...

  • ARM CM940T - page 24

    Introduction 1-12 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A ...

  • ARM CM940T - page 25

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 2-1 Chapter 2 Gett ing Sta r te d This chapter describes how to set up and prepare the ARM Integrato r/CM940T core module for use. It con tains the following sections: • Setting up a s tandal one ARM Integrat or/C M940T on page 2-2 • Attaching th e ARM Integrator/CM9 40T to a mot ...

  • ARM CM940T - page 26

    Getting Started 2-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 2.1 Setting up a standalone ARM Integrator/CM940T To set up the core module a s a standalone develop ment system: 1. Optionally , fit an SD RAM DIMM. 2. Suppl y po wer . 3. Connect Multi-ICE. 2.1.1 Fitting an SDRAM DIMM You shou ld fit the following type o f SDRA ...

  • ARM CM940T - page 27

    Getting Started ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 2-3 2.1.3 S upplying power When using the core modul e as a st andalon e de vel opm ent s ys tem, y ou should conn ect a bench power supp ly with 3 .3V and 5V outputs to the p ower connect or, as i llustrated in Figu re 2-1. Figure 2-1 Power connec tor Note This power ...

  • ARM CM940T - page 28

    Getting Started 2-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 2.1.4 Connecting Multi-ICE When you ar e using th e core mod ule as a stan dalone system , Multi-IC E debugg ing equipment can be u sed to download pr ograms. The Mu lti-ICE setup for a standalone cor e modu le is show n in F igur e 2-2 . Figure 2-2 Mu lti-ICE co ...

  • ARM CM940T - page 29

    Getting Started ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 2-5 2.2 Attaching the ARM Integrator/CM940T to a m otherboard Attach the core modu le onto a moth erboard ( for example, the AR M Integrator/SP) by engaging the connectors HDRA and HDRB on the bottom of the core module with the corresponding connectors on the top of t ...

  • ARM CM940T - page 30

    Getting Started 2-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 2.2.1 Core module ID The ID of the core module is configured autom atically by the connectors (there are no links to set) and depends on its p osition in the stack : • core module 0 is instal led first • core modu le 1 is install ed nex t, and canno t be fi t ...

  • ARM CM940T - page 31

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-1 Chapter 3 Hardware Description This chapter describes the on- board hardware. It contains the following sections: • ARM940T micr oprocessor co r e on pag e 3-2 • SSRAM contr oller on page 3-3 • Cor e m odule FPGA on page 3-4 • SDRAM contr oller on page 3-6 • Reset contr ...

  • ARM CM940T - page 32

    Hardware Description 3-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.1 ARM9 40T microproc es sor co re The ARM940T cached pr ocessor macrocell is a member of the ARM9 Thumb family of high- performan ce 32-bit system-on -a-chip pr ocesso rs. It p rovides the fo llowin g: • ARM9TDMI RISC int eger CP U • 4KB instruction an ...

  • ARM CM940T - page 33

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-3 3.2 SS RAM co ntroller The SSRAM controller is impl emented in a Xilinx 9572 PLD which enables the SSRAM to achieve single-cycle operation. In addition to controlling accesses to the SSRAM, the controller generates the processor response signals ( BWAIT , BER ...

  • ARM CM940T - page 34

    Hardware Description 3-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.3 Core module FPGA The core modu le FPGA contains five main functional blocks: • SDRAM contr oller on page 3-6 • Reset controller on page 3-8 • System bus bridg e on page 3-1 1 • Cor e module r egisters on pag e 4-7 • Debug int errupt co ntroller ...

  • ARM CM940T - page 35

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-5 At power-up the FPGA lo ads its co nfigurati on data fr om a flash memory devi ce. Parallel data from the flash is serialized by the Programmable L ogic Device (PLD) into the configu r atio n inputs of the FPGA. Fi gure 3-2 shows th e FP GA configur atio n me ...

  • ARM CM940T - page 36

    Hardware Description 3-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.4 SDRAM controlle r The core modu le pro vides supp ort fo r a single 16, 32, 64, 128, or 25 6MB SDRA M DIMM. 3.4.1 SDRAM operati ng mode The operating mode of the SDRAM devices is controlled with the mode set reg ister within each SDRAM. These registers a ...

  • ARM CM940T - page 37

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-7 a 64 x 32-bit area of memor y (CM_SPD) within the SDRAM controller. The SPD flag is set in the SDRAM contro l regis ter (CM_SDRAM) when the SPD data is available. This copy can be r andomly accessed at 0 x10000100 to 0x10000 1FC (see CM_SPD (0x100001 00 to 0x ...

  • ARM CM940T - page 38

    Hardware Description 3-8 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.5 Rese t controller The core mod ule FPGA incorporates a reset contr oller which enables the co re module to be reset as a standalone uni t or as part of an Integrator de velopment system. The core module can be reset fr om five sour ces: • reset button ...

  • ARM CM940T - page 39

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-9 3.5.1 Reset si gnals Table 3-1 describes t he external res et signal s. Table 3- 1 Reset signal d escription s Name Description T ype Function BnRES_M Processor r eset Output The BnRES_ M signal is u sed to reset the pr ocessor core. It is generated from nSRS ...

  • ARM CM940T - page 40

    Hardware Description 3-10 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.5.2 Software r esets The core module FPGA prov ides a software reset which can be trigg ered by writi ng to the reset bit in the CM _CTRL register. This generates the internal reset signal SWRST which generat es nSRS T an d resets the whole system (see C ...

  • ARM CM940T - page 41

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-11 3.6 System bus bridge The system bus bridge provides an asynchrono us bus interface between the local system bus and s ystem bu s connect ing the mother board and o ther mo dules. Inter-module accesses are su pported by two 16 x 74-bit FIFOs. Each o f the 16 ...

  • ARM CM940T - page 42

    Hardware Description 3-12 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Write transactions from the processor to the system bus normally complete o n the local memory bus in a single cycle. Th e data, address, and con trol information associated with the transfer are posted into FIFO, and the transfer on the system bus occurs s ...

  • ARM CM940T - page 43

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-13 3.6.2 Motherboard a ccesses to SDR AM The second FIFO supports read and write accesses by system bus masters on the motherboard a nd other co re modules to the local co re module m emory. System bus w rites The data routing for system bus writes to SDRAM is ...

  • ARM CM940T - page 44

    Hardware Description 3-14 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A System bus reads The data routing for sy stem bus reads from SDRAM is illust rated in Figure 3-7. Figure 3-7 System bu s reads from SDRAM For system bus reads, the address and control information also pass through the FIFO, but th e returned data fr om the ...

  • ARM CM940T - page 45

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-15 3.6.4 System bus signal routing The core module is mounted onto a motherboar d via the connectors HDRA and HDRB. As well as carrying all signal connection s between the boar ds, these provide mechanical mounting (s ee Attaching the ARM Integrat or/CM920T to ...

  • ARM CM940T - page 46

    Hardware Description 3-16 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A The example in Figure 3-8 illustrates how a group o f four signals (labelled A, B, C, and D) are routed throu gh a group of four con nector pins u p through t he stack. It highli ghts how signal C is rotated as it passes up through the stack an d only utili ...

  • ARM CM940T - page 47

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-17 3.7 Clock generators The core modu le provides its own cloc k generators an d operates asynchron ously with the mo therbo ard. T he cloc k gene rator pr ovide s two p r ogramm able c locks : • processor core clock CORECLK • processor local memory bus clo ...

  • ARM CM940T - page 48

    Hardware Description 3-18 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.7.1 Processor core clock (CO RECLK) The frequency of CORECLK is controllable in 1MHz steps in the range 12MHz to 160MHz. This is achieved by s etting the Vo ltage Contr olled Osci llator (VC O) di vider and output di vid er for the CORECLK generator via t ...

  • ARM CM940T - page 49

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-19 3.7.2 Processor bus cloc ks (LCLK and nLC LK) The frequency of the pr ocessor bus clocks LCL K and nLCLK is determined by the frequency of 2XCLK . The clock sign al 2XCLK is div ided by 2 by the SS RAM controller PLD to produce LCLK and nLCLK . The frequency ...

  • ARM CM940T - page 50

    Hardware Description 3-20 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A The LCLK clock si gnal is b uffered b y a 5-ou tput l ow-ske w buf fer PI49F CT3805 to drive five loads. These ar e: • SDRAM_CLK[3:0] •S S R A M _ C L K . The nLCLK clock si gnal is a phase-aligned inversion of the LC LK signal. It is buffered by a 5-ou ...

  • ARM CM940T - page 51

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-21 3.8 Multi-I CE support The core modu le provi des support for debug using JTAG. It pro vides a Multi -ICE connector and JTAG scan path s around the develo pment syst em. Figure 3- 10 shows t he Multi-ICE connector and the CONFIG link. Figure 3-10 JTAG conne ...

  • ARM CM940T - page 52

    Hardware Description 3-22 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.8.1 JT AG scan path Figure 3 -11 shows a simpli fied di agram of the scan pat h. Figure 3-11 J TAG scan pa th (simp lified) When the core module is used as a stand alone development system, the JTAG scan path is routed through the processor co re and back ...

  • ARM CM940T - page 53

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-23 3.8.2 De bugging modes The core modu le is capable of operating in two modes: • normal debug mode • confi guratio n mode. Normal debug mode During normal operation and software develop ment, the core module operates in debug mode. The deb ug mode is sele ...

  • ARM CM940T - page 54

    Hardware Description 3-24 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A The configuration mod e allows FPGA and PLD code to be updated as follows: • The FPGAs are volatile, bu t load their configuratio n from flash memory . Flash memo ry , wh ich itself does not ha ve a JT AG por t, can be pr ogram med by lo ading designs int ...

  • ARM CM940T - page 55

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-25 Table 3-4 J TAG signal descriptio n Name Description Function DBGR Q Debu g req ue s t (from JT AG equipment) DBGRQ is a request for the proc essor core to enter th e deb ug state. It is p rovided for compati bility with third-pa rty JT AG equipm ent. DBGACK ...

  • ARM CM940T - page 56

    Hardware Description 3-26 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A RTCK Return TCK (to JT AG equi pment) Some devi ces samp le TCK (for example a synthesizable core with only on e clock), and th is has the effect of delayin g t he t i me at which a com ponent ac t ually capture s data. RTCK is a mechanism fo r returnin g t ...

  • ARM CM940T - page 57

    Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-27 3.8.4 Debug communications interrupts The ARM940T processo r core incorpo rates EmbeddedICE h ardware and provides a debug commu nications data regi ster which i s used to pass dat a between the processo r and JTAG equipment. Th e processor accesses this reg ...

  • ARM CM940T - page 58

    Hardware Description 3-28 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A ...

  • ARM CM940T - page 59

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-1 Chapter 4 Programmer’s Reference This chapter describes the memory map and the status and control registers. It contains the following sectio ns: • Memory or ganizat ion on page 4-2 • Exception vector mapping on page 4-6 • Cor e module r egisters on p age 4 -7 • Interru ...

  • ARM CM940T - page 60

    Programmer’s R eference 4-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.1 Memory organization This section d escribes the memory map. Fo r a st and alone core module, the memo ry map is limited to local SS RAM, SD RAM, and core module regis ters. For the full memory ma p of an In tegrator deve lopmen t system, which inclu ...

  • ARM CM940T - page 61

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-3 Motherboard detect The nMBDET signal operates as follows: nMBDE T =0 T he core module is attached to a motherboard, and accesses in the address range 0x0 t o 0x3FF FF t o the boot ROM or SS RAM are controlled by the REMAP bit. nMBDE T =1 T he core module ...

  • ARM CM940T - page 62

    Programmer’s R eference 4-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.1.3 SDRAM acc esses The Integrator mem ory map prov ides a 256MB addr ess space for SDRAM. When a smaller sized S DRAM DIMM is fitted, it i s mapped repeatedly to fill the 25 6MB space. For example, a 64MB DIMM appears four times, as shown in Figure 4 ...

  • ARM CM940T - page 63

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-5 System bus acc esses to SDRAM If the core mod ule is mounted on a motherboard, the SDRAM is mapped to ap pear at the aliased mo dule memory region of t he combine d Integrator s ystem bus memo ry map. The SDRAM can be accessed by all b us masters at its ...

  • ARM CM940T - page 64

    Programmer’s R eference 4-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.2 Exception vect or mapping The convention f or ARM cores is to ma p the exception vector s to begin at add ress 0. However, the ARM940 T core al lows th e vectors to be moved to 0xFFFF000 0 by writing to the V b it in coprocessor 15 regis ter 1 (CP15 ...

  • ARM CM940T - page 65

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-7 4.3 Core m odule regist ers The core modu le status and control r egisters allow the processor to deter mine its environment and to control some core module operations. The r egisters, listed in Table 4-2, are located at 0 x1000000 0 and can only be acce ...

  • ARM CM940T - page 66

    Programmer’s R eference 4-8 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.3.1 CM_ID (0x10 000 000) The core module ID register (CM_ID) is a read- only register that identifies the bo ard manufacturer , board type, and r evis ion. Table 4-3 de scribes t he core mod ule ID regis ter bits . 4.3.2 CM_PR OC (0x1000 0004) The cor ...

  • ARM CM940T - page 67

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-9 4.3.3 CM_OSC (0 x10 000 008) The core module oscillator register (CM_OSC) is a read/write register that controls the frequ ency of the clo cks gene rated by the two clo ck ge nerators (see C lock generato rs on page 3- 17). In addition, it prov ides info ...

  • ARM CM940T - page 68

    Programmer’s R eference 4-10 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1 1 Reserved Use read-modify-write to preserv e value. 10:8 COREOD Read/write Core clock output divider: 000 = div ide by 10 001 = div ide by 2 (def au lt) 010 = div ide by 8 011 = divide by 4 100 = div ide by 5 101 = div ide by 7 1 10 = divi de by 9 1 ...

  • ARM CM940T - page 69

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-11 4.3.4 CM_CTRL (0x1000 000C) The core modu le control register (CM_CTRL) is a read/write re gister that pro vides control of a nu mber of user-configurable f eatures of the core mo dule. Table 4-5 describes t he core module co ntrol register bi ts. Table ...

  • ARM CM940T - page 70

    Programmer’s R eference 4-12 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.3.5 CM_ST A T (0x 10000010) The core modu le statu s re gister (CM_STAT) is a read -on l y r egister that can be read to determine where in a mu lti-core modu le stack this core m odule is positioned. Table 4-6 de scribes t he core mod ule status reg ...

  • ARM CM940T - page 71

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-13 4.3.6 CM_LOCK (0x1 0000014) The core modu le lock register (CM_LOCK) is a read/write register that is used to control access to the CM_OSC register , allowing it to be lo cked and unlocked. Th is mechanism prevents the C M_OSC register from being ove rw ...

  • ARM CM940T - page 72

    Programmer’s R eference 4-14 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.3.7 CM_SDRAM (0x10 000 020) The SDRAM status and co ntrol register ( CM_SDRAM) is a read/write r egister used to set the configuration parameters fo r the SDRAM DIMM. This control is necessary because of the variety o f module sizes and types availab ...

  • ARM CM940T - page 73

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-15 Note Before the SDRAM is used it is necessary to read the SPD memory and p rogram the CM_SDRAM register with the parameters indicated in Table 4-8. If these valu es are not correctly set then SDRAM accesses may be slow or unreliable. See CM _SPD (0x1000 ...

  • ARM CM940T - page 74

    Programmer’s R eference 4-16 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.3.8 CM_SPD (0x10 0001 00 to 0x100001 FC) This area of memory contain s a copy of the SPD data from the SPD EEPROM on the DIMM. Because accesses to the EEPROM are very slow, the data is copied to this memory during board initialization to allow faster ...

  • ARM CM940T - page 75

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-17 Example 4-1 CM_BASE EQU 0x10000000 ; base address of Core Module registers SPD_BASE EQU 0x10000100 ; base address of SPD information lightled ; turn on header LED and remap memory LDR r0, =CM_BASE ; load register base address MOV r1,#5 ; set remap and l ...

  • ARM CM940T - page 76

    Programmer’s R eference 4-18 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A not64 CMP r5,#0x80 ; is it 128MB? BNE not128 ; if no, move on MOV r6,#0xe ; store size and CAS latency of 2 B writesize not128 ; if it is none of these sizes then it is either 256MB, or ; there is no SDRAM fitted so default to 256MB. MOV r6,#0x12 ; sto ...

  • ARM CM940T - page 77

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-19 4.4 Interrupt register s The core module provides a 3-bit IRQ co ntroller and 3-bit F IQ controller to su pport the debug commu nications channel u sed for passin g informat ion between applicati ons software and the debu gger. The interru pt control re ...

  • ARM CM940T - page 78

    Programmer’s R eference 4-20 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Figure 4-4 I nterrupt contro l 4.4.1 CM_IRQ_ ST A T (0x10000040 )/CM_FIQ_ST A T (0x1 0000060) The status register con tains the logical AND of the bits in the raw status register and the enable register. 4.4.2 CM_IRQ_ RST A T (0x1000 0044)/CM_FI Q_RST ...

  • ARM CM940T - page 79

    Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-21 4.4.4 CM_IRQ_ENCLR( 0x1000004 C)/CM_FIQ_ENC LR (0x10000 06C) The clear set locations are used to set bits in the enable register as follows: • clear bits in the enabl e register by writing to the ENCLR locat ion for the required IRQ or F IQ controller ...

  • ARM CM940T - page 80

    Programmer’s R eference 4-22 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.4.6 CM_SOF T_I NTSET (0x10000 050)/CM_SO F T_ INTCL T (0x10000 054) The core module interrupt controller provides a register for controllin g and clearing software interrupts. This register is accessed using the software interrupt set and software in ...

  • ARM CM940T - page 81

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. A-1 Appendix A Signal Descriptions This index prov ides a summary of signals present on the cor e module main co nnectors. It contains the follo wing secti ons: • HDRA on page A-2 • HDRB on page A-4. Note For the Multi-ICE connector pinout and signal descrip tions see JTAG signal ...

  • ARM CM940T - page 82

    Signal Descriptions A-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A A.1 HDRA Figure A-1 shows th e pin number s of th e HDRA plug and s ocket. All pins on the HDRA socket are connected to the correspon ding pins on the HDRA p lug. 1A 0 GND 101 2 GND D0 102 3A 1 D1 103 4 A2 D2 104 5A 3 GND 105 6 GND D3 106 7A 4 D4 107 8 A5 D5 ...

  • ARM CM940T - page 83

    Signal Descriptions ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. A-3 The signals presen t on th e pins labeled A[31:0], B[31:0] , and C[31:0] are described in Table A-1. Note Table A-1 s hows signal descr iptio ns for an AMB A ASB bus i mplement ation . Table A-1 Bus bit assignme nt (for an AMBA ASB bus ) Pin label Name (ASB) D ...

  • ARM CM940T - page 84

    Signal Descriptions A-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A A.2 HDRB The HDRB plug an d socket have sli ghtly differ ent pin outs, as des cribed belo w. A.2.1 HDRB socket pinout Figure A-2 s hows the p in numbe rs of th e socket HDRB on the under side of th e core module, viewed from ab ove the core module. 1E 0 GND 6 ...

  • ARM CM940T - page 85

    Signal Descriptions ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. A-5 A.2.2 HDRB plug pinout Figur e A-3 shows t he pin number s of th e HDRB plug on the t op of th e core modul e. 1E 1 GND 61 2 GND F0 62 3E 2 F1 63 4 E3 F2 64 5E 0 GND 65 6 GND F3 66 7E 5 F4 67 8 E6 F5 68 9E 7 GND 69 10 GND F6 70 11 E 4 F7 71 12 E9 F8 72 13 E10 ...

  • ARM CM940T - page 86

    Signal Descriptions A-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A A.2.3 Through-board signal connections The signals on the pins labeled E[31:0] are cross-connected between the plug and socket so that the signals are rotated through the stack in groups of four. For example, the fir st block of four are conn ected as sh own ...

  • ARM CM940T - page 87

    Signal Descriptions ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. A-7 A.2.4 HDRB signal descriptions Table A-3 des cribes t he sig nals on t he pins labeled E[31:0], F[31: 0], and G[1 5:0]. Table A-3 HDRB sig nal description Pin label Name Descrip tion E[31 :28] SYSCLK[3 :0] System cloc k (ASB clock) to each co re modu le/exp an ...

  • ARM CM940T - page 88

    Signal Descriptions A-8 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Note Table A-3 shows signal descri ptions for an AMBA ASB bus imp lementati on. G4 TCK JT AG test clock G[3:1] MASTER[2: 0] Master ID. Binary enco ding of the mast er current ly perfo r ming a tra nsfer on th e bus. Correspond s to the mo dule ID and to the A ...

  • ARM CM940T - page 89

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. B-1 Appendix B Spe cifica tions This appendix contains the specifications fo r the ARM Integrator/CM940 T core module. It contains th e followin g sections: • Electrical sp ecification on page B-2 • T iming specification on page B-3 • Mechanic al d etails on page B-4. ...

  • ARM CM940T - page 90

    Specifications B-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A B.1 Electrical spec ification Table B-1 shows the core module electrical characteristics for the system bus interface. The core modu le uses 3.3V and 5 V source. The 1 2V inputs are supplied by the motherboard b ut not used by the core modu le. Table B-1 Core m od ...

  • ARM CM940T - page 91

    Specifications ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. B-3 B.2 T iming speci ficat ion Table B-2 provides the operating timing characteristics for the system bus interface signals. Table B-2 Core m odule tim ing (prelimina ry) Symbol Descri ption Min Max Uni ts F MAX Operating frequ ency - 2 5 MHz T CH Clock HIGH 19 - ns T ...

  • ARM CM940T - page 92

    Specifications B-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A B.3 Mechanical details The core module i s designed to be stackable on a num ber of different mothe rboards. Its size allows it to be m ounted onto a CompactPC I motherboard while allowin g the motherboard to be installed in a card cage. Figure B-1 shows the mecha ...

  • ARM CM940T - page 93

    ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. Index-i Index The items in this index are listed in alphab etic order, with symbols and numerics appear ing at the end. The references given are to page numbers. A Abou t th is book feed back xi typogr aph ical co nve ntions ix Access arbitration, SDRAM 3-6 Accesses boot ROM 4-2 SSRA ...

  • ARM CM940T - page 94

    Index Index-ii © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Connect ors HDRA and HDRB 1-3 Multi-ICE 2-4 power 2-3 Contro ller clock 1-6, 3 -17 reset 1-5, 3-8 SDRAM 1-5, 3-6 SSRAM 3-3 Contro llers FIQ 4-19 IRQ 4-19 Core module c ontrol register 4-11 Core module FPG A 1-5 Core module ID 2-6 Core module r egisters 4 -7 Core modu ...

  • ARM CM940T - page 95

    Index ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. Index-iii SDRAM op erating mo de 3-6 SDRAM re pe at mapp ing 4-4 SDRAM st atus and co ntrol regi ster 4 -14 SDRAM, SPD memory 4-16 Serial pre sence detec t 3-6 Setting CA S latency 4-1 5 Setting SDRAM size 4 -15 Set up power co nne ct ions 2-3 standalo ne 2-2 Soft ware int e rr ...

  • ARM CM940T - page 96

    Index Index-iv © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A ...

Fabricant ARM Catégorie Computer Hardware

Les documents que nous recevons du fabricant de l'appareilARM CM940T peuvent être divisés en plusieurs groupes. Ceux-ci sont, entre autres:
- dessins techniques ARM
- manuels d’utilisations CM940T
- fiches produit ARM
- dépliants
- ou étiquettes-énergie ARM CM940T
Tous sont importants, mais les informations les plus importantes du point de vue de l'utilisation de l'appareil se trouvent dans le manuel d’utilisation ARM CM940T.

Un groupe de documents appelé manuels d’utilisation est également divisé en types plus spécifiques, tels que: Manuels d’installation ARM CM940T, manuels d’entretien, brefs manuels ou manuels de l’utilisateur ARM CM940T. Selon vos besoins, vous devriez chercher le document dont vous avez besoin. Sur notre site, vous pouvez voir le manuel le plus populaire d’utilisation du produit ARM CM940T.

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Manuel d’utilisation complet de l’appareil ARM CM940T, quelle devrait-elle être?
Le manuel d’utilisation, également appelé le mode d’emploi, ou tout simplement le manuel, est un document technique destiné à aider à utiliser ARM CM940T par les utilisateurs. Des manuels sont généralement écrits par un rédacteur technique, mais dans un langage accessible à tous les utilisateurs ARM CM940T.

Le manuel d’utilisation complet ARM, devrait inclure plusieurs éléments de base. Certains d'entre eux sont moins importants, tels que: la couverture / page de titre ou pages d'auteur. Cependant, la partie restante, devrait nous fournir des informations importantes du point de vue de l'utilisateur.

1. Introduction et des conseils sur la façon d'utiliser le manuel ARM CM940T - Au début de chaque manuel, nous devrions trouver des indices sur la façon d'utiliser le document. Il doit contenir des informations sur l'emplacement de la table des matières ARM CM940T, FAQ ou des problèmes les plus fréquents - les points qui sont les plus souvent recherchés par les utilisateurs de chaque manuel
2. Table des matières - index de tous les conseils pour lARM CM940T qui peuvent être trouvés dans le document courant
3. Conseils sur la façon d'utiliser les fonctions de base de l’appareil ARM CM940T - qui devraient nous aider dans les premières étapes lors de l'utilisation ARM CM940T
4. Troubleshooting - séquence systématique des activités qui nous aideront à diagnostiquer et ensuite résoudre les principaux problèmes de ARM CM940T
5. FAQ - questions fréquemment posées
6. Détails du contact Informations sur l'endroit où chercher le contact avec le fabricant / service ARM CM940T dans un pays donné, si le problème ne peut être résolu par nous-mêmes.

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