-
Cypress CY7C1298H - page 1
1-Mbit (64K x 18) Pipelined DCD Sync SRAM CY7C1298H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05665 Rev . *B Revised July 5, 2006 Features • Registered inp uts and outputs for pipelined op er ation • Optimal for pe rformance (Double-Cy cle deselect) — Depth exp an ...
-
Cypress CY7C1298H - page 2
CY7C1298H Document #: 38-05665 Rev . *B Page 2 of 16 Functional Block Diagram ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSC BW B BW A CE 1 DQ B, DQP B BYTE WRITE REGISTER DQ A , DQP A BYTE WRITE REGISTER ENABLE REGISTER OE SENSE AMPS MEMORY ARRAY ADSP 2 A [1:0] MODE CE 2 CE 3 GW BWE PIPELINED ENABLE DQ s, DQP A DQP B OUTPUT REGIST ...
-
Cypress CY7C1298H - page 3
CY7C1298H Document #: 38-05665 Rev . *B Page 3 of 16 Pin Configurations 100-Pin TQFP To p V i e w A NC NC V DDQ V SSQ NC DQP A DQ A DQ A V SSQ V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A NC NC V SSQ V DDQ NC NC NC NC NC NC V DDQ V SSQ NC NC DQ B DQ B V SSQ V DDQ DQ B DQ B V DD NC V SS DQ B DQ B V DDQ V SSQ DQ B DQ B DQP B NC V S ...
-
Cypress CY7C1298H - page 4
CY7C1298H Document #: 38-05665 Rev . *B Page 4 of 16 Pin Descriptions Pin T ype Description A0, A 1 , A Input- Synchronous Address Inputs used to select one of the 64K add ress locations . Sampled at the rising edg e of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A [1:0] are fed to the two-bit counter . BW ...
-
Cypress CY7C1298H - page 5
CY7C1298H Document #: 38-05665 Rev . *B Page 5 of 16 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled b y the rising edge of the clock. The CY7C1298H supports secondary cache in systems utilizing either a linear or interleave ...
-
Cypress CY7C1298H - page 6
CY7C1298H Document #: 38-05665 Rev . *B Page 6 of 16 Interleaved ‘Burst Address T able (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 1 1 01 00 1 1 10 10 1 1 00 01 1 1 10 01 00 Linear Burst Address T ab le (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Addre ...
-
Cypress CY7C1298H - page 7
CY7C1298H Document #: 38-05665 Rev . *B Page 7 of 16 T ruth T able for Read/W rite [2,3] Function GW BWE BW A BW B Read H H X X Read H L H H Write byte A – (DQ A and DQP A )H L L H Write byte B – (DQ B and DQP B )H L H L Write all bytes H L L L Write all bytes L X X X ZZ Mode Electrical Characteristics Parameter Description T est Conditions Min ...
-
Cypress CY7C1298H - page 8
CY7C1298H Document #: 38-05665 Rev . *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ................. .............. .... –65°C to + 150° Ambient T e mperature with Power Applied ........... ............................ ..... –55°C to + 125°C Supply V o ...
-
Cypress CY7C1298H - page 9
CY7C1298H Document #: 38-05665 Rev . *B Page 9 of 16 Cap acit ance [9] Parameter D escrip tion T est Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5p F C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Characteristics [9] Parameter Description T est Cond itions 1 ...
-
Cypress CY7C1298H - page 10
CY7C1298H Document #: 38-05665 Rev . *B Page 10 of 16 Switching Characteristics Over the Operating Range [14, 15] Parameter Description 166 MHz 133 MHz Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the first Access [10] 11 m s Clock t CYC Clock Cycle T ime 6.0 7.5 ns t CH Clock HIGH 2.5 3.0 ns t CL Clock LOW 2.5 3.0 ns Output Times t CO Data ...
-
Cypress CY7C1298H - page 11
CY7C1298H Document #: 38-05665 Rev . *B Page 1 1 of 16 Switching W aveforms Read Timing [16] Note: 16. On this diagra m, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES G W, BWE,BW Data Out (Q) Hi ...
-
Cypress CY7C1298H - page 12
CY7C1298H Document #: 38-05665 Rev . *B Page 12 of 16 Wri te Tim i n g [16, 17] Note: 17. Full width write can be initia ted by either GW LOW; or by GW HIGH, BWE LOW and BW [A:B] LOW. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW [A:B] ADV BURST READ BURST WRITE D(A2) D(A2 ...
-
Cypress CY7C1298H - page 13
CY7C1298H Document #: 38-05665 Rev . *B Page 13 of 16 Read/Write T iming [16, 18, 19] Notes: 18. The data bus (Q) rema ins in High-Z foll owing a WRITE cycle, unless a new read access initiated by ADSP or ADSP . 19. GW is HIGH. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CES Data Out ...
-
Cypress CY7C1298H - page 14
CY7C1298H Document #: 38-05665 Rev . *B Page 14 of 16 ZZ Mode T iming [20, 21] Notes: 20. Device must be deselected when entering ZZ mode. See tru th ta ble for all possible signal conditions to deselect t he device. 21. I/Os are in High -Z when exiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS (except ...
-
Cypress CY7C1298H - page 15
CY7C1298H Document #: 38-05665 Rev . *B Page 15 of 16 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do ...
-
Cypress CY7C1298H - page 16
CY7C1298H Document #: 38-05665 Rev . *B Page 16 of 16 Document History Page Document Title: CY7C1298H 1-Mbit (64K x 18) Pipelined DCD Sync SRAM Document Number: 38-05665 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 3438 96 See ECN PCI New Data Sheet *A 430678 See ECN NXR Changed address of Cypress Semicond uctor Corporation on ...
Hai una domanda su Cypress CY7C1298H?
Utilizza il modulo sottostante
Se non hai risolto il problema con Cypress CY7C1298H con l'aiuto del manuale che hai trovato, fai una domanda utilizzando il modulo sottostante. Se un utente ha avuto un problema simile con Cypress CY7C1298H è probabile che voglia condividere il modo di risolverlo.