-
Samsung M471B1G73AH0 - page 1
- 1 - M471B1G73AH0 Rev . 1.0, Jul. 2010 SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMA TION AND SPECIFICA TIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference pur poses only . All info rmation discussed herein is provided on an "AS IS" basis, without warra nties of any kind. This documen ...
-
Samsung M471B1G73AH0 - page 2
- 2 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 Rev ision History Revision No. History Draft Date Remark Editor 1.0 - First Release Jul. 2010 - S.H.Kim ...
-
Samsung M471B1G73AH0 - page 3
- 3 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 Table Of Contents 204pin Unbuffered SODIMM based on 4Gb A-die 1. DDR3 Unbuffered SODIMM Ordering Information .......................................... ....................................... ...... ................. 4 2. Key Features ......... ................. .................... ........... ...
-
Samsung M471B1G73AH0 - page 4
- 4 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 1. DDR3 Unbuff ered SODIMM Order ing Inf ormation NOTE : 1. "##" - F8/H9 2. F8 - 1066Mbps 7-7-7 & H9 - 1333Mbp s 9-9-9 - DDR3-1333(9-9-9) is backward compatib le to DDR3-1066(7-7-7) 2. Key F eatures • JEDEC standard 1.5V ± 0.075V Power Supply •V DDQ = 1.5V ± 0.075V • 400 M ...
-
Samsung M471B1G73AH0 - page 5
- 5 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 4. x64 DIMM Pin Configurations (F ront side/B ack Side) NOTE : 1. NC = No Connect, NU = Not Used, R FU = Reserved Future Use 2. TEST(pin 125) is reserved for bus analysi s probes and is NC on normal memory modul es. 3. This address might be connected to NC balls of the DRAMs (depen ding on dens ...
-
Samsung M471B1G73AH0 - page 6
- 6 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 5. Pin Descr iption NOTE: * The V DD and V DDQ pins are tied commo n to a si ngle po wer-plane on these designs. Pin Name Description Number Pin Name Description Number CK0, CK1 Clock Inputs, positive line 2 DQ0-DQ63 Data Input/Output 64 CK 0, CK 1 Clock Inputs, negative line 2 DM0-DM7 Data Mas ...
-
Samsung M471B1G73AH0 - page 7
- 7 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 6. Input /Output F uncti onal Description Symbol Ty p e Function CK0-CK1 CK0 -CK1 Input The system clock inputs. All address and command lines are sampled on the cross point of the rising edg e of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is dr iven from the clock inputs an d ...
-
Samsung M471B1G73AH0 - page 8
- 8 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 7. F uncti on Block Diagram: 7.1 8GB, 1Gx64 Module (Popu lated as 2 ranks of x8 DDR3 SDRAMs) V7 V8 V5 S1 RAS CAS WE CK1 CK1 CKE1 ODT1 A[0:N] /BA[0:N] S0 CK0 CK0 CKE0 ODT0 DQS3 DQS3 DM3 DQS DQS D1 1 CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[ N:0] ZQ DQ[0: 7] DM 240 Ω ± 1% DQ[24:31] D3 CS RAS CAS W ...
-
Samsung M471B1G73AH0 - page 9
- 9 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 8. Abso lute Maximum Ratings 8.1 Abso lute Maximum DC Ratings NOTE : 1. S tresses greater th an those listed under “A bsolute Maximum Rating s” may cause p ermanent damage to the d evice. This is a stre ss rating o nly and functional operation of the device at these or an y other conditions ...
-
Samsung M471B1G73AH0 - page 10
- 10 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10. AC & DC Input Measurement Levels 10.1 AC & DC Logic Input Leve ls for Single-ended Signals [ T abl e 1 ] Single-ended AC & DC in put levels for Command and Address NOTE : 1. For input o nly pins except RESET , V REF = V REFCA (DC) 2. See ’Overshoot/Undershoo t S pecification? ...
-
Samsung M471B1G73AH0 - page 11
- 11 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10.2 V REF T olerances. The dc-tolerance limits and ac-noise limits for the reference voltages V REFCA and V REFDQ are illustrate in Figure 1. It shows a valid reference voltage V REF (t) as a function of time. (V REF stands for V REFCA and V REFDQ like wise). V REF (DC) is the linear average ...
-
Samsung M471B1G73AH0 - page 12
- 12 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10.3 AC and DC Logic Input Levels f or Diff erential Signals 10.3.1 Diff erential Signa ls Definition Figure 2. Definition of dif ferential ac-swing and "time above ac leve l" tDV AC 10.3.2 Differential Swing Requirement for Clock (CK - CK ) and Strobe (DQS- DQS ) NOTE : 1. Used to d ...
-
Samsung M471B1G73AH0 - page 13
- 13 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK , DQS ) has also to comply with cert ain requirements for single-ended signals. CK and CK have to approximately reach V SEH min / V SEL max (approximately equal to the ac-l ...
-
Samsung M471B1G73AH0 - page 14
- 14 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10.3.4 Different ial Input Cross Poi nt Voltage T o guarantee t ight setup and hold time s as well as output skew para meters wit h respect to clock and strobe, each cross point vo ltage of differential input signals (CK, CK and DQS, DQS ) must meet the requir ements in below table. The differ ...
-
Samsung M471B1G73AH0 - page 15
- 15 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 11. AC & DC Output Measurement Levels 11.1 Single Ended AC and DC Output Lev els [ T abl e 7 ] Single Ended AC and DC out put levels NOTE : 1. The swing of +/-0.1 x V DDQ i s based on approximately 50% of the static sin gle ended output high or low swing with a driver impedance of 40 Ω an ...
-
Samsung M471B1G73AH0 - page 16
- 16 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 11.4 Diff erential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V OLdiff (AC) and V OH- diff (AC) for differential signals as shown in below . [ T abl e 1 1 ] Differential Output slew rate defini ...
-
Samsung M471B1G73AH0 - page 17
- 17 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 12. DIMM IDD specification definition Symbol Description IDD0 Operating One Bank Active-Precharge Cur rent CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Da tasheet for det ail patt ern ; BL : 8 1) ; AL : 0; CS : High between ACT and PRE; Command, Address, Bank Address I ...
-
Samsung M471B1G73AH0 - page 18
- 18 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1, 0]=00B 2) Output Buf fer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01 B; R TT_Nom enable: set MR1 A[9,6,2] = 01 1B; RTT_Wr en able: set MR2 A[10,9] = 10B 3) Precharge Power Down Mode: set MR0 A12=0 B for Slow Exit or MR0 A12=1B for Fast ...
-
Samsung M471B1G73AH0 - page 19
- 19 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 13. IDD SPEC T ab le M471B1G73AH0 : 8 GB (1Gx64) Module NOTE : 1. DIMM IDD SPEC is calculated with consid ering de-actived rank(IDLE) is IDD2N. Symbol CF8 (DDR3-1066@CL=7) CH9 (DDR3-1333@CL=9) Unit NOTE IDD0 600 680 mA 1 IDD1 720 800 mA 1 IDD2P0(slow exit) 240 240 mA IDD2P1(fast exit) 320 320 ...
-
Samsung M471B1G73AH0 - page 20
- 20 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 14. Input /Output Capacitance 14.1 2Rx8 2G B SODIMM Parameter Symbol M471B1G73AH0 Unit s NOTE DDR3-1066 DDR3-1333 Min Max Min Max Input/output capacitance (DQ, DM, DQS, DQS , TDQS, TDQS ) CIO - TBD - TBD pF Input capacitance (CK and CK) CCK - TBD - TBD pF Input capacitance (All other input-onl ...
-
Samsung M471B1G73AH0 - page 21
- 21 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 15. E lectric al Char acteristics and AC timing (0 ° C<T CASE ≤ 95 ° C, V DDQ = 1.5V ± 0.075V; V DD = 1.5V ± 0.075V) 15.1 Refresh Par ameters by Dev ice Density NOTE : 1. Users should refer to the DRAM supplier data sheet and/or t he DIMM SPD to determine if DDR3 SDRAM devices support ...
-
Samsung M471B1G73AH0 - page 22
- 22 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ T abl e 14 ] DDR3-1066 Speed Bins Speed DDR3-1066 Units NOTE CL-nRCD-nRP 7 - 7 - 7 Parameter Symbol min max Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 - ns PRE command period tRP 13.125 - ns ACT to ACT or REF command period tRC 5 ...
-
Samsung M471B1G73AH0 - page 23
- 23 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ T abl e 15 ] DDR3-1333 Speed Bins Speed DDR3-1333 Units NOTE CL-nRCD-nRP 9 -9 - 9 Parameter Symbol min max Internal read command to first data tAA 13.5 (13.125) 8 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125) 8 - ns PRE command period tRP 13.5 (13.125) 8 - ns ACT to ACT o ...
-
Samsung M471B1G73AH0 - page 24
- 24 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ T abl e 16 ] DDR3-1600 Speed Bins Speed DDR3-1600 Units NOTE CL-nRCD-nRP 11-11 -11 Parameter Symbol min max Internal read command to first data tAA 13.75 (13.125) 8 20 ns ACT to internal read or write delay time tRCD 13.75 (13.125) 8 - ns PRE command period tRP 13.75 (13.125) 8 - ns ACT to A ...
-
Samsung M471B1G73AH0 - page 25
- 25 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 15.3.1 Speed Bin T able Notes Absolute S pecification (T OPER ; V DDQ = V DD = 1.5V +/- 0.075 V); NOTE : 1. The CL setting and CWL setting result in tCK(A VG).MIN and tCK(A VG).MAX requ irements. When making a selection of tCK(A VG), bo th need to be fulfilled: Requirements from CL setting as ...
-
Samsung M471B1G73AH0 - page 26
- 26 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 16. T iming P arameters by Speed Gr ade [ T abl e 17 ] Timing Parameters by Speed Bin Speed DDR3-80 0 DDR3-1066 DDR3-1333 DDR3 -1600 Units NOTE Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX Clock Timing Minimum Clock Cycle Time (DL L off mode) tCK(DLL_OF F) 8 - 8 - 8 - 8 - ns 6 Average Cloc ...
-
Samsung M471B1G73AH0 - page 27
- 27 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ Table 17 ] Timing Parame ters by Speed Bin (Cont.) Speed DDR3-800 DDR3-1066 DDR 3-1333 DDR3-1600 Units NOTE Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX Command and Address Timing DLL locking time tDLLK 512 - 512 - 512 - 512 - nCK internal READ Command to PRECHARGE C ommand delay tRTP ma ...
-
Samsung M471B1G73AH0 - page 28
- 28 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ T abl e 17 ] Timing Parameters by Speed Bin (Cont.) Speed DDR3-800 DDR3-1066 DDR3-1 333 DDR3-1600 Units NOTE Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX Power Down Timing Exit Power Down with DLL on to an y valid com- mand;Exit Precha rge Power Down with DLL frozen to co mmands not req ...
-
Samsung M471B1G73AH0 - page 29
- 29 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 16.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input cl ock under operation. Unit ’nCK’ r epresents one clock cycle of the input clock, counting the actual clock edges .ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at ...
-
Samsung M471B1G73AH0 - page 30
- 30 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 16.2 T iming P arameter Not es 1. Actual val ue dependant upo n measuremen t level defini tions which are TBD. 2. Commands requ iring a locked DL L are: READ (and RAP) an d synchronous ODT co mmands. 3. The max value s are system dep endent. 4. WR as programmed in mode register 5. Value must b ...
-
Samsung M471B1G73AH0 - page 31
- 31 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 17. Physical Dimensions : 17.1 512Mx8 based 1Gx64 Module (2 Ranks) - M471B1G73AH0 The used device is 512M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B4G0846A - HC** * NOTE : T olerances on all dimensions ±0.15 unless otherwise specified. 0.25 MAX 2.55 Deta il B Deta il A 1.00 ± 0.10 0.45 ± ...
Hai una domanda su Samsung M471B1G73AH0?
Utilizza il modulo sottostante
Se non hai risolto il problema con Samsung M471B1G73AH0 con l'aiuto del manuale che hai trovato, fai una domanda utilizzando il modulo sottostante. Se un utente ha avuto un problema simile con Samsung M471B1G73AH0 è probabile che voglia condividere il modo di risolverlo.