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Manuale per l’uso Cypress CY7C1372D

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Summary
  • Cypress CY7C1372D - page 1

    18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture CY7C1370D CY7C1372D Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05555 Rev . *F Revised June 28, 2006 Features • Pin-comp atible and functionally equiv a le nt to ZBT™ • Supports 250-MHz bus operati ...

  • Cypress CY7C1372D - page 2

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 2 of 28 Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access T ime 2.6 3.0 3.4 ns Maximum Operating Curren t 350 300 275 mA Maximum CMOS S tandby Cu rrent 70 70 70 mA A0, A1, A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQs DQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S ...

  • Cypress CY7C1372D - page 3

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A CE 1 CE 2 BW a CE 3 V DD V SS CLK WE CEN OE A A ...

  • Cypress CY7C1372D - page 4

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 4 of 28 Pin Configurations (continued) 234 5 6 7 1 A B C D E F G H J K L M N P R T U DQ a V DDQ NC/576 M NC/1G DQ c DQ d DQ c DQ d AA A A AV DDQ CE 2 A V DDQ V DDQ V DDQ V DDQ NC/144 M NC A DQ c DQ c DQ d DQ d TMS V DD A NC/72M DQP d A A ADV/LD AC E 3 NC V DD AA N C V SS V SS NC DQP b DQ b DQ b ...

  • Cypress CY7C1372D - page 5

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 5 of 28 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE V SS V SS V SS V SS V DDQ V SS V DD V SS V SS V SS NC V ...

  • Cypress CY7C1372D - page 6

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 6 of 28 Pin Definitions Pin Name I/O T ype Pin Description A0 A1 A Input- Synchronous Address Inputs used to select one of the addres s locations . Sa mpled at the rising e dge of the CLK. BW a BW b BW c BW d Input- Synchronous Byte Write Select Input s, active LOW . Qualified with WE to conduc ...

  • Cypress CY7C1372D - page 7

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 7 of 28 Introduction Functional Overview The CY7C1370D and C Y7C1372D are synchronous-pipeli ned Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transi tions. All synchronous input s pass through input registers co ntrolled by the rising ed ge of the clock. The ...

  • Cypress CY7C1372D - page 8

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 8 of 28 Asserting the Write Enable input (WE ) with the selected Byte Write Select (BW ) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed w rite mechanism has been provided to simplify the wr ...

  • Cypress CY7C1372D - page 9

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 9 of 28 Notes: 1. X = “Don't Care”, H = Lo gic HIGH, L = Logic L OW , CE stands fo r ALL Chip Ena bles active. BWx = L signifies at least one Byte W rite Select is active, BW x = V alid signifies that the desired byte writ e selects are as se rted, see Write Cycle Description table for ...

  • Cypress CY7C1372D - page 10

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 10 of 28 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1370D) WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Wri te Byte a – (D Q a and DQP a ) L HHH L Wri te Byte b – (D Q b and DQP b )L H H L H Write Bytes b, a L H H L L Write Byte c – (DQ c and ...

  • Cypress CY7C1372D - page 11

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 1 1 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1370D/CY7C1372D incorpora tes a serial boundary scan test access por t (T AP). This p art is fully compliant with 1 149.1. The T AP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1370D/CY7C1372 D contains a T AP c ...

  • Cypress CY7C1372D - page 12

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 12 of 28 When the T AP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board -level serial test data path. Byp ass Register T o save time when serial ly shifting data through registers, it is som ...

  • Cypress CY7C1372D - page 13

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 13 of 28 in the T AP controller , i t will directly control the state of the output (Q-bus) pins, when t he EXTEST is entered as the current instruction. When HIGH, it will e nable the output buffers to drive the output bus. When LOW , this bit will place the output bus into a High-Z condition. ...

  • Cypress CY7C1372D - page 14

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 14 of 28 3.3V T AP AC T est Conditions Input pulse levels ... ............... .............. .............. .. V SS to 3.3V Input rise and fall times ......... ........ ........... ... ........... ... ...... 1 ns Input timing referenc e levels .................... ........... ............1.5V O ...

  • Cypress CY7C1372D - page 15

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 15 of 28 Identification Register Definitions Instruction Field CY7C137 2D CY7C1370D Description Revision Number (31:29) 000 000 Reserved for version number . Cypress Device ID (28:12) [12] 0101 1001000100101 0101 1001000010101 Reserved for future use. Cypress JEDEC ID (1 1:1) 000001 10100 00000 ...

  • Cypress CY7C1372D - page 16

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 16 of 28 1 19-Ball BGA Boundary Scan Order [13, 14] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2T 4 2 4 E 7 4 6 A 4 6 8 M 2 3T 5 2 5 D 7 4 7 G 3 6 9 N 1 4T 6 2 6 H 7 4 8 C 3 7 0 P 1 5R 5 2 7 G 6 4 9 B 2 7 1 K 1 6L 5 2 8 E 6 5 0 B 3 7 2L 2 7R 6 2 9 D 6 5 1 A 3 ...

  • Cypress CY7C1372D - page 17

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 17 of 28 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N 6 3 1 D 1 0 6 1G 1 2N 7 3 2 C 1 1 6 2 D 2 3N 1 0 3 3 A 1 1 6 3 E 2 4P 1 1 3 4 B 1 1 6 4 F 2 5P 8 3 5 A 1 0 6 5G 2 6R 8 3 6 B 1 0 6 6 H 1 7R 9 3 7 A 9 6 7 H 3 8P 9 3 8 B 9 6 8 J 1 9P 1 0 3 9 C 1 0 6 9 ...

  • Cypress CY7C1372D - page 18

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 18 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T e mperature ............. .............. ...... –65 °C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... –55 °C to +125°C ...

  • Cypress CY7C1372D - page 19

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 19 of 28 Note: 18. T ested initially and af ter any design or proc ess chan ge that may affect these p arameters. Cap acit ance [18] Parameter Description T est Conditions 1 00 TQ FP Max. 1 19 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V . V DDQ = 2.5 ...

  • Cypress CY7C1372D - page 20

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 20 of 28 Switching Characteristics Over the Operating Range [23, 24] Parameter Descriptio n –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [19] V CC (typical) to the first access read or write 1 1 1 ms Clock t CYC Clock Cycle T ime 4.0 5 6 ns F MAX Maximum Operating Frequency 2 ...

  • Cypress CY7C1372D - page 21

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 21 of 28 Switching W aveforms Read/Wri te/Timing [25, 26, 27] Notes: 25. For this waveform ZZ is tied LOW. 26. When C E is LOW, CE 1 is LOW , C E 2 is HIGH and CE 3 is LOW . When CE is HIGH,CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 27. Order of the Burst sequ ence is determined by the statu ...

  • Cypress CY7C1372D - page 22

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 22 of 28 Notes: 28. The Ignore Clock Edge or St all cycle (Clock 3) illustrated CEN being used to create a p ause. A write is not perfor m ed durin g this cycle. 29. Device must be deselected when entering ZZ mode. See cycle descr ipt ion table for all possible signal co nditions to deselect th ...

  • Cypress CY7C1372D - page 23

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 23 of 28 Ordering Information Not all of the spe ed, package and temperature ran ges are available. Please contact your local sales r epresentative or visit www .cypress.com for actual pro duct s offered. Speed (MHz) Ordering Code Packa ge Diagram Part and Packa ge T ype Operating Range 167 CY7 ...

  • Cypress CY7C1372D - page 24

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 24 of 28 250 CY7C1370D-250AXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1372D-250AXC CY7C1370D-250BGC 51-851 15 1 1 9-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372D-250BGC CY7C1370D-250BGXC 51-851 15 1 1 9-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-F ...

  • Cypress CY7C1372D - page 25

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMAT ...

  • Cypress CY7C1372D - page 26

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 26 of 28 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.00(3X) REF. 7.62 22.00±0.20 14.00±0.20 1.27 0.60±0.10 C 0.15 C B A 0.15(4X) Ø0.05 M C Ø0.75±0 ...

  • Cypress CY7C1372D - page 27

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 27 of 28 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod u ...

  • Cypress CY7C1372D - page 28

    CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 28 of 28 Document History Page Document Title: CY7C1372D/CY7C1370D 18-Mbit (512 K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05555 REV . ECN No. Issue Date Orig. of Change Description of Chang e ** 254509 See ECN RKF New data sheet *A 276690 See ECN VBL C hang ed ...

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Tutti sono importanti, ma le informazioni più importanti dal punto di vista di utilizzo del dispositivo possono essere trovate nel manuale per l’uso Cypress CY7C1372D.

Un gruppo di documenti denominato manuali per l’uso, è anche suddiviso in tipi più specifici, come: Manuali di installazione Cypress CY7C1372D, manuali di manutenzione, brevi manuali o manuali utente Cypress CY7C1372D. A seconda delle esigenze, si dovrebbe cercare il documento necessario. Nel nostro sito web, puoi visualizzare il manuale più popolare per l'uso del prodotto Cypress CY7C1372D.

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Il manuale per l’uso, denominato anche istruzioni per l’uso, o semplicemente il manuale è un documento tecnico progettato per aiutare ad utilizzare Cypress CY7C1372D dagli utenti. I manuali sono di solito scritti da uno scrittore tecnico, ma in un linguaggio accessibile a tutti gli utenti Cypress CY7C1372D.

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