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Manuale per l’uso Cypress CY7C1426JV18

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  • Cypress CY7C1426JV18 - page 1

    36-Mbit QDR™-II SRAM 4-W ord Burst Architecture CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-12557 Rev . *C Revised June 25, 2008 Features ■ Separate independent read and write data ports ❐ Supports concurrent ...

  • Cypress CY7C1426JV18 - page 2

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 2 of 28 Logic Block Diagra m (CY7C141 1JV18) Logic Block Diagram (CY7C1426JV18) 1M x 8 Array CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 16 20 32 8 NWS ...

  • Cypress CY7C1426JV18 - page 3

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 3 of 28 Logic Block Diagram (CY7C1413JV18) Logic Block Diagram (CY7C1415JV18) CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 36 19 72 18 BWS [1:0] V REF ...

  • Cypress CY7C1426JV18 - page 4

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 4 of 28 Pin Configuration The pin configuration for CY7C141 1JV18, CY7C1413JV18, and CY7C1415JV18 follows. [1] 165-Ball FBGA (15 x 17 x 1 .4 mm) Pinout CY7C141 1JV18 (4M x 8) 123456789 10 11 A CQ NC/72M A WPS NWS 1 K NC/144M RPS AA C Q B NC NC NC A NC/28 ...

  • Cypress CY7C1426JV18 - page 5

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 5 of 28 CY7C1413JV18 (2 M x 18) 123456789 10 11 A CQ NC/144M A WPS BWS 1 K NC/288M RPS A NC/72M CQ B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AN CA V SS NC Q7 D8 D NC D1 1 Q10 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V SS V SS ...

  • Cypress CY7C1426JV18 - page 6

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 6 of 28 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C141 1JV18 − D [7:0] CY7C1426JV18 − D [8:0] CY7C1413JV18 − D ...

  • Cypress CY7C1426JV18 - page 7

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 7 of 28 CQ Echo Clock CQ is Referenced With Respect to C . This is a free running clock and is synchroni zed to the input clock for output data (C) of the QDR-II. In the single clock mode , CQ is generated wi th respect to K. The timing s for the echo cl ...

  • Cypress CY7C1426JV18 - page 8

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 8 of 28 Functional Overview The CY7C141 1JV18, CY7C14 26JV18, CY7C1413JV18, and CY7C1415JV18 are synchronous pipe lined burst SRAMs with a read port and a write port. The read port is dedicated to rea d operations and the write port is dedicated to write ...

  • Cypress CY7C1426JV18 - page 9

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 9 of 28 includes forwarding data from a write cycle that was initiated on the previous K clock rise. Read accesses and w rite access must be scheduled such that one transaction is initiated on an y clock cycle. If both ports are selected on the same K cl ...

  • Cypress CY7C1426JV18 - page 10

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 10 of 28 T ruth T able The truth table for CY7C141 1JV18, CY7C1426 JV1 8, CY7C1413JV18, and CY7C1415JV18 follow s. [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ DQ DQ Write Cycle: Load address on the rising edge of K; input write data on two consecutive K ...

  • Cypress CY7C1426JV18 - page 11

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 1 1 of 28 Write Cycle Descriptions The write cycle description tabl e for CY7C1426JV18 follows. [2, 10] BWS 0 K K L L–H – During the data portion of a write sequence, the single b yte (D [8:0] ) is written into the device. L – L–H Du ring the dat ...

  • Cypress CY7C1426JV18 - page 12

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 12 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.1 -2001. The T AP operates using JEDEC standard 1.8V ...

  • Cypress CY7C1426JV18 - page 13

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 13 of 28 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the ...

  • Cypress CY7C1426JV18 - page 14

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 14 of 28 T AP Controller St ate Diag ram The state diagram for the T AP controller follows. [1 1] TEST -LOGIC RESET TEST -LOG IC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 ...

  • Cypress CY7C1426JV18 - page 15

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 15 of 28 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [12, 13, 14] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 ...

  • Cypress CY7C1426JV18 - page 16

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 16 of 28 T AP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Se ...

  • Cypress CY7C1426JV18 - page 17

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 17 of 28 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C141 1JV18 CY7C1426JV18 CY7C1413JV18 CY7C1415JV18 Revision Numb er (31:29) 000 000 000 000 V ersio n number . Cypress Device ID (28:12) 1 101001 1 01 10001 1 1 1 101 ...

  • Cypress CY7C1426JV18 - page 18

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 18 of 28 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 87 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61 4B 89 1K 6 8R 34 1 1E 62 ...

  • Cypress CY7C1426JV18 - page 19

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 19 of 28 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW). ...

  • Cypress CY7C1426JV18 - page 20

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 20 of 28 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature .................. ............... –65°C to +150°C Ambient T emperature w it h Pow e r App l i ...

  • Cypress CY7C1426JV18 - page 21

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 21 of 28 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs St a t ic 300 MHz (x8) 350 mA (x9) 350 (x18) 355 (x36) 395 250 MHz (x8) 355 mA (x9) 355 (x18) 355 (x36) 370 200 MHz ...

  • Cypress CY7C1426JV18 - page 22

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 22 of 28 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V , V DDQ = 1.5V 5 pF C CLK Clock ...

  • Cypress CY7C1426JV18 - page 23

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 23 of 28 Switching Characteristics Over the Operating Range [22] Cypress Parameter Consortium Parameter Descr iption 300 MHz 250 MHz 200 MHz Unit Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [23] 111 m s t CYC t KHKH K Clock and C ...

  • Cypress CY7C1426JV18 - page 24

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 24 of 28 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29 ] K 1 2 34 5 6 7 RPS WPS A Q D C C READ READ WRITE WRITE NOP NOP DON’ T CARE UNDEFINED CQ CQ K A0 A1 t KH t KHKH t KL t CY C t t HC t SA t HA A2 SC tt HC SC A3 t KHCH t K ...

  • Cypress CY7C1426JV18 - page 25

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 25 of 28 Ordering Information Not all of the speed, package, and temper ature ranges are available. Please cont act your local sale s representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Pack age Diagram Packag ...

  • Cypress CY7C1426JV18 - page 26

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 26 of 28 200 CY7C141 1 JV18-200BZC 51-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1426JV18-200BZC CY7C1413JV18-200BZC CY7C1415JV18-200BZC CY7C141 1JV18-200BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 m ...

  • Cypress CY7C1426JV18 - page 27

    CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 27 of 28 Package Diagram Figure 6. 165 - B a ll FBGA (15 x 17 x 1.40 mm ), 51- 85195 !  0).#/2.%2 ¼ ¼   ? ...

  • Cypress CY7C1426JV18 - page 28

    Document Number: 001-12557 Rev . *C Revised June 25, 2008 Page 28 of 28 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. A ll pr oduct an d company n ames mentio ned in this do cument are the tr ad emarks of their resp e ctive hold ers. CY7C141 1JV18, CY7C1426JV18 CY7C1413 ...

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Tutti sono importanti, ma le informazioni più importanti dal punto di vista di utilizzo del dispositivo possono essere trovate nel manuale per l’uso Cypress CY7C1426JV18.

Un gruppo di documenti denominato manuali per l’uso, è anche suddiviso in tipi più specifici, come: Manuali di installazione Cypress CY7C1426JV18, manuali di manutenzione, brevi manuali o manuali utente Cypress CY7C1426JV18. A seconda delle esigenze, si dovrebbe cercare il documento necessario. Nel nostro sito web, puoi visualizzare il manuale più popolare per l'uso del prodotto Cypress CY7C1426JV18.

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Il manuale per l’uso, denominato anche istruzioni per l’uso, o semplicemente il manuale è un documento tecnico progettato per aiutare ad utilizzare Cypress CY7C1426JV18 dagli utenti. I manuali sono di solito scritti da uno scrittore tecnico, ma in un linguaggio accessibile a tutti gli utenti Cypress CY7C1426JV18.

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