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Manuale per l’uso Cypress CYDC128B08

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Summary
  • Cypress CYDC128B08 - page 1

    1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port S t atic RAM CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 001-01638 Rev . *E Revised January 25, 2007 Features • T rue dual-ported memory cel ls which allow sim ...

  • Cypress CYDC128B08 - page 2

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 2 of 26 Notes: 1. A 0 –A 11 for 4k devices; A 0 –A 12 for 8k devices; A 0 –A 13 for 16k devices. 2. BUSY is an output in master mode and an input in slave mode. IO Control Address Decode Mailb oxes INT L INT R Addres s D ecode 16K X 16 Dual Ported A ...

  • Cypress CYDC128B08 - page 3

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 3 of 26 Pin Configurations [3, 4, 5, 6, 7] Notes: 3. A12L and A12R are NC pins for CYDC064B16. 4. IRR functionality is not supported for the CYDC256B 16 device. 5. Thi s pin is A 13L for CYDC256B 16 device. 6. This pin is A13R for CYDC256B16 device. 7. Le ...

  • Cypress CYDC128B08 - page 4

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 4 of 26 Notes: 8. IRR functionality is not supported for the CYDC128B 08 device. 9. Thi s pin is A 13L for CYD C128B08 devices. 10. This pin is A13R for CYDC128B08 devices. Pin Configurations (continued) [7, 8, 9, 10] 1 3 2 92 91 90 84 85 87 86 88 89 83 8 ...

  • Cypress CYDC128B08 - page 5

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 5 of 26 Functional Description The CYDC256B16, CYDC128B16 , CYDC064B16, CYDC128B08, CYDC064B08 are lo w-power CMOS 4k, 8k,16k x 16, and 8/16k x 8 dual-port static RAMs. Arbitration schemes are included on the devices to handle situations when multiple pro ...

  • Cypress CYDC128B08 - page 6

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 6 of 26 then the SEM pin must be asserted instead of th e CE pin, and OE must also be asser ted. Interrupts The upper two memory locati ons may be used for message passing. The highest memo ry location (FF F fo r th e CYDC064B16, 1FFF for the CYDC128B16 a ...

  • Cypress CYDC128B08 - page 7

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 7 of 26 When reading a semapho re, all sixteen/eight data lines output the semaphore value. The read value is latched in an output register to prevent the semapho re from changing state during a write from the o ther port. If bo th ports attempt to access ...

  • Cypress CYDC128B08 - page 8

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 8 of 26 T ab le 3. Inpu t Read Register Operation [16, 19] SFEN CE R/W OE UB LB ADDR I/O 0 – I/O 1 I/O 2 – I/O 15 Mode HLHL L L x 0 0 0 0 - M a x V A L I D [17] VA L I D [1 7] S tandard Memory Access L L H L X L x0000 V ALID [18] X IRR Read T able 4. ...

  • Cypress CYDC128B08 - page 9

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 9 of 26 Maximum Ratings [23] (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... .............. ...

  • Cypress CYDC128B08 - page 10

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 10 of 26 I IX Input Leakage Current 1.8V 1.8V –1 1 –1 1 µ A 2.5V 2.5V –1 1 –1 1 µ A 3.0V 3.0V –1 1 –1 1 µ A I CC Operating Current (V CC = Max., I OUT = 0 mA) Outputs Disabled Ind. 1.8V 1.8V 25 40 15 25 mA I SB1 S tandby Current (Both Ports ...

  • Cypress CYDC128B08 - page 11

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 1 1 of 26 Electrical Characteristics for V CC = 2.5V Over the Operating Range Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC06 4B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Unit -40 -55 P1 I/O Vo l t a g e P2 ...

  • Cypress CYDC128B08 - page 12

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 12 of 26 Electrical Characteristics for 3.0V Over the Operating Range Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC06 4B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Unit -40 -55 P1 I/O Vo l t a g e P2 I/O V ol ...

  • Cypress CYDC128B08 - page 13

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 13 of 26 7 AC T est Loads and W aveforms Switching Characteristics for V CC = 1.8V Over the Operating Range [27] Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Un ...

  • Cypress CYDC128B08 - page 14

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 14 of 26 t HA Address H old From W rite End 0 0 ns t SA [28] Address Set-up to W rite S tart 0 0 ns t PWE Write Pulse Width 25 40 ns t SD Data Set-up to W rite End 20 30 ns t HD Data Hold From W ri te End 0 0 ns t HZWE [30, 31] R/W LOW to High Z 15 25 ns ...

  • Cypress CYDC128B08 - page 15

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 15 of 26 Switching Characteristics for V CC = 2.5V Over the Operating Range Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Unit -40 -55 Min. Max. Min. Max. Read C ...

  • Cypress CYDC128B08 - page 16

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 16 of 26 Interrupt Timing [33] t INS INT Set T ime 35 45 ns t INR INT Reset T ime 35 45 ns Semaphore T iming t SOP SEM Flag Update Pulse (OE or SEM )1 0 1 5 n s t SWRD SEM Flag Write to Read Time 10 10 ns t SPS SEM Flag Contention Wind ow 10 10 ns t SAA S ...

  • Cypress CYDC128B08 - page 17

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 17 of 26 t HZWE [30, 31] R/W LOW to High Z 15 25 ns t LZWE [30, 31] R/W HIGH to Low Z 0 0 ns t WDD [32] W rite Pulse to Data Delay 55 80 ns t DDD [32] Write Dat a V alid to Read Data V al id 55 80 ns Busy Timing [33] t BLA BUSY LOW from Address Match 30 4 ...

  • Cypress CYDC128B08 - page 18

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 18 of 26 Switching W aveforms Read Cycle No.1 (Either Port Address Access ) [36, 37, 38] Read Cycle No.2 (Either Port CE /OE Access) [36, 39, 40] Read Cycle No. 3 (Eithe r Port) [36, 38, 41, 42] Notes: 36. R/W is HIGH for read cycles. 37. Device is contin ...

  • Cypress CYDC128B08 - page 19

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 19 of 26 Write Cycle No.1: R/W Controlled T iming [41, 42, 43, 44, 45, 46] Write Cycle No. 2: CE Controlled T iming [41, 42, 43, 48] Notes: 43. t HA is me asured fro m the ea rlier of CE or R/W or (SEM or R/W ) going HIGH at the end of write cycle. 44. If ...

  • Cypress CYDC128B08 - page 20

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 20 of 26 Semaphore Read After W rite Timing, Either Side [49, 50] Timing Diagram of Semap hore Contention [51, 52] Notes: 49. If the CE or SEM LOW transition occu rs simultaneously with or af ter the R/W LO W transition, the output s remain in the high-im ...

  • Cypress CYDC128B08 - page 21

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 21 of 26 Timing Diagram of Read with BUSY (M/S =HIGH) [53] Write T iming with Busy Input (M/S = LOW) Note: 53. CE L = CE R = LOW . Switching W aveforms (continued) VA L I D t DDD t WDD MA TCH MA TCH R/W R DA T A IN R DA T A OUTL t WC ADDRESS R t PWE VA L ...

  • Cypress CYDC128B08 - page 22

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 22 of 26 Busy Timing Diagram No.1 (CE Arbitration) Busy Timing Diagram No.2 (Address Arbitration) [54] Note: 54. If t PS is violated, the busy signal will be asserted on one side or t he other , but there is no guarantee to which side BUSY will be asserte ...

  • Cypress CYDC128B08 - page 23

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 23 of 26 Interrupt Timing Diagrams Notes: 55. t HA depends on which enable pin (CE L or R/W L ) is deasserted first . 56. t INS or t INR depends on which enable pin (CE L or R/W L ) is asserted last. Switching W aveforms (continued) WRITE 1FFF (OR 1/3FFF) ...

  • Cypress CYDC128B08 - page 24

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 24 of 26 Ordering Information 16k x16 1.8 V Asynchronous Dual-Por t SRAM Spee d (ns) Orderin g Code Package Name Package T ype Operating Range 40 CYDC256B16-40AXC AZ0AB 1 00-pin Lead-free TQFP Commercial 55 CYDC256B16-55AXC AZ0AB 1 00-pin Lead-free TQFP C ...

  • Cypress CYDC128B08 - page 25

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 25 of 26 © Cypress Semi conductor Corpora tion, 2006. The information con tained he rein is subject to change wit hout notice. Cypr ess Semic onductor Corpo ration assumes no responsibility for th e use of any circuitry o ther than circui try embodied in ...

  • Cypress CYDC128B08 - page 26

    CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 26 of 26 Document History Page Document Title: CYDC256B16/CYDC128B16/CYDC06 4B16/CYDC 128B08/CYDC064B08 1.8V 4 k/ 8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port St atic RAM Document Number: 00 1-01638 REV . ECN NO. Issue Date Orig. of Change Description o ...

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