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Cypress CY7C68000A - page 1
CY7C68000A MoBL-USB™ TX2 USB 2.0 UTMI T ransceiver Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-08052 Rev . *G Revised October 5, 2 008 MoBL-USB ™ TX2 Features ■ UTMI-compliant and USB 2.0 certified for device operation ■ Operates in both USB 2.0 High S p eed (HS), 48 ...
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Cypress CY7C68000A - page 2
CY7C68000A Document #: 38-08052 Rev . *G Page 2 of 15 Applications Mobile Applications ■ Smart Phones ■ PDA Phones ■ Gaming Phones ■ MP3 play ers ■ Portable Media Players (PMP) ■ GPS T racking Devices Consumer Applications ■ Cameras ■ Scanners ■ DSL Modems ■ Memory Card Readers Non-Consumer Applicatio ns ■ Networking ■ Wirel ...
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Cypress CY7C68000A - page 3
CY7C68000A Document #: 38-08052 Rev . *G Page 3 of 15 Operational Modes The operational modes are cont rolled by the OpMode signa ls. The OpMode signals are capable of inhibiti ng normal operation of the transceiver an d evoking special test modes. These modes take effect immediately and take precedence over any pending data operations. The transmi ...
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Cypress CY7C68000A - page 4
CY7C68000A Document #: 38-08052 Rev . *G Page 4 of 15 Pin Configurations The following pages ill ustrate the individual pin diagrams t hat are available in the 56-pi n QFN and 56-pin VFBGA packages. The packages offered use either an 8-bit (6 0 MHz) or 16-bit (30 MHz) bus interface. Figure 1. CY7C68000A 56-pin QF N Pin Assignment D4 D3 V CC D2 Rese ...
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Cypress CY7C68000A - page 5
CY7C68000A Document #: 38-08052 Rev . *G Page 5 of 15 Figure 2. CY7C68000A 56- pin VF BGA Pin Assignment 12345678 A B C D E F G H 1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C 4C 5C 6C 7C 8C 1D 2D 7D 8D 1E 2E 7E 8E 1F 2F 3F 4F 5F 6F 7F 8F 1G 2G 3G 4G 5G 6G 7G 8G 1H 2H 3H 4H 5H 6H 7H 8H [+] Feedback ...
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Cypress CY7C68000A - page 6
CY7C68000A Document #: 38-08052 Rev . *G Page 6 of 15 Pin Descriptions T able 1. Pin Descriptions QFN VFBGA Name Ty p e Default Description [1] 4H 1 A V C C P o w e r N / A Analog V CC This signal provides power to the analog sectio n of the chip. 8H 5 A V C C P o w e r N / A Analog V CC This signal provides power to the anal og section of the chip ...
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Cypress CY7C68000A - page 7
CY7C68000A Document #: 38-08052 Rev . *G Page 7 of 15 24 B8 T ri_state Input T ri-st ate Mode Enable Places the CY7C68000A into T ri-state mode which tri-states all outputs and IOs. Tri-st ate Mode can only be enabled while suspended. 0: Disabl es T ri-st ate Mode 1: Enables T ri-state Mode 19 C2 Lin eS t ate1 Output Line St ate These signals refle ...
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Cypress CY7C68000A - page 8
CY7C68000A Document #: 38-08052 Rev . *G Page 8 of 15 21 A4 RXV alid Output Receive Data V alid This signal indicate s that the DataOut bus has valid data. The Receive Data Holding Re gister is full and rea dy to be unloade d. The SIE is expected to latch the DataOut bus on the clock edge. 22 B7 RXActive Output Receive Active This signal in dicates ...
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Cypress CY7C68000A - page 9
CY7C68000A Document #: 38-08052 Rev . *G Page 9 of 15 Absolute Maximum Ratings S torage T emperature ................ .............. ... –65°C to +150°C Ambient T emperature with Power Supplie d ..... 0°C to +70°C Supply V oltage to Ground Potentia l ............... –0.5V to +4.0V DC Input V oltage to Any Input Pin ............ ............ ...
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Cypress CY7C68000A - page 10
CY7C68000A Document #: 38-08052 Rev . *G Page 10 of 15 AC Electrical C haracteristics USB 2.0 T ransceiver USB 2.0-compliant in FS and HS modes. Tim in g Di a gr am HS/FS Interface Ti ming - 60 MHz Figure 3. 60 MHz Interface Timing Constr aints T able 3. 60 MHz Interface Timing Constraints Parameters Parameter Description Min Ty p Max Unit Notes T ...
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Cypress CY7C68000A - page 11
CY7C68000A Document #: 38-08052 Rev . *G Page 1 1 of 15 HS/FS Interface Ti ming - 30 MHz Figure 4. 30 MHz Timing Interface Timing Constr aints Figure 5. T ri-state Mo de T iming Constraint s T able 5. Tr i-state Mode Timing Constraints Parameters T able 4. 30 MHz Timing Interf ace Timing Constraint s Parame ters Parameter Description Min Ty p Max U ...
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Cypress CY7C68000A - page 12
CY7C68000A Document #: 38-08052 Rev . *G Page 12 of 15 Ordering Information Ordering Code Package T ype CY7C68000A-56LFXC 56 QFN CY7C68000A-56BAXC 56 VFBGA CY3683 MoBL-USB TX2 Development Board Package Diagrams The MoBL-USB TX2 is available in two packages: ■ 56-pin QFN ■ 56-pin VFBGA Figure 6. 56-Pin Quad Flatpack No Lead Package 8 x 8 mm (Saw ...
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Cypress CY7C68000A - page 13
CY7C68000A Document #: 38-08052 Rev . *G Page 13 of 15 PCB Layout Recommendations Follow these recommendations to ensure reliable, high-perfor - mance operation [3] . ■ A four-layer impedance controlled board is required to ma intain signal quality ■ S pecify impedan ce targets (ask your board vendor what they can achieve) ■ T o control imped ...
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Cypress CY7C68000A - page 14
CY7C68000A Document #: 38-08052 Rev . *G Page 14 of 15 Quad Flat Package No Leads (QFN) Package Design Notes Electrical cont act of the part to the Print ed Circuit Board (PCB) is made by sold ering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide ...
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Cypress CY7C68000A - page 15
Document #: 38-08052 Rev . *G Revi sed October 5, 2008 Page 15 of 15 MoBL-USB TX2 is a trademark of Cypress Semiconductor Corporation. Intel is a regist ered trademark of I ntel Corporation. All p ro duct and comp any names mentioned in this document are the tradema rks of their respective holder s. All product s and comp any names me ntioned in th ...
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