Intel IXF1104の取扱説明書

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Summary
  • Intel IXF1104 - page 1

    Intel ® IXF1 104 4-Port Giga bit Ethe rnet Med ia A ccess Co ntro ller Da ta sh eet The In te l ® IXF1 104 is a four -p ort Giga bit MAC that supp orts IEEE 802.3 10/ 100/ 1000 Mbps app lic at io ns. The IXF1 104 supp orts a S yst e m Pac ket In te rfac e P hase 3 (SP I 3) s yst e m int erfac e to a network processor or ASIC, and concur rent ly s ...

  • Intel IXF1104 - page 2

    2 D atasheet Document Number: 2 78757 Re vision Num ber: 007 Revis ion Date: Ma rch 25 , 2004 Applic ati ons Load Ba la n ci n g Sy s t em s Mul tiS e rv ice S w it ch W eb Cachi ng Appli ances I nte lligent Ba c kpl ane Interfaces Edge Route r Bas e S tatio n Contro ller Redun da n t Li ne Cards Base T rans c eiver S tatio n Serving GRPS Sup port ...

  • Intel IXF1104 - page 3

    Contents Datasheet 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Content s 1. 0 I ntr odu cti on ... .... ..... ..... ..... .... ..... ..... .... ..... ..... ..... .... ........ .... ..... ..... .... ..... ..... ..... .... ..... ..... ..... .... .... ... 19 1.1 What You W ill Fi nd i n T his D ocum en t .... ...

  • Intel IXF1104 - page 4

    Contents 4 D at a sheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 5.1.5 .1 Speed... .. ..... .... ..... ..... ..... .... ..... ..... ..... .... ..... ..... ..... .... ..... ..... .... ..... ..... ...... 77 5.1.5 .2 Dupl e x .... ....... ..... ..... .... ..... ..... ..... .... ..... ..... .... ..... ....... ... ...

  • Intel IXF1104 - page 5

    Contents Datasheet 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.6.2.3 Recei ver Op erational Overview . ..................................................... ..... 1 04 5.6. 2.4 Sel ecti ve P ower-Down .... ..... ..... ..... .... ..... ..... .. ..... ..... .... ..... ....... ..... ....... 104 5.6. 2.5 Rec ...

  • Intel IXF1104 - page 6

    Contents 6 D at a sheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 6.0 Applications ..... .... ..... ..... ....... ..... .... ..... ..... ..... .... ..... ..... ..... .... ..... ....... ..... ..... .... ..... ..... .... ..... ..... .... 129 6.1 Change Port Mode Initialization Sequenc e........................ . ...

  • Intel IXF1104 - page 7

    Contents Datasheet 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 9.2 Pack a ge Sp ecif ics f or the IXF1104 ..... ..... .... ..... ... .... ..... ..... .... ........ .... ..... ..... .... ..... ..... ....... 2 23 9.3 Pack a ge In fo rm a t i on ... ..... .. ..... .. ..... ... .... ....... ..... ..... .. .... ...

  • Intel IXF1104 - page 8

    Contents 8 D at a sheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 43 MDIO Write Timi n g Diagra m . ... .... ... .... ..... ... .... ... .... ... ..... .. ..... .... ... .... ... ..... .. ..... ....... .... ........ .... .. 145 44 MDIO Read Timing Diag r a m .... .. ..... .... ... ..... .. ..... .. ..... .. .. ...

  • Intel IXF1104 - page 9

    Contents Datasheet 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 33 M ode 1 Clock Cycle to Data Bit Relationship .................. .............. ................... ................. ....... 1 17 34 LED_DATA # Deco des . ..... ..... .. ..... .... ..... ..... ....... ..... ....... ..... ....... .... ..... . ...

  • Intel IXF1104 - page 10

    Contents 10 D at a sheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 83 F lush TX ($ Port_Index + 0x11). ........................... ........................................ ........................... . 166 84 FC Enable ($ P o rt_Index + 0x 12) .............................................. .................... ...

  • Intel IXF1104 - page 11

    Contents Datasheet 11 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 133 TX FIFO Low Water mar k Regi ster Port s 0 - 3 ($0 x6 0 A – 0x6 0 D) .... ..... .. ..... ....... .... ... ..... ....... .. 203 134 TX FIFO MAC Threshold Register Ports 0 - 3 ( $ 0x 614 – 0x617) ..................... ................... ...

  • Intel IXF1104 - page 12

    Contents 12 D at a sheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 Revision History Re vi sio n Nu mb er: 00 7 Re vi sio n Da te : M arc h 25, 20 04 (Sh e et 1 of 5 ) Pag e # Des crip ti on All Glob ally repl aced GBI C w ith O pti cal M o dule Inter fac e. Al l Gl oba lly ed ite d sign al nam es. All Gl oba l ...

  • Intel IXF1104 - page 13

    Contents Datasheet 13 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 38 Modi fied Secti on 4.3, “Sign a l Des cript ion T abl es” [ch ange d head ing f rom “ Si gnal Na ming Co nv en t io ns ; ad de d ne w head in gs S ec tio n 4.1 .1 , “S ig na l Na me C onv e ntion s ” and Se ction 4. 1.2, “Reg is ...

  • Intel IXF1104 - page 14

    Contents 14 D at a sheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 97 Mo difi ed Fi gu re 2 0 “RX _C TL Be havi or” [c hang ed s igna l n ame s] . 98 Mo difi ed Se cti on 5 .5, “ MD IO C o ntr ol an d In terf ac e” [cha ng ed 3 .3 us to 3 .3 ms in fou rth pa rag rap h, thi rd se nt en ce ] . 102 Mod if ...

  • Intel IXF1104 - page 15

    Contents Datasheet 15 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 155 Br ok e up th e old Re gister Map int o T able 59 “MAC Contro l Registers ($ Po rt Index + Offset)” , T abl e 60 “ MAC RX S t atis tics Regi ste rs ( $ P or t I ndex + Off set) ” , T a bl e 61 “M AC TX S tat istic s Reg i sters ( ...

  • Intel IXF1104 - page 16

    Contents 16 D at a sheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 206 Mo di fie d T able 136 “Loo p R X Da t a to TX FIF O (L ine- Side L oopb ack ) Por ts 0 - 3 ($0 x61F )” [r enam ed hea ding and bit nam e]. 207 Mo di fie d T able 138 “T X FIF O O verfl ow Fra me Dr op C ou nt er Por ts 0 - 3 ($ 0x 62 ...

  • Intel IXF1104 - page 17

    Contents Datasheet 17 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 140 M odif i ed T ab le 53 “ IPG Re cei ve an d Tr ansmi t T ime R egist er (A ddr: Por t_I ndex + 0x 0A – + 0x0C )” . 143 M odifi ed T able 60 “ Sho rt Runt s Thre shol d R egis ter (A d dr: Po rt_I nd ex + 0x1 4)”. 143 M odifi ed T ...

  • Intel IXF1104 - page 18

    Contents 18 D at a sheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 ...

  • Intel IXF1104 - page 19

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 19 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 1.0 I ntr oduc tion This docu m ent co ntains info rmati on on the In tel ® IXF1 104 4-Port 10/ 100/1000 Mbps Et her net Media Acces s Control ler (MAC). 1.1 Wha t Y ou Wi l l Fi nd in Thi s ...

  • Intel IXF1104 - page 20

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 20 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 2.0 General Desc r ipti on The IXF 11 04 provide s up to a 4.0 Gbp s inte rfa c e to f our indiv idual 10/100 /1000 Mbps full -duplex or 10/100 Mbps half-du plex-capable Etherne t Med ia Ac cess Co ...

  • Intel IXF1104 - page 21

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 21 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Figure 2 illustra tes the IXF1 104 intern a l archi te c t ure. Figure 2. Internal Arch itec ture SP I3 I nte rfa ce CPU I nterfa c e RMON St at isti cs Pack et TX Buf fer RX Pack et Buf fer ...

  • Intel IXF1104 - page 22

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 22 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 3.0 Ball Assignment s and Ball List T ables 3.1 Ball A ssig nmen t s See Figur e 3 , T able 1 “Ball List in Alphan umeric Order by Sign a l Name” on page 23 , a nd Ta b l e 2 “Ba ll List in Al ...

  • Intel IXF1104 - page 23

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 23 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 3.2 Ball List T ab le s 3.2.1 Ba lls Listed in Alphabe t ic Order by Sign al Name Ta b l e 1 shows the ball locati ons and s igna l names arranged in alphanum er ic order by signal na m e. The fol ...

  • Intel IXF1104 - page 24

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 24 Document N umber: 27 8757 Revision Nu mber: 00 7 Revision Da te: Ma rch 25 , 2004 GN D R 2 GN D R 6 GN D R 9 GN D R 11 GN D R 1 4 GN D R 1 6 GN D R 1 9 GN D R 2 3 GN D T1 0 GN D T1 5 GN D U 4 GN D U 8 GN D U 1 2 GN D U 1 3 GN D U 1 7 GN D U 2 1 GN D W2 GN D W6 GN D W1 0 GN D ...

  • Intel IXF1104 - page 25

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 25 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 No Ba ll AC1 No Ba ll AC2 No Ball AC23 No Ball AC24 No Ba ll AD1 No Ba ll AD2 No Ba ll AD3 No Ball AD22 No Ball AD23 No Ball AD24 No Pad A1 PT PA 2 B1 1 RDA T_0 2 A15 RDA T_1 2 A14 RDA T_2 2 B14 R ...

  • Intel IXF1104 - page 26

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 26 Document N umber: 27 8757 Revision Nu mber: 00 7 Revision Da te: Ma rch 25 , 2004 RXD5_1 1 AC1 1 RXD5_2 1 V20 RXD5_3 1 T1 7 RXD6_0 1 AB 5 RXD6_1 1 AA 1 1 RXD6_2 1 V19 RXD6_3 1 T1 8 RXD7_0 1 AC5 RXD7_1 1 Y1 0 RXD7_2 1 W20 RXD7_3 1 T1 9 ST P A 2 C1 1 SY S_RST_ L AD12 T ADR0 2 A ...

  • Intel IXF1104 - page 27

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 27 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 TXD4_1 1 AA 7 TXD4_2 1 AD1 6 TXD4_3 1 AA 14 TXD5_0 1 AC3 TXD5_1 1 AB 8 TXD5_2 1 AB 19 TXD5_3 1 Y1 5 TXD6_0 1 AB4 TXD6_1 1 AD8 TXD6_2 1 AA 20 TXD6_3 1 AA 16 TXD7_0 1 Y4 TXD7_1 1 AC9 TXD7_2 1 AA 18 ...

  • Intel IXF1104 - page 28

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 28 Document N umber: 27 8757 Revision Nu mber: 00 7 Revision Da te: Ma rch 25 , 2004 VDD2 F8 VDD2 F12 VDD2 H2 VDD2 H6 VDD2 J12 VDD2 M2 VDD2 M6 VDD2 M9 VDD2 M12 VDD3 B13 VDD3 B17 VDD3 B21 VDD3 D23 VDD3 F13 VDD3 F17 VDD3 H19 VDD3 H23 VDD3 J13 VDD3 M13 VDD3 M16 VDD3 M19 VDD3 M23 VD ...

  • Intel IXF1104 - page 29

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 29 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 3.2.2 Ba lls Listed in Alph abetic Orde r by Ball Locatio n Ta b l e 2 shows the ball locati ons and s ignal na mes arran ged in order by ba ll lo cation. T ab le 2. Ball List in Al phan ume ric O ...

  • Intel IXF1104 - page 30

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 30 Document N umber: 27 8757 Revision Nu mber: 00 7 Revision Da te: Ma rch 25 , 2004 E6 TDA T1 7 2 E7 TDA T1 8 2 E8 TDA T1 9 2 E9 TDA T2 0 2 E10 TDAT21 2 E1 1 TERR_2 2 E12 NC E13 RS X 2 E14 RDA T_6 2 E15 RPR TY_0 2 E16 RDA T_1 1 2 E17 RDA T_13 2 E18 RDA T_14 2 E19 RV A L_2 2 E20 ...

  • Intel IXF1104 - page 31

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 31 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 J2 4 TDI K1 TERR_1 2 K2 GND K3 UPX_D ATA1 K4 VDD K5 UPX_D ATA7 K6 GND K7 NC K8 VDD K9 GND K10 UPX_ DATA17 K1 1 GND K12 UPX_ DATA21 K13 UPX_ DATA23 K14 GN D K15 UPX_ DATA25 K16 GN D K17 VDD K18 NC ...

  • Intel IXF1104 - page 32

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 32 Document N umber: 27 8757 Revision Nu mber: 00 7 Revision Da te: Ma rch 25 , 2004 P18 NC P19 RX_ LOS_IN T 3 P20 T X PAUSE_ADD1 P21 T X PAUSE_ADD2 P22 RX_P _0 3 P23 T X_F AUL T _IN T 3 P24 I 2 C_DA T A_3 3 R1 UPX_ADD3 R2 GND R3 UPX_CS_L R4 VDD R5 NC R6 GND R7 GND R8 VDD R9 GND ...

  • Intel IXF1104 - page 33

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 33 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 W12 VDD5 W13 VDD4 W1 4 TX D7_ 3 1 W1 5 GN D W16 TX_P_2 3 W17 VDD4 W1 8 RX D3_ 3 1 W1 9 GN D W2 0 RX D7_ 2 1 W2 1 VD D W2 2 RX D4_ 2 1 W2 3 GN D W2 4 MDC 4 Y1 TXD0_0 1 Y2 TXD1_0 1 Y3 TXD2_0 1 Y4 TX ...

  • Intel IXF1104 - page 34

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 34 Document N umber: 27 8757 Revision Nu mber: 00 7 Revision Da te: Ma rch 25 , 2004 AD6 TX_E R_1 1 AD7 TXC_1 1 AD8 TXD 6_1 1 AD9 TXD 3_1 1 AD10 RXD4_1 1 AD1 1 RXC_1 1 AD12 SY S_RS T_L AD 13 TX_P_ 1 3 AD 14 TX _N_ 1 3 AD15 CO L_2 1 AD16 TXD 4_2 1 AD 17 TX_ER _2 1 AD 18 TX _N_ 3 ...

  • Intel IXF1104 - page 35

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 35 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 ...

  • Intel IXF1104 - page 36

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 36 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 4.0 Ball Assignm ent s and Signal Descri ptions 4.1 Namin g Con ve nt io ns 4.1.1 Signal Name Conventions Si gna l na mes beg in with a Si gna l Mne moni c , and can also c ontain one or more of th ...

  • Intel IXF1104 - page 37

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 37 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 4.2 Int erfa ce Si gnal Gr oup s This s ection descri bes the IXF 110 4 signal s in g roups a ccording to t he ass ocia ted i nterface or functi on. Figure 4 shows the vario us inte rfaces a ...

  • Intel IXF1104 - page 38

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 38 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 4. 3 S i g nal D e script ion T abl es The I/O s ignal s, power s upplie s, or ground r eturns a ssoci a ted wit h each IXF110 4 conne ctio n ball are d esc r ib e d in Ta b l e 3 thro ugh Ta b l e ...

  • Intel IXF1104 - page 39

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 39 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 TPRTY_0 T PRTY_0 TPR TY_ 1 TPR TY_ 2 TPR TY_ 3 D5 G3 B9 J6 Inpu t 3.3 V LV T T L T ran smit P ari ty . TPRTY in dica te s odd parit y for the TD A T bus. TPR T Y i s va lid on ly w hen a ch a ...

  • Intel IXF1104 - page 40

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 40 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 TM OD 1 TM OD 0 NA D9 A6 In pu t 3.3 V L V TTL TM OD[1:0] Transmit Word M odulo . 32 -bit Mu lti- P HY mod e: T MO D[1 :0] indi cate s th e vali d data by tes of TDA T[31: 0]. D uring tra nsm issi ...

  • Intel IXF1104 - page 41

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 41 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 DTP A_0 DTP A_1 DTP A_2 DTP A_3 DTP A_0 DTP A_1 DTP A_2 DTP A_3 D3 L1 A9 J7 Output 3. 3 V LV T T L DT P A_0 :3 Di r ect T ran smi t Packe t Available . A di rect st atus ind ic ati on fo r tr ...

  • Intel IXF1104 - page 42

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 42 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 P T PA PT PA B 11 O u t p u t 3.3 V L V TTL P olled- PHY Tran smit P acke t Avail able. PT P A all ows th e polli ng of t he port select ed by the T A DR addr ess bus . W hen Hi gh, P TP A indi ca ...

  • Intel IXF1104 - page 43

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 43 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 RDA T 7 RDA T 6 RDA T 5 RDA T 4 RDA T 3 RDA T 2 RDA T 1 RDA T 0 RDA T7_0 RDA T6_0 RDA T5_0 RDA T4_0 RDA T3_0 RDA T2_0 RDA T1_0 RDA T0_0 F1 4 E1 4 D1 4 C1 3 C1 4 B1 4 A1 4 A1 5 Output 3. 3 V L ...

  • Intel IXF1104 - page 44

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 44 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 RERR_0 RERR_0 RERR_1 RERR_2 RERR_3 A16 G17 D20 H20 Ou tp ut 3.3 V L V TTL Receive Error . R ERR ind ica tes tha t the cu rrent pa cket is in error . RERR is only asse rte d wh en REOP is ass er ted ...

  • Intel IXF1104 - page 45

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 45 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 REOP_0 REOP_0 REOP_1 REOP_2 REOP_3 C1 6 D1 8 C2 3 J19 Output 3. 3 V LV T T L Re ceive E n d of Pac ket. RE O P in dicate s the end of a pa cket w hen asserted with RV AL. 3 2 - bit M ul ti- P ...

  • Intel IXF1104 - page 46

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 46 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 T ab le 4. SerDes Interface S ignal Descri ptions Signa l N ame B all D es ign ato r T yp e St an da r d Descri ptio n T X_P _0 T X_P _1 T X_P _2 T X_P _3 Y13 AD13 W16 AC18 Ou tput Ser Des Trans mi ...

  • Intel IXF1104 - page 47

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 47 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 5 . GMI I Interface Signal D escription s (Sheet 1 of 2) Signal Nam e Ba ll Des ign ator Ty p e Sta ndar d Desc ripti on TXD7_0 TXD6_0 TXD5_0 TXD4_0 TXD3_0 TXD2_0 TXD1_0 TXD0_0 TXD7_1 ...

  • Intel IXF1104 - page 48

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 48 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 RXD7_0 RXD6_0 RXD5_0 RXD4_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 RXD7_1 RXD6_1 RXD5_1 RXD4_1 RXD3_1 RXD2_1 RXD1_1 RXD0_1 RXD7_2 RXD6_2 RXD5_2 RXD4_2 RXD3_2 RXD2_2 RXD1_2 RXD0_2 RXD7_3 RXD6_3 RXD5_3 RXD4_3 R ...

  • Intel IXF1104 - page 49

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 49 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 6. RGMII Interface Signal Description s (Sheet 1 of 2) Signal Nam e Ball Desi gn ator T ype Standar d Descrip tion TXC_0 TXC_1 TXC_2 TXC_3 AA1 AD7 AC20 AB14 Ou tput 2.5 V CMOS Sourc e ...

  • Intel IXF1104 - page 50

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 50 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 RD3_0 RD2_0 RD1_0 RD0_0 RD3_1 RD2_1 RD1_1 RD0_1 RD3_2 RD2_2 RD1_2 RD0_2 RD3_3 RD2_3 RD1_3 RD0_3 Y7 W7 V7 V8 W9 W1 1 Y1 1 Y9 Y2 3 Y2 2 Y2 1 Y2 0 W18 Y1 9 Y1 8 Y1 7 In pu t 2.5 V CMOS Re ce ive D ata ...

  • Intel IXF1104 - page 51

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 51 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 UPX_DA T A 31 UPX_DA T A 30 UPX_DA T A 29 UPX_DA T A 28 UPX_DA T A 27 UPX_DA T A 26 UPX_DA T A 25 UPX_DA T A 24 UPX_DA T A 23 UPX_DA T A 22 UPX_DA T A 21 UPX_DA T A 20 UPX_DA T A 19 UPX_DA T ...

  • Intel IXF1104 - page 52

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 52 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 T ab le 8. T ran smit Pause Co ntrol Interface S ignal Descripti ons Signa l N ame Ball Designator T yp e Stan dard D esc rip ti on TXP AUSEADD2 TXP AUSEADD1 TXP AUSEADD0 P21 P20 N20 In put 2. 5 V ...

  • Intel IXF1104 - page 53

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 53 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 TX_F AU L T_INT P 23 Open Drai n Output* 2.5 V CMOS T rans mitter Fau lt Interrupt. TX _F AUL T_I NT i s an op en dr a in i nterr u pt o utpu t th at si gn al s a TX _FAUL T con di tio n. NOT ...

  • Intel IXF1104 - page 54

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 54 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 T ab le 1 1. LE D Interface Signal Descriptions Signa l N ame Ba ll Designator T ype St andard Descripti on LED_CLK K 24 Ou tput 2. 5 V CMOS LED_ CLK is the cl ock ou tp ut for the L E D b lock. LE ...

  • Intel IXF1104 - page 55

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 55 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 1 4. P ower Su pply Signal D escription s Signal Name Ball Designator T y pe S tandard Descripti on GND A4 B15 D12 F2 F19 H12 J10 K9 K19 L12 M4 M17 N1 1 P10 R2 R1 1 R23 U8 U21 W15 AA8 ...

  • Intel IXF1104 - page 56

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 56 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 4.4 Ball U sage Summ ary T ab le 15. Ball Usage Summa ry T ype Q uantity Inpu ts 158 Outputs 12 6 Bi -d ir ecti on al 37 T otal S ign al s 321 Power 75 Grou nd 82 No Co nn ects 74 To t a l 5 5 2 ...

  • Intel IXF1104 - page 57

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 57 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 4. 5 M ultip lex ed B all C onn ec tion s 4.5.1 GMII/RGMII/ S erDes/O MI Multiplexed Ba ll Connectio n s T able 16 lists th e balls us e d for t he li ne - si de i nte rfaces (GMII , RGMII, S ...

  • Intel IXF1104 - page 58

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 58 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 4. 5.2 SP I3 MPHY /SPHY B all Conn ections Ta b l e 1 7 li sts t he ba lls used fo r the SPI3 Interface a nd provide s a guide to c onnect t he se ba lls in MPHY and SPHY mode. NC N C TX_FAUL T _IN ...

  • Intel IXF1104 - page 59

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 59 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 TERR_0 T ERR_0 A8 MPH Y : U s e TE RR _ 0 as the T ER R sign al. SPHY : Eac h po r t has i ts o wn de dica te d TERR_ n sign al GND TERR_ 1 K1 GND TERR_ 2 E1 1 GND TERR_ 3 J8 TSOP_0 TSOP_0 C7 ...

  • Intel IXF1104 - page 60

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 60 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 4. 6 B al l St ate D ur ing Re se t RERR_0 RERR_0 A16 MP HY : Use RE RR_0 as the RERR si gnal . SPHY : Each po rt has a d edic at ed RERR_ n sign al NC RERR_ 1 G17 NC RERR_ 2 D20 NC RERR_ 3 H20 RV ...

  • Intel IXF1104 - page 61

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 61 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 JT AG TDO 0x0 – MDIO MD IO Hi gh Z Bi -di rec ti onal MDC 0x0 – CPU U PX _DAT A[3 1:0] Hi gh Z Bi -di rec ti onal UPX _R DY _L 0X1 O p en- drain o utp ut, re quir es an e xt ern al pull - ...

  • Intel IXF1104 - page 62

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 62 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 4.7 Powe r S upp ly Se qu enci ng Fol low th e power - up and powe r -down s equenc es des c ribed in this secti on to ens ure co rrec t I XF1 104 opera tio n. The sequenc e desc ribed in Secti on ...

  • Intel IXF1104 - page 63

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 63 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 4.8 Pull-Up/P ull- Down B all Gu idelin es The signa ls shown in T able 20 requi re the addit ion of a pull-up or pull-d own resis t or to the board des ign for norm a l ope r a tion. Any bal ...

  • Intel IXF1104 - page 64

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 64 Datasheet Document Nu mber: 27 8757 Revis ion Numb er: 007 Revision Dat e: Marc h 25, 2004 Figu re 6. A nal og Po we r S up pl y Fil te r Ne two rk T ab le 21. Analog Power Bal ls Signa l N ame Ball Desi gn ator C omme nts A VDD1 P8_1 A5 A20 Need t o provi de a fil ter ( see Figu re 6 ). ...

  • Intel IXF1104 - page 65

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 65 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.0 Functio nal Descriptions 5.1 Media Ac cess Cont rolle r (M AC) The IXF1 104 m ain func tiona l block con s is ts of fo ur inde pe n den t 10/100/10 00 Mbps Etherne t MACs, w ...

  • Intel IXF1104 - page 66

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 66 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 CRC is removed opti onally from recei ve pa c kets aft e r va li da t ion, a nd is not forwarde d to S P I 3. Pa cke ts wit h a b ad CRC are marke d, count ed in th e statist ic s b ...

  • Intel IXF1104 - page 67

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 67 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5. 1. 1. 3. 2 Fil ter on M u l t icas t Pack et Ma tc h Thi s feat u re is en ab l ed w he n bit 1 o f the “RX Packe t Filt er Control ($ Port_Inde x + 0x19)" = 1. Any fr ...

  • Intel IXF1104 - page 68

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 68 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 Whe n the CRC Error Pa ss Filt er bit = 0 ( “RX Packe t Filter Cont rol ($ Port_Index + 0x19) ” ), i t tak e s prec ede nce over the other fi lte r bits. Any packet ( Paus e, Un ...

  • Intel IXF1104 - page 69

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 69 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 The IXF1 104 MAC imple ments the IEEE 802.3x sta ndard RX FIFO thr eshol d-ba sed Flow Cont rol in coppe r and fiber modes. When appropria tely programm ed, the MAC can both gen ...

  • Intel IXF1104 - page 70

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 70 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.1.2. 1 .1 Pau se F r am e Form at P AUSE frames are MAC con trol frames tha t are padde d to the m inim um size (64 byt e s). Figure 8 and Figure 9 illu s t r at e th e fram e for ...

  • Intel IXF1104 - page 71

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 71 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 An IEEE 802.3 MAC P AUSE frame is ide ntifie d by det ec tin g all of the followi ng: • OpCode of 00-01 • Lengt h/T ype f iel d of 88-08 • DA matching the uni que mult ica ...

  • Intel IXF1104 - page 72

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 72 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.1.2. 1. 3 R es pon se to Rece i ved P AUS E C o mm a nd Fram es When Flow Contr ol is enable d in the re cei ve di rec t i on ( bit 0 in the “FC E nabl e ($ Port_ Index + 0x12)& ...

  • Intel IXF1104 - page 73

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 73 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 23. V a lid Decodes for TXP AUSEADD[2:0] TXP AUSEADD_ 2:0 Ope ration of TX Pause Con trol In terface 0x0 Tran smi ts a P AU SE fra m e on ev ery por t w ith a pa use _ti ...

  • Intel IXF1104 - page 74

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 74 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5. 1.3 Mixed -Mode Operat ion The I ntel ® IXF 110 4 giv es the user t he optio n of config uring each po rt for 10 /100 Mbps half-dupl ex coppe r , 10/100/1000 Mbps f ull-dupl ex ...

  • Intel IXF1104 - page 75

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 75 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.1. 4 Fiber Mode When the IXF1 104 is configure d for fiber mode, the TX Data path from the MAC is an inte rnal 10- bit inte rface as des cribed in the IEEE 802. 3z speci ficat ...

  • Intel IXF1104 - page 76

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 76 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 When co nfigured for fiber mode , the full set of Opti ca l Mod ule int erf a ce c ontr ol a nd status sig nals is pr esen te d through re-use of GMII signa ls on a pe r -p ort ba s ...

  • Intel IXF1104 - page 77

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 77 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 use r . The RGMII interface suppor ts operati on a t 10/ 100/1000 Mbps when a f ull-duplex li nk is establ ished, and supports 10 /100 Mbp s whe n a ha lf-dup lex l ink is estab ...

  • Intel IXF1104 - page 78

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 78 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 The regis t e r shoul d be progr a mmed to 0x266 7 for the 9.6 KB l ength jumbo fra me, opt imized for the IXF1 104. The RMON c o unters are also imple m ente d for jum bo frame sup ...

  • Intel IXF1104 - page 79

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 79 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.1. 7 Packe t Buffer D imens ions 5. 1.7.1 TX and R X FIF O O per atio n 5. 1.7. 1.1 TX FIFO The IXF1 104 TX FIFOs are im ple m ente d with 10 KB for each chan ne l. Th is prov ...

  • Intel IXF1104 - page 80

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 80 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 T ab le 25. RMON Additional St a tistics (Sheet 1 of 2) R MON Ethe rne t St atisti cs Gr oup 1 Stati sti cs Ty p e I XF1104-E quiva lent Sta t i st i c s Ty p e De finition of RMON ...

  • Intel IXF1104 - page 81

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 81 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5. 1.8.1 C onven tion s The fol lowi ng c onv entions are used throughou t the RMON Management Informati on Base (MIB) and its compa nion docum ents . • Good P ackets : Error ...

  • Intel IXF1104 - page 82

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 82 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.1.8 .2 IXF1 104 A d va n tage s The follo w ing list s addi tional IXF 1 104 re gist ers that support feat ures not d ocumented in RMON: • MAC (fl ow) control frames • VLAN T ...

  • Intel IXF1104 - page 83

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 83 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 • SPHY or 4 x 8 mode (f our ind ividual 8 -bit d ata buses) 5.2. 1 MPHY Ope ration The MPHY o perati on mode is s ele cted wh en bit 21 of the “SPI3 T r ansm it and Glob al ...

  • Intel IXF1104 - page 84

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 84 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.2.2 .1 T rans mit Tim ing I n MPHY mode a packe t tra nsm i ssi on s t ar ts wi th the T SX signa l indica ting port a ddress inform atio n is on the dat a bus . T he ne xt c lock ...

  • Intel IXF1104 - page 85

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 85 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Fi gur e 12 . MPHY Recei ve Lo gic a l T imi ng Figure 13. M P HY 32-Bit Interface B3217-01 TFCLK RENB RSX RSOP REOP RERR RMOD[1:0] RDAT[31:0] RPRTY RVAL 0000 B1-B4 B5-B8 B9-B12 ...

  • Intel IXF1104 - page 86

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 86 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.2.2 .3 Cloc k R at es I n MPHY mode, the TFC LK and RFCL K can be i nde pe n dent of each othe r . T FCL K and RFCL K sho uld be common to the IXF1 104 and the Netw ork P roce sso ...

  • Intel IXF1104 - page 87

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 87 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.2. 2.6 SPHY Logical Timing SPI3 interface A C t i ming for SPHY c an be found in Section 7.2 , “SPI3 AC T iming Spe cific ations ” on page 136 . Logic al timi ng i n the f ...

  • Intel IXF1104 - page 88

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 88 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 Figure 15. SPH Y Receive Logical Timing B3250-01 RFCLK RENB RSOP REOP RERR RDAT[7:0]_n RPRTY RVAL B1 B2 B3 B4 B62 B63 B64 ...

  • Intel IXF1104 - page 89

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 89 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5. 2. 2. 8. 1 Cloc k Rates The TFCLK and RFCLK can be i nde pe n dent of each othe r in SPHY mode opera tio n. TFCLK and RFCLK sho uld be common to all the Network Proce s s or ...

  • Intel IXF1104 - page 90

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 90 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.2.2. 8 .2 Parity The IXF 1 104 c an be odd or eve n (the IXF1 104 def aults t o odd) whe n calcu lat in g pa rity on th e data bus . This can be cha nged to accommod ate even pari ...

  • Intel IXF1104 - page 91

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 91 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 The IXF1 104 provides the foll owing three types of TP A signa ls: • Dedic ated per po rt Direct T rans mit P acket A vai lable (DTP A ) • Selec ted-PHY T ransm it Packe t A ...

  • Intel IXF1104 - page 92

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 92 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.2 . 3 Pre - P end ing Fu nct ion The IXF1 104 impl ement s a pre-pe ndi ng feature to allow 1518 -byte Ethern et packets to be pre- padde d with two add itional byt e s of data so ...

  • Intel IXF1104 - page 93

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 93 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.3. 1 GMII S ignal Mu ltiplexi ng The GMII balls are re assig ned whe n using the RGMII mode or f iber m ode. T able 16 “Line Si de Interf ace Multipl exe d Ba lls ” on pag ...

  • Intel IXF1104 - page 94

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 94 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 T ab le 26. GM II Interface Signal Definitions IXF 1104 Signa l GMII St andard Signa l Sou rce D e scr ipt ion TXC _0 TXC _1 TXC _2 TXC _3 G TX_ CLK IXF1 10 4 Transm it R e fer enc ...

  • Intel IXF1104 - page 95

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 95 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.4 Reduc ed Gi ga bit Medi a Ind epen den t Int erf ace ( RGM II) The IXF1 104 support s t he RGMII int e rf ac e standard as defined in th e RGMII V ers ion 1. 2 sp ec i fi c ...

  • Intel IXF1104 - page 96

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 96 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5. 4.2 T iming S p ecifi cs The IXF1 104 RGMII complies with RGMII Rev1.2a requ ire ments. T a bl e 27 prov ides the timi ng specifi cs. 5. 4.3 TX_ ER and R X_ER Codin g T o re du c ...

  • Intel IXF1104 - page 97

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 97 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Figure 19. T X _CTL Behavior Figure 20. RX _CT L Beh avior B0616-02 TXC_0:3 (at Transmitter) TD[3:0]_0:3 TX_CTL_0:3 End-of-Frame TD[3:0] TD[7:4] TX_EN=True TX_ER=False TX_EN=Fal ...

  • Intel IXF1104 - page 98

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 98 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.4 .3.1 In-Band S tatus Carri er Sense ( CRS) is g enerated by t he PHY when a packet i s rece ived from the network in te rface . CRS is indi ca ted when: • RXD V = tru e . • ...

  • Intel IXF1104 - page 99

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 99 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.5. 1 MDIO Addres s The 5-bi t P HY addre ss for the MD IO transa c t ions ca n be set in the “M DIO Si ngl e Com ma nd ($0x680)" . Bit s 5:2 of the PHY ad dres s are fi ...

  • Intel IXF1104 - page 100

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 100 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 Refer t o Fi gure 42 “ MDC Low-Spe e d Opera tion Tim ing” on page 144 for the low frequency MDC tim ing di a gram. 5. 5.5 Mana gement F r ames The M an a ge m e n t Int erf a ...

  • Intel IXF1104 - page 101

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 10 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Figure 22. M DI St ate Idl e P reamble Go = 1 Cnt = 32 Cnt < 32 St a r t B i ts Cnt = 2 Cnt < 2 Cnt > 32 Cnt > 2 Cnt > 2 Op Code Phy Ad dr Cnt = 2 Cnt < 2 Cn ...

  • Intel IXF1104 - page 102

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 102 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5. 5.8 Au toscan Operat ion The au t os ca n fu nc ti o n all o ws th e 32 re g is te rs in each ex t er nal PHY (u p to f our ) to be st ore d inte rnally in the IXF1 104. Autos c ...

  • Intel IXF1104 - page 103

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 10 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 spe ed SerDe s and are capabl e of oper a t ing in eith er an AC- or DC-coupl ed en viro nm ent. AC coupl ing is recommende d for this int erface to en su re tha t the corr e ...

  • Intel IXF1104 - page 104

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 104 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.6.2 .3 Rec ei ve r Op er at iona l Ove rvi ew The receive r structure perf orm s Clo c k and Data Rec over y (CDR) on the inco ming seria l da ta st rea m. The qual ity of this o ...

  • Intel IXF1104 - page 105

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 10 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5. 6. 2.6 T ran s mit Ji t ter The S erDe s c ore total t ransmit j itter , inc luding con tributions f rom th e intermedia te freque ncy PL L, is co mpri s ed of the followin ...

  • Intel IXF1104 - page 106

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 106 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.7 Optical M o dule Interfa ce Thi s secti on des c ribes the connecti on of the IXF1 104 por ts to an Optical Modul e Interface and det a il s the minimal con ne cti ons t hat ar ...

  • Intel IXF1104 - page 107

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 10 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.7. 2 Func tional De scription s 5. 7. 2.1 High - Spe ed Ser i a l Inte rf ac e Thes e sig n al s are res pons ible fo r tr an s fer of th e actua l da ta at 1 .2 5 Gbp s. T ...

  • Intel IXF1104 - page 108

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 108 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 The statu s of each bit (one for each port ) is found in bit s [3:0] of the “Opti cal Modul e St atus Por ts 0- 3 ($0x799 )” on page 221 ). Any cha nge in the sta te of these b ...

  • Intel IXF1104 - page 109

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 10 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Note: MOD_DEF_ INT , T X_F AUL T_INT , an d RX_LOS_INT a re open-d rain t ype ou tputs. Wi th the three si gna ls on the de vice, t he s ystem can decid e whic h “ Opt ica l ...

  • Intel IXF1104 - page 110

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 110 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 b. I nitiat e th e I 2 C trans fe r by sett ing bit [24] of the control re giste r to 0x1. c. Sele c t t he port by u s ing bits [17 : 16]. d. Sele c t the Re ad mo de of ope rat i ...

  • Intel IXF1104 - page 111

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 11 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 d. Set the Device ID Regis ter bits 14:1 1 to Ah (Atmel com pat ible). e. Se t th e 11-b it re gi s t er ad d r es s ( R eg is te r bit s 10 : 0 ) to 0F F h . f. E n abl e the ...

  • Intel IXF1104 - page 112

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 112 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.7 .3.6.1 St art Condit ion A High-to-L ow transition of I 2 C _DA T A, with I 2 C_CL K Hig h , is a start con dition th at must p rec ede any o t her co m man d (se e Figur e 26 ...

  • Intel IXF1104 - page 113

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 11 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5. 7.3. 6.4 Mem ory Res et After an in te rruption in protoc ol, power loss, or syst e m reset , any 2-wire optical modul e c an be res et by fol lowing thre e ste ps : 1. Clo ...

  • Intel IXF1104 - page 114

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 114 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.8 LED Int erfa ce The IXF 1 104 uses a Serial in terface, consist i ng of t hree si gnal s , to provi de L ED da ta to some for m of exte rnal driv er . Thi s pr ovides the data ...

  • Intel IXF1104 - page 115

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 11 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.8. 3 Mode 0: Det ail ed Oper ati on Note: Ple ase re fer to t he SG S Thomps on* M5450 datas heet for de vice-operati on info rmation. The operat i on of the LED Inte rface ...

  • Intel IXF1104 - page 116

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 116 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 When im ple m ente d on the board wit h the M54 50 device , th e LED DA T A bit 1 appea rs on Output bit 3 of the M5450 and the LED DA T A bit 2 app ears on Output bi t 4, etc. Thi ...

  • Intel IXF1104 - page 117

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 11 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Note: The LED_DA T A signal is now inv ert e d from the state in Mode 0. 5.8. 5 Powe r-On, Res et, Initi alization The LED int erface is disable d at power -on or re set. The ...

  • Intel IXF1104 - page 118

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 118 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 Note : The data dec ode of th e LED bits is indepe nde n t of the Physi ca l mode sele c t ion . 5.8 .6.1 LED Signaling Be havior Opera tion in eac h mode for th e decoded LED data ...

  • Intel IXF1104 - page 119

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 11 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.8. 6.1.2 Copper LED Behavi or 5.9 CPU Int erfa ce The CPU i nterfac e block provi des access t o regi st ers and s ta tistic s in the IXF1 104. The int erface is asy nchr on ...

  • Intel IXF1104 - page 120

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 120 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5. 9.1 Fun ctional D escrip tion 5.9.1 .1 Rea d Ac ce ss Re ad ac ces s in vol ves th e fo llo wi ng: • Dete ct a sserti on of asynchron ous Read c ontrol s ignal and lat ch a dd ...

  • Intel IXF1104 - page 121

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 12 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5. 9. 1.3 CPU Ti mi n g Pa ramet ers For informati on on the CPU interface Read and W rite cycle AC timing parameters , re fer to F igure 47 “CPU Interf ace Read Cycle AC T ...

  • Intel IXF1104 - page 122

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 122 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5.10 T A P In terf ace ( JT A G) The IXF1 104 incl udes an IE EE 1 149.1 complia nt T est Access Por t (T AP) interfac e used during bounda ry sca n testi ng. The inte rface cons i ...

  • Intel IXF1104 - page 123

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 12 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5.10.2 Instruct ion Reg ister an d Support ed Instru ctions The i ns tructi on register i s a 4-bit r e gi st er that enac ts the bo undary scan in s t ruc tions. Aft er t he ...

  • Intel IXF1104 - page 124

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 124 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 5. 10.3 I D Regist er The ID registe r is a 3 2-bi t re gis ter . The IDCODE instructi on connects thi s registe r bet ween TDI and TDO. See T a ble 112 “JT AG ID ($0x50 C)” on ...

  • Intel IXF1104 - page 125

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 12 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Note: There is a restr iction when us ing this loo pback mode. At lea s t one cloc k cyc le is r equi re d betwe en a T EOP ass ertion and a TSOP a ssert ion. T his i s requir ...

  • Intel IXF1104 - page 126

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 126 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 When th e IXF1 104 is c onfi gured in this loopba c k mod e, al l of t he MAC function s and fe ature s are ava ilabl e , i ncludi ng flow control and pa use-pa c ket genera tion. ...

  • Intel IXF1104 - page 127

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet M edia Access Con trol ler Datasheet 12 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 5. 12.1 .1 CLK1 25 The sys te m inte rfa c e c loc k, whi ch s uppl ies the cloc k to the majority of the in ternal cir cui try , is the 125 MHz clock. The sourc e of this c l ...

  • Intel IXF1104 - page 128

    IXF1 104 Quad-Port 10/100/ 1000 M bp s Ethernet Me dia Access Cont roller 128 Datasheet Documen t Numb er: 27875 7 Revis ion Number: 00 7 Revision Date: M arch 2 5, 2004 • 43/ 5 7 d u ty cy cl e fo r 18 M H z op e r a t io n 5. 12.5 J T AG Cloc k The IXF1 104 s uppor ts JT AG . The source of thi s clock m ust m eet the f ollowing spe cific a tion ...

  • Intel IXF1104 - page 129

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 12 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 6.0 Appli cations 6.1 Chan ge Por t Mo de In itiali zat ion Se quen ce Use the cha nge port mode ini t i al ization seque nc e after powe r -up an d anyt im e a port is configure d into or ...

  • Intel IXF1104 - page 130

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 130 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 Ena ble p acket pa dding and CR C appe ndin g on t ransmit ted pa cket s i n b its 6 and 7, as ne ed ed . Se t bit 5 t o 0x0. b. Fi ber Mode : W rit e the reserv ed bi ts t o the d efa ult valu e. ...

  • Intel IXF1104 - page 131

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 13 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 7.0 Electrical S pecifications T able 39 through T a ble 5 8 “LED I nterface AC T iming P arameters ” on page 153 a nd Figur e 35 “SPI3 Receiv e Inte rface T imi ng” on page 136 thr ...

  • Intel IXF1104 - page 132

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 132 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7.1 DC Speci fic ati ons The IXF1 104 suppor ts the following I/O buf fer t ypes: • 2.5 V CMOS • 3. 3 V L V T TL • SerDes T ab le 40. Recomm e nd ed Op erating Condit ions Par am ete r Sym bo ...

  • Intel IXF1104 - page 133

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 13 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 See Sect ion 5.1.7, “P acket Buf fe r Di mension s” on pa ge 79 f or addi tio nal in formation rega rding I/ O buf fe r types. The relat ed dri ve r character istics are des cri bed in ...

  • Intel IXF1104 - page 134

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 134 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7. 1.1 Un dersh oot / Ov er s hoot S pecific ations The overshoo t figures give n in thi s sec ti on represe nt the maxim um voltage th a t can be appl ie d witho ut af f e cting th e rel ia bilit ...

  • Intel IXF1104 - page 135

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 13 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a bl e 4 5 . R GM I I Po we r Symbo l P arame ter Con dit ions Min Ma x Units V OH Out put Hig h V o ltag e I OH = -1.0 M A; V CC = M IN 2.0 VDD +.3 V V OL Out put Lo w Volta ge I OL = 1. ...

  • Intel IXF1104 - page 136

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 136 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7. 2 S PI 3 A C T iming S pec i ficat ions 7. 2.1 Receive Int erf ace T imi ng Fi gure 35 a nd T able 46 ill ustra te and provi de SP I 3 rec eive int erfac e timing infor mation. Figure 35. SPI3 R ...

  • Intel IXF1104 - page 137

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 13 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 46. SPI3 Receive Interface S ignal Par ameters Symbol Param eter Min M ax Un its – RFCL K freq uency – 133 MHz – R FCLK du ty cyc l e 40 60 % T srenb REN B set up ti me to R F ...

  • Intel IXF1104 - page 138

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 138 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7. 2.2 T ransmit In terface T imin g Fi gure 36 a nd T able 47 il lu st r at e an d pr o v id e SPI 3 tr an s m it in te r f ac e ti m i ng in f o r ma ti o n. Figure 36. SPI3 T ran smi t Interface ...

  • Intel IXF1104 - page 139

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 13 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 47. SPI3 T ran smi t Interface Signal Param eters Sy mbo l Par a met er Mi n M ax U n its – T FCL K fr eq ue ncy – 1 33 M Hz – TFCLK duty cycle 40 60 % TStenb T ENB se tu p ti ...

  • Intel IXF1104 - page 140

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 140 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7.3 RGMII AC T imin g Specific ati on Fi gure 37 a nd T able 48 provid e RGMII interface timin g paramete rs . Figu re 37 . RG MII I nte rfa ce Timing T ab le 48. RGMII Interface Timing P aram eter ...

  • Intel IXF1104 - page 141

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 14 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 7.4 GMII A C Timing Spec ificat ion 7.4. 1 100 0 Base -T Oper ation Figure 38 and Figure 39 and T able 49 and T able 50 provid e GMII AC timing specifica tions . 7. 4.1.1 100 0 BAS E-T T ra ...

  • Intel IXF1104 - page 142

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 142 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7.4.1 .2 1000 BA SE -T Rece i ve Inte rfac e Figure 39. 100 0BASE-T Re ceive Inter f ace Timing T ab le 50. GMII 1000BASE -T Receive Sign al Parame ters Symbol Para meter Min T yp 1 Max Unit 2 t1 R ...

  • Intel IXF1104 - page 143

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 14 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 7.5 SerD es A C T imi ng S p eci ficat ion Figure 40. S er Des Timing Diagram T abl e 5 1. S erDes Timi ng P ar amet ers Sy mbo l Par a met er Mi n M ax U n its Tt Transmi t e ye wid th 800 ...

  • Intel IXF1104 - page 144

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 144 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7.6 MDIO AC Timing Sp ecifica tion The MDIO Interfa ce on the IXF1 104 can oper ate in two modes – low-s pe e d and high-spe e d . In low-s pe e d mode, the MDC clock signal operate s at a freque ...

  • Intel IXF1104 - page 145

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 14 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 7.6.3 MDIO AC Tim ing Figur e 43 . MDIO W rite T iming Diag ram Figure 44. M DI O Read Ti ming Diag ram T a bl e 5 2 . M D IO Ti min g Pa r am et ers Para mete r Sy mbol M in T yp 1 M ax U ...

  • Intel IXF1104 - page 146

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 146 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7.7 Optical M o dule and I 2 C A C Ti mi ng Sp eci fic at ion 7. 7.1 I 2 C Int erface Timi ng Fi gure 45 a nd Figur e 46 il lus trat e bus timing and write cyc l e, a nd Ta b l e 5 3 sh ow s th e I ...

  • Intel IXF1104 - page 147

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 14 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 t SU .S T A St art se tup ti me 4.7 – µs t HD.DA T D ata in hold ti me 0 – µ s t SU .DAT Data in setu p time 200 – ns t R Inp uts rise ti me – 1.0 µ s t F Inp uts fa ll tim e – ...

  • Intel IXF1104 - page 148

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 148 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7.8 CPU AC Timing S p e cifica tion 7. 8.1 CPU Inter face Read Cycle AC T iming Fi gure 47 , Figur e 48 , a nd T able 54 i ll ustr ate the CPU in ter fa ce r ead and writ e cy cle AC t iming. 7. 8. ...

  • Intel IXF1104 - page 149

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 14 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 5 4. CPU Inter face Write Cycle AC Signal Par ameters Symb ol Par ameter Min Max T cas Ad dress, chip s el ect set up time 5 ns – T cah Ad dr ess, chi p sel ect hold ti me 10 ns ? ...

  • Intel IXF1104 - page 150

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 150 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7. 9 T rans mit Paus e Contr ol A C T imi ng Sp ecif ica tio n Fi gure 49 a nd T able 55 show th e pause cont rol AC ti m i ng sp ecifi c atio ns. The Pause Con trol inte rface operate s as an asyn ...

  • Intel IXF1104 - page 151

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 15 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 7. 10 JT A G AC Timi ng Speci fic ati on Figure 50 and T a bl e 56 prov ide t he J T AG AC timing spec ifi cations. Figure 50. JT AG AC T iming T a ble 5 6. JT AG AC Timing Parameters Sy mb ...

  • Intel IXF1104 - page 152

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 152 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 7.1 1 Syst em AC Timing Specif icati on Fi gure 51 a nd T able 57 illust rat e the syste m reset AC timin g spec ifica tion s. Figure 51. System Reset AC Timing T ab le 57. System Re set AC Timing ...

  • Intel IXF1104 - page 153

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 15 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 7. 12 LED AC Tim ing Spec ifi catio n Figure 52 and T a bl e 58 prov ide the LED AC tim ing spe ci fications. Fi gur e 52 . LED AC I n te rf ac e T i min g T a ble 58. LED Interface AC Timi ...

  • Intel IXF1104 - page 154

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 154 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 8.0 Register Set The re gisters s hown in thi s section pr ovide a cc es s for c onfiguratio n, alarm m oni toring, an d control o f t he ch ip. T able 59 “MAC C ontrol Registers ($ P ort In de x ...

  • Intel IXF1104 - page 155

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 15 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 8.3 Per P o r t Re gist ers Secti on 8. 4 cove rs all of th e registe rs that are repli c ated i n each port o f the IXF1 104. These regis ters perform a n iden tical f unction in each port ...

  • Intel IXF1104 - page 156

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 156 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 “Max Fr am e S ize (A ddr: P or t_Ind ex + 0x 0F) ” 32 R/W 165 0x0F “M AC IF Mo de an d RG M II S p ee d ($ Port _In d ex + 0x 10 )” 32 R/W 16 6 0x10 “F lu sh TX ( $ P or t_I ndex + 0x1 1 ...

  • Intel IXF1104 - page 157

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 15 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 RxUnknownMacControlFrameCount er 32 R 17 3 0x 33 RxV eryL ongErrors 32 R 17 3 0x 34 RxRuntErrors 32 R 17 3 0x 35 RxShortErrors 32 R 17 3 0x 36 RxCarrierExte ndError 32 R 17 3 0x 37 RxSequen ...

  • Intel IXF1104 - page 158

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 158 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 62. PHY Autoscan Reg isters ($ Port Inde x + O ffset) Reg ister Bit S i z e Mo de 1 Re f Page Offset “PHY Co ntrol ($ Port Index + 0x60)” 32 RO 18 0 0x60 “PHY Status ($ Port Index + 0 ...

  • Intel IXF1104 - page 159

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 15 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 “R X F I F O Low W ate r mark Po r t 3 ( $ 0x5 8D)” 32 R /W 19 4 0x58 D Re ser ved 32 RO – 0x58E - 0x5 93 RX F IFO Ov erflo w Fra me Drop Coun ter Por t 0 3 2 R 19 4 0x594 RX F IFO Ov ...

  • Intel IXF1104 - page 160

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 160 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 Rese rve d 32 RO – 0x60 E - 0x 613 TX FIFO MAC Thr eshold Port 0 3 2 R/W 204 0x 614 TX FIFO MAC Thr eshold Port 1 3 2 R/W 204 0x 615 TX FIFO MAC Thr eshold Port 2 3 2 R/W 204 0x 616 TX FIFO MAC T ...

  • Intel IXF1104 - page 161

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 16 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Re served 32 R – 0x70 2 - 0x7 09 “Address Pa rity Erro r Packet Drop C ounter ($0x7 0A)” 32 R 218 0x 70 A Re ser ved 32 R – 0x70B - 0x7 16 T a ble 6 8. SerDes Reg isters ($ 0x78 0 - ...

  • Intel IXF1104 - page 162

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 162 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 8.4.1 MAC Control Registers Ta b l e 7 0 through T able 92 “Port Multica st Addre ss ($ Port_In dex +0x1A – +0x1B )” on page 172 pr ovid e de t ai ls on the control an d statu s regis te rs a ...

  • Intel IXF1104 - page 163

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 16 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 73. Col lision Distance ($ Port_Index + 0x05) Name Desc ripti on Add res s T y pe 1 Default Col lisio n Distance This is a 1 0-bit valu e that s e t s the limi t f or lat e coll is ...

  • Intel IXF1104 - page 164

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 164 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 77. IPG Receive Time 1 ($ Po rt_Index + 0x0A ) Name Descriptio n Address T ype 1 Default IPG Rec ei ve T im e 1 Th is tim e r is use d du rin g half -du pl ex ope ra tio n whe n ther e is a ...

  • Intel IXF1104 - page 165

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 16 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 8 0. Pause T hreshold ($ Port_I ndex + 0x0E ) Name De scription Address T ype 1 De fault Pause Thres hold W hen a pa use fram e has be en se nt , a n i nte rn al time r c hecks wh e ...

  • Intel IXF1104 - page 166

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 166 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 82. MAC IF Mode and RGMII Speed ($ Port_Index + 0x10) Bi t Nam e Des crip tion T y pe 1 Default Reg ister D e scrip tion – M A C I F M o de: Dete rm in es th e MA C op er ati on fr eq ue ...

  • Intel IXF1104 - page 167

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 16 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 8 4. FC Enab le ($ Port_Index + 0 x12) Bi t Nam e Des cri pt io n Type 1 De fault Reg iste r De sc ript ion: Indic ates w hich fl ow cont rol mod e is use d f or the RX an d TX MAC. ...

  • Intel IXF1104 - page 168

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 168 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 86. Short Runts Thre shold ($ P ort_Ind ex + 0x14) Name Descripti on Addr ess T ype 1 Default Shor t Runt s Th res hol d The 5- bit conf igura tio n hold s th e value in by tes, whi ch a pp ...

  • Intel IXF1104 - page 169

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 16 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 19 RX Co nfi g 0 = Recei ving id le /dat a strea m 1 = Recei ving /C / order ed set s RO 0 18 Con fig C hange d 0 = RxCo nfi gWor d has chan ged si nc e last rea d 1 = RxC onf igW ord has n ...

  • Intel IXF1104 - page 170

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 170 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 13:1 2 2 Rem ote Faul t [1:0 ] Remo te fa ult d efini tions : 00 = No er ro r , lin k oka y 01 = Off line 10 = Li nk f ail ure 1 1 = Aut o-ne gotiat ion _E rror R/W 00 1 1: 9 Res er ved Writ e a s ...

  • Intel IXF1104 - page 171

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 17 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 3:2 2 Rese rved Writ e a s 1, ig nore on Re ad . R/ W 1 1 1 2 Re served Wr it e as 0, ig nor e on Re ad. R/ W 0 0 2 Re served Wr it e as 1, ig nor e on Re ad. R/ W 1 T a ble 90. Di verse Co ...

  • Intel IXF1104 - page 172

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 172 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 2 B /Cas t Drop En T his b it ena ble s a G loba l fi lt er o n br oad c ast f rames . 0 = All br oadc as t frame s are p assed to the S PI3 Inte rfa ce. 1 = All br oadc as t frame s are drop ped. ...

  • Intel IXF1104 - page 173

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 17 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 8.4. 2 MAC RX S ta tistics Reg ister O verview The MAC RX Stati s tics re gisters c ontain th e MAC re c eive r stati st ic c ounters a nd are cl eare d whe n re ad. Th e s oftw are p oll s ...

  • Intel IXF1104 - page 174

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 174 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 RxP kts 65to 12 7 Octet s T he to tal nu mber of pac kets re ce ived (i nc ludi ng bad packets ) tha t we re 65 -127 octets i n len gth. Inc reme nted for tag ged p ackets with a le ngth of 65- 127 ...

  • Intel IXF1104 - page 175

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 17 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 RxAlignErrors 3 Fra mes with a le gal fram e siz e, but c o ntai ning less than eig ht ad ditio nal b its. T his occur s wh en the frame is not by te alig ned. The CRC of th e fram e is wr ...

  • Intel IXF1104 - page 176

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 176 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 RxRuntE rrors 3 T he to tal nu mber of pac kets re ce ived th at ar e les s tha n 64 oct ets in leng th, b ut long er tha n or equ al to 96 b it tim es, which cor respo nds to a 4- by te fra me wi ...

  • Intel IXF1104 - page 177

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 17 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 8.4. 3 MAC T X St ati stics R egister Overview The M A C TX S tat is tics r egi ste rs conta in all th e MAC t r a nsmi t st atisti c cou n te rs and ar e clear e d wh en read . The so ft w ...

  • Intel IXF1104 - page 178

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 178 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 Tx BCP kt s Th e t otal nu mber of broad cast p a cket s tran s mi tte d (ex c l ud in g ba d pac ke ts) . Por t _Ind ex + 0x 44 R 0 x000 00 00 0 TxP kts64 Octets Th e tota l numb er of p ac k et s ...

  • Intel IXF1104 - page 179

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 17 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 TxSin gl eCo llis io ns A cou n t of successf ully t ransmi t t e d fr ame s on a par t icul ar inter fa ce wh er e th e tr ans mi ssio n is in hi bit ed b y exa ctl y one co ll is io n. A ...

  • Intel IXF1104 - page 180

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 180 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 8. 4.4 PH Y Auto sca n Regi sters Note : These re gis t er hold th e current value s of the P HY regi s ters onl y when Autos ca n (s ee Section 5.5.8, “Auto s can Operat ion ” on pa g e 102 ) ...

  • Intel IXF1104 - page 181

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 18 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 12 Au to-N egot iat ion Enable 0 = Dis ab le au to -ne got iati on pr oces s 1 = Enabl e a ut o-neg ot ia tio n pr oce ss Thi s regi ster bi t m ust be en able d f or 1000BASE -T o peratio ...

  • Intel IXF1104 - page 182

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 182 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 10 100 BASE-T2 Fu ll- Duple x 0 = PHY not ab le to ope rate in 10BASE -T2 in full - dupl ex mod e (not s upport ed) 1 = PH Y ab le to ope rat e i n 100B AS E-T2 i n f ull- dupl ex m ode RO 0 9 100 ...

  • Intel IXF1104 - page 183

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 18 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 15:1 0 PHY I D Numb er The PHY i dent if ier is com posed of regi ster b its 24: 19 of th e OUI ( Organ i zati on ally Uniq ue Ident ifier) R O 0 1111 0 9:4 Man uf actu r er’s Mo del Si x ...

  • Intel IXF1104 - page 184

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 184 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 6 10B ASE-T Fu ll- Duple x 0 = DTE i s not 1 0B ASE-T , ful l -d uple x mode capa bl e 1 = DT E is 1 0BASE-T , ful l-duple x mode capab le RO 1 5 10B ASE-T Ha lf -Dup lex 0 = DT E is not 10BAS E-T ...

  • Intel IXF1104 - page 185

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 18 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 7 100B A SE-T X Half-Duplex 0 = L ink partner i s no t 100 BASE-TX, half- duplex mo de capa bl e 1 = Li nk p a rtner is 100 BASE - TX, ha lf-d uple x mo de capa ble RO 1 6 10BASE -T Fu ll- ...

  • Intel IXF1104 - page 186

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 186 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 102 . Auto-Negotiation Next Page T ransmi t ($ Port Index + 0x67) Bi t Nam e Des crip tion T y pe 1 Default 31:1 6 Reserve d Reser ved RO 0 15 Ne xt Pa ge (N P) 0 = Las t pa ge 1 = Additi o ...

  • Intel IXF1104 - page 187

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 18 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 8.4. 5 Global St atus an d Conf iguration Registe r Overv iew Ta b l e 1 0 3 th rough T able 1 12 “JT AG ID ($0x50C)” on pag e 191 pr ovide a n ov erview f or th e Globa l Control and S ...

  • Intel IXF1104 - page 188

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 188 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 105 . Link LED Enable ($0x50 2) Bi t Nam e D escr ip t io n T y pe 1 Default Reg ister D e scrip t i on: Per por t bit shou ld b e se t upo n de tecti on of link to e nabl e pro per oper at ...

  • Intel IXF1104 - page 189

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 18 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 107. MDIO Soft Reset ($0x506) Bi t Nam e Des cri pt io n Type 1 De fault Reg iste r De sc ript ion: Sof twa re- a ctiv at ed rese t of the MDIO mod ule. 0 x0000 00 00 31: 1 Rese rve ...

  • Intel IXF1104 - page 190

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 190 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 1 10. L ED Flash Rate ($0x50A) Bi t Nam e Des crip tion T y pe 1 Default Reg ister D e scrip t i on: Gl obal s elec tio n of LE D fl ash r ate . 0x 0000 00 00 31: 3 Re ser ved Re s erved RO ...

  • Intel IXF1104 - page 191

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 19 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 1 12 . JT AG ID ($ 0x50C) Bi t Nam e Des cri pt io n Type 1 De fault Reg iste r De sc ript ion: The val ue of th is re giste r fol lows t he same sch eme as th e device identifi cat ...

  • Intel IXF1104 - page 192

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 192 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 8. 4.6 RX F IFO Regist er Overview T a ble 11 3 thro ugh T able 13 1 provide an o ve rv iew o f the RX FIFO re gisters, wh ic h inc lude the R X FIFO High a nd Low watermarks. T ab le 1 13. RX FI F ...

  • Intel IXF1104 - page 193

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 19 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 1 16. RX FIFO High W a termark P ort 3 ($0x583) Bi t Nam e Des cri pt io n Type 1 De fault Reg iste r De sc ript ion: T he d e fau lt va lu e of 0x 0E 6 re p resen ts 23 0 eig ht -b ...

  • Intel IXF1104 - page 194

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 194 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 2 T ab le 1 19. RX FIFO Low Watermark Po rt 2 ($0x58 C) Bi t Nam e Des crip tion T y pe 1 Default Reg ister D e scrip t i on: T he def aul t v alu e o f 0 x07 2 re p resen ts 1 14 ei ght- byt e l o ...

  • Intel IXF1104 - page 195

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 19 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 122. RX FIFO Port Reset ($0x59E) Bi t Nam e Des cri pt io n Type 1 De fault Reg iste r De sc ript ion: Th e so ft re set re gister for each port in th e R X blo ck. Port ID = b it p ...

  • Intel IXF1104 - page 196

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 196 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 2 RX FIF O Errore d F rame Dr op E na ble Po rt 2 This bit i s us ed in co njunct ion wi th MA C filte r bit s. Thi s all ows t he us er to sel ect wh ethe r the erro red pac ke ts a re to be d rop ...

  • Intel IXF1104 - page 197

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 19 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 1 25. RX F IFO Errored Frame Dr op Co unter Po rt s 0 - 3 ($0x5 A2 - 0x5A5) (S heet 1 of 2) Name Descriptio n Add ress T y pe Defa ult RX FIFO E rrored Fr ame Dr op Co unter on P or ...

  • Intel IXF1104 - page 198

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 198 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 RX FIF O Errore d F rame Dr op C o unte r on P ort 2 This regist er coun ts a l l fr a mes drop ped f rom the RX FIF O for por t 2 by mee tin g on e of the fol lowin g cond it ion s : • Frames ar ...

  • Intel IXF1104 - page 199

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 19 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 127. RX FIFO Padding and CRC S trip Enab le ($0x5B 3) Bi t Nam e Des cri pt io n Type 1 De fault Reg iste r De sc ript ion: T his con tr ol r egi st er en able s to pre -pend e ve r ...

  • Intel IXF1104 - page 200

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 200 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 128 . RX F IFO T ransfer T hreshold P ort 0 ($0x5B8 ) Bit Nam e Des crip tion T ype Def ault Reg ister D e scrip t i on: R X FI FO t r ansf er thr esh ol d for po rt 0 i n 8- byte l oc ati ...

  • Intel IXF1104 - page 201

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 20 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 130. RX FIFO T ransfer Thresh old Port 2 ($0x5BA) Bi t Nam e D escr i ptio n T yp e De fa ult Reg iste r De sc ript ion: R X FI FO t rans fer thr es hold fo r p ort 2 in 8-by te lo ...

  • Intel IXF1104 - page 202

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 202 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 8. 4.7 TX FIFO R egi ster Ove rview T a ble 13 2 thro ugh T able 139 provid e an over view of the TX FI F O regi sters, whic h in clu de the TX FIFO High a nd Low watermark. T ab le 132. TX FIFO Hi ...

  • Intel IXF1104 - page 203

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 20 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 1 33. TX FIFO L ow Watermar k Register Ports 0 - 3 ($0 x60A – 0 x60D) Na me Desc ript io n Add res s T ype 1 De faul t TX FIFO Lo w W a terma rk Port 0 Low watermark for TX FIFO P ...

  • Intel IXF1104 - page 204

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 204 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 134 . TX F IFO M AC Thre shold Reg ister Po rts 0 - 3 ($0x614 – 0x 617) Name Descr iption Addr ess T ype 1 Default TX FIFO MAC T hre sh ol d Por t 0 MAC thr eshol d fo r TX FIF O Po rt 0. ...

  • Intel IXF1104 - page 205

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 20 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 1 35. TX FIFO O verflow/Un derflow/Out o f Seq uence Event ($0x61E ) (Sh eet 1 o f 2) Bi t Nam e Des cri pt io n Type 1 De fault Reg iste r De scr ipti on: TX FIFO Out o f Se qu enc ...

  • Intel IXF1104 - page 206

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 206 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 2F O E 2 Por t 2 0 = FIFO ov er flow ev e nt di d no t occ ur 1 = FIF O o ver fl ow even t o c cur red R0 1F O E 1 Por t 1 0 = FIFO ov er flow ev e nt di d no t occ ur 1 = FIF O o ver fl ow even t ...

  • Intel IXF1104 - page 207

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 20 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 2P o r t 2 R e s e t Port 2 0 = De- ass e rt R ese t 1 = Ass e rt R e set R/W 0 1P o r t 1 R e s e t Port 1 0 = De- ass e rt R ese t 1 = Ass e rt R e set R/W 0 0P o r t 0 R e s e t Port 0 0 ...

  • Intel IXF1104 - page 208

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 208 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 139. TX FIFO Erro red Fr ame Drop Counte r P o rts 0 - 3 ($0x 625 – 0x629) Name Descri ption Addre ss T ype * Default TX FI FO erro red f rame dr op cou nt er on P ort 0 Thi s regis ter p ...

  • Intel IXF1104 - page 209

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 20 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 1 40. TX FIFO Occupancy Co unter fo r Po rt s 0 - 3 ($0x62D – 0x 630) Na me De scri pti on Ad dr ess T ype Defau lt Occ upanc y for T x FIFO Port 0 Thi s regi ste r gives t he O c ...

  • Intel IXF1104 - page 210

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 210 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 8. 4.8 MDIO R egiste r Overview T able 142 through T able 145 pro vide an overview of the MDIO r egisters. T ab le 142 . MDIO S ingle Comm an d ($0x680) Bi t Nam e Des cri ptio n T ype 1 Defa ult R ...

  • Intel IXF1104 - page 211

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 21 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 T a ble 144. Autoscan PHY Address Enab le ($0x682 ) Bi t Nam e Des cri pt io n Type 1 De fault Reg iste r De sc ript ion: Defi ne s vali d P HY add r esses . Ea ch bit enab le s the cor res ...

  • Intel IXF1104 - page 212

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 212 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 8. 4.9 SPI 3 Registe r Overview T able 146 through T abl e 148 “Address Pari ty E rr or Packet Drop Cou nte r ($0x70A) ” on page 218 pr ovid e a n overvi e w of the SPI3 reg is te rs. T ab le 1 ...

  • Intel IXF1104 - page 213

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 21 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 16 Dat _prtye r_dr p Port 0 SPHY/MP HY Mode: Ind ica tes wh et her to dr op pa ck ets w i th da ta pa rit y error for p ort 0. 0 = Do n ot dro p pack ets wit h data par ity e rr or (d ef au ...

  • Intel IXF1104 - page 214

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 214 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 2 Tx_p or t_ena ble P or t 2 SPHY Mo de: 0 = Di sabl es th e se le ct ed S PI 3 T X p or t 2 1 = Ena bl es the sel ect ed SP I 3 TX por t 2 MPHY Mod e: 0 = Di sabl es th e se le ct ed S PI 3 T X p ...

  • Intel IXF1104 - page 215

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 21 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 2 5 B 2B_ P AU SE P or t 1 SPHY M ode: Ind icates the nu mb er of pau se cycl es to be int roduc ed betw een b ack- to -back t ran sfers fo r por t 1. 0 = Zero paus e cy cl es 1 = T w o pau ...

  • Intel IXF1104 - page 216

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 216 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 17:16 RX _BURST Port 0 SPHY Mode: Selects the m aximu m bu rst s ize on the R X path for port 0 . 0x = 64 byt es maximu m burs t s ize 10 = 128 by t es ma ximum bur st size 1 1 = 256 by tes ma ximu ...

  • Intel IXF1104 - page 217

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 21 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 11 Rx _port _ena ble Port 3 SPHY M ode: 0 = Dis ab le s the sel ec te d S PI3 RX po rt . 1 = Enabl es the s elec ted SP I3 RX p ort . MPHY Mo de : 0 = Dis ab le s the sel ec te d S PI3 RX p ...

  • Intel IXF1104 - page 218

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 218 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 148. Address Pari ty Error Pa cket Drop Coun ter ($0 x70A) Bi t Nam e Des crip tion T y pe 1 Default Reg ister D e scr i pti on : Thi s regi ster co unt s the nu mber of pa cke ts d r opped ...

  • Intel IXF1104 - page 219

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 21 9 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 8.4. 10 SerDe s Register Ove rview T able 149 through T able 152 “Clock and Interfa c e Mode Cha nge Enable Ports 0 - 3 ($0x794 )” on page 220 defin e the cont ent s of the SerDes re gi ...

  • Intel IXF1104 - page 220

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 220 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 152 . Clock and Interface Mode Change E nable Port s 0 - 3 ($0x794) Bi t Nam e Des crip tion T ype 1 Defa ult Reg ister D e scr i pti on : Thi s regi ster i s used whe n a cha ng e to th e ...

  • Intel IXF1104 - page 221

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 22 1 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 8.4. 1 1 Op tical Mo dule Reg ister Ove r vi ew T able 153 throug h T ab le 156 “I2C Data Ports 0 - 3 ($0x79 F )” on pa ge 222 provide an overvi ew of th e Opti c al Modul e Registe r s ...

  • Intel IXF1104 - page 222

    IXF1 104 4-Port Gigabit Ethern et Media Access Contro ller 222 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 T ab le 155. I 2 C Co ntro l Ports 0 - 3 ($0x79B) Bi t Nam e Des crip tion T y pe 1 Default Re gist er Desc ri pti on: Thi s regi ster contr ols an d mon itors the inte r f a ce t o the op ti cal m ...

  • Intel IXF1104 - page 223

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 22 3 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 9.0 Mechanical Speci fications The IXF1 104 is packag e d in a 576-bal l BGA pa ckag e with 6 balls remov ed dia gonall y from eac h corne r , for a tot al of 552 ba lls use d measuri ng 25 ...

  • Intel IXF1104 - page 224

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller 224 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 9. 3 P acka ge In fo r ma tio n Figure 55. CBGA Package Diagram B0034-01 3.902 3.938 Chip Substrate 7.804 7.877 (25 ± 0.2) (25 ± 0.2) 47P6802 Note: All dimensions are in mm. B0035-03 (25 ± 0.2 ...

  • Intel IXF1104 - page 225

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 22 5 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 Figure 56. CB GA Pa ckage Side View Diagram B0555-01 Seating Plane 0.15 C (4.237 Max) (3.619 Min) (3.327 Max) (2.809 Min) (0.857 Max) (0.779 Min) (4.16 Max) (3.43 Min) (6X) (3.24 Max) (2.72 ...

  • Intel IXF1104 - page 226

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller 226 Datasheet Docume nt Num ber: 2787 57 Revision Number: 0 07 Revis ion Date: March 25, 2004 9. 3.1 Exam ple P ackage M ar k ing Figu re 57. I nte l ® IXF1 104 E xamp le Package Mark in g 25. 0 mm 7. 5 x 7 . 5 mm 25. 0 mm P in 1 m ark AAA00 0AAA = Int el Product Number Cou nt r y XX = I ...

  • Intel IXF1104 - page 227

    IXF1 104 4 -Port G igabit Et hernet Media A ccess Controller Datasheet 22 7 Documen t Numbe r: 2 78757 Re vi sion N u mber : 007 Revision Date: M arch 2 5, 2004 10.0 Produ ct Orderi ng In forma ti on T able 157 and Fi gure 58 pro vide IXF1 104 pr oduct ordering informat ion. T abl e 1 57. P rod uct In f orm a tio n Num ber Revi si on Qu ali fi cat ...

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- #BRANDの図面#
- IXF1104の取扱説明書
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それらは全部重要ですが、デバイス使用の観点から最も重要な情報は、Intel IXF1104の取扱説明書に含まれています。

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Intel IXF1104デバイスの取扱説明書はどのようなものですか?
取扱説明書は、ユーザーマニュアル又は単に「マニュアル」とも呼ばれ、ユーザーがIntel IXF1104を使用するのを助ける技術的文書のことです。説明書は通常、全てのIntel IXF1104ユーザーが容易に理解できる文章にて書かれており、その作成者はその分野の専門家です。

Intelの取扱説明書には、基本的な要素が記載されているはずです。その一部は、カバー/タイトルページ、著作権ページ等、比較的重要度の低いものです。ですが、その他の部分には、ユーザーにとって重要な情報が記載されているはずです。

1. Intel IXF1104の説明書の概要と使用方法。説明書にはまず、その閲覧方法に関する手引きが書かれているはずです。そこにははIntel IXF1104の目次に関する情報やよくある質問、最も一般的な問題に関する情報を見つけられるはずです。つまり、それらはユーザーが取扱説明書に最も期待する情報なのです。
2. 目次。Intel IXF1104に関してこのドキュメントで見つけることができる全てのヒントの目次
3. Intel IXF1104デバイスの基本機能を使うにあたってのヒント。 Intel IXF1104のユーザーが使い始めるのを助けてくれるはずです。
4. トラブルシューティング。Intel IXF1104に関する最も重要な問題を診断し、解決するために役立つ体系化された手続き
5. FAQ。よくある質問
6. 連絡先。一人では問題を解決できない場合に、その国におけるIntel IXF1104のメーカー/サービスへの連絡先に関する情報。

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