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8XC196MC, 8XC196MD, 8XC196MH M i cr o co n tr o l l e r U ser ’ s M a nual ...
We V alue Y our Opinion Dear Inte l Cus tomer: W e have updated th e infor ma t ion that was provided in the 1992 version of the 8XC196MC User ’ s Manual , added in fo rmation a b out the 8 XC196M D and 8XC1 9 6MH, and c o rrected known errata. W e hope these chan ges make i t easier for you t o use o ur products. Y our feedbac k will help us t o ...
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8XC 196MC, 8XC196M D, 8XC196MH Micr oc ontr olle r User ’ s Manu al August 2004 Order Number 272181-00 3 ...
Informa tion in thi s document is provided sole ly to enabl e use of Intel products . Intel assu mes no li ability w hatsoev er , incl udin g infringem ent of an y patent or copyrig ht, for sale and use o f Intel products except as provi ded in Intel’s T erms and Co nditi ons of S ale for such products. Intel Corporation makes no warranty for the ...
iii CONTENT S CHAPTER 1 GUIDE T O THIS MANUAL 1. 1 MANU AL CON TENTS ... . .... . .... . . . .... . . .......... .. . .... . .... . .... . .... . .... . .... . .... . .... . ... .. . . . .......... . . . ... 1-1 1.2 NOTATI ONAL CO NVENTI ONS AN D TERMIN OLOG Y ... . .... . .... . . . .... . .... . . .......... .. . .... . ... 1-3 1. 3 REL AT ED DOC ...
8XC1 96MC, MD, MH USER’S MANUAL iv CHAPTER 3 PROGRAMMING C ONSIDERATIONS 3.1 OVERVIEW OF THE INSTRUCTION SET . . ........ ............... . . ............... . ...... . . ............... . . 3-1 3.1.1 BIT Operands ........ ... .. ................... . .... ...................... . .... . ...... ...................... ............... 3 - 2 3.1.2 B ...
v CONTENTS 4.1.5.1 Memory-mapped SFRs .. ............... . . ............... . . ............... . .... . . ............... . . .............4-5 4.1.5.2 Peripheral SFRs . . . ..... . . ..... ... . . . . ..... ..... ... . . . . ..... ...... ..... . . ..... . . . . ..... ..... ... . . . . ..... ... . . . . ....4-5 4.1.6 Register F i le .......... ... ...
8XC1 96MC, MD, MH USER’S MANUAL vi 5.6.6 Serial I/O Modes .................... ... ......... ... .. . ................ ... .. ... ......... . ................ ... .. ... .....5-37 5.6.6.1 Sy nchronous SIO Trans m it Mode Example . .... ....... ..... ........ . .... ....... . ........ ..... ....5-43 5.6.6.2 Sy nchronous SIO R e ceive Mode Example ...
vii CONTENTS 7.4.5 Determining Seri al Port St atus ......... . .. . . . ........... . .............. . . .. . . . .. . . . ...................... .. . .. 7-15 CHAPTER 8 FREQUENCY GENERATOR 8.1 FUNCTIONAL OVERVIEW.......... ................. . . ............... . . ............... . .... . . ............... . . ....... 8 -1 8.2 PROGRAMMING THE FREQ ...
8XC1 96MC, MD, MH USER’S MANUAL vi ii 10.5.2 Reading the Curr ent Value of the D o w n-counter ................. . .. ................................1 0 -7 10.5.3 En ablin g the PW M Outputs ................................................................. .................... 1 0-8 10.5.4 Gene r ating Analog O utpu ts .......... . . ........ .. ...
ix CONTENTS 12.6.1.4 Using Mixed Analog and Digital Inp uts .......... . .... . . ............... . . ............... . .... . . .... 12-13 12.6.2 Understanding A/D Conversion Er rors ................ ...................... . ................ ... .. ..... .12-13 CHAPTER 13 MINIMUM HARDWARE CONSIDERATI ONS 13.1 MINI MUM CONNECTIONS ................. ...
8XC1 96MC, MD, MH USER’S MANUAL x 15.4 WAIT STATES (READY CONTROL).. . ......... . ...... .......... . ........... . ...... .......... . ......... . .... 15-1 7 15.5 BUS-CONTROL MODES... .......... . ........... . .... ............ . ......... . ........... . .... ............ . ......... 15-21 15.5.1 Standa rd Bus-cont rol Mode ... . . ......... ...
xi CONTENTS APPENDIX A INSTRUCTION SET REFERENCE APPENDIX B SIGNAL DESCRIPTIONS B.1 SIGNAL NAME CHANGES................. . .... . . ............... . .... . . ............... . . ............... . .... . . ...... B - 1 B.2 FUNCTIONAL GROUPINGS OF SIGNAL S ............. . .... . . ............... . . ............... . .... . . ...... B -1 B.3 SIGNAL ...
8XC1 96MC, MD, MH USER’S MANUAL xi i FIGURES Figure Page 2-1 8XC1 96M x Bl ock D i agr am . ..... ... .. .. ..... ... .. ... .. .. ... .. ... .. ... .. ..... .. ... .. ... .. ... .. .. ... .. ... ..... .. .. ... .. 2- 3 2-2 Block Diagram of the Core ............... . ......... ............ ................. . ......... . ........... ............. ...
xiii CONTENTS FIGURES Figure Page 7-5 Serial Port Frames i n Mode 2 and 3 ........ ..... ....... ....... ...... . . . . ..... ........ . ...... ....... ....... ......7-9 7-6 Serial Port Control (SP x _CON) Register .......................... ... . . .. . .... . .. ........................... 7-10 7-7 Serial Port x Baud Rate (SP x _BAUD) Register... ...
8XC1 96MC, MD, MH USER’S MANUAL xi v FIGURES Figure Page 12-3 A/D Result ( AD_RESULT) Register — W r ite For mat ........ .... ... ..... ..... .... ... ..... ..... .... ... 1 2-6 12-4 A/D Time (AD _TIME) Register ....... ................. ...................... ...................... ............... 1 2-7 12-5 A/D Comm and (AD_COMMAND) Register ...
xv CONTENTS FIGURES Figure Page 15-2 1 1 6-bit S ystem with RAM ... .. ..... ..... .. ... ..... .. ..... .. ..... ..... ... ..... .. .. ..... ..... ... .... ... ..... .. ..... .. . 15-31 15-22 S y st e m Bus Timi ng ......... ...................... ...................... . .... . ...... ...................... . .... ...... 15-32 16-1 Un e ra sable ...
8XC1 96MC, MD, MH USER’S MANUAL xvi T ABLES T able Page 1-1 Han dbook s an d Produ ct In f or mation . .............. . ......... .. . .............. .. . ......... . .. .............. . .... 1-6 1-2 Ap p l ication Notes, Application Briefs, and Art icle Reprints . . . .. ... . ............................ ..... 1-6 1-3 MCS ® 96 M icrocon t roll ...
xvii CONTENTS T ABLES T able Page 6-8 C ontrol Register V alues for Each Configuration ..... . . ........ ............ . . .......... . .... . . .......... . 6-11 6-9 Port Co nfiguration Exa m ple . . ...................................... . ................ ... .. ... ......... . ............6-11 6-10 Port Pin States After Reset a nd After Example ...
8XC1 96MC, MD, MH USER’S MANUAL xviii T ABLES T able Page 16 -1 87 C196M x OTPROM Memory Map . . . .. . . ... . . ..... . . ... . . ... . . ... . . .. ... . . ... . . ... . . ..... . . ... . . ... . . ..... . 1 6 -3 16-2 Memory Pr otection for N o r mal Op e r ating Mode ... ................. . ................................. ... 16-4 16-3 Memo ...
1 Guide to This Manu al ...
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1- 1 CH A PT ER 1 GUI DE TO THIS MANUAL This manual descri bes the 8XC1 96MC, 8XC196MD, and 8XC 196M H embedde d microcontr ol- lers. It is intended f or use b y both software and hardware designe rs fa m i l i ar with the princi ples of microcont rollers. This chapte r descri bes wh at yo u’ll find in this m anual, lists ot her documents that ma ...
8XC196MC, MD, MH USER’S MANUAL 1-2 Chapter 9 — W av eform Ge nera tor — describe s the waveform generat or and explains h ow to configure it. For addit ional information and application exampl es , consult AP-483, A pplicat ion Exam p l es Using t he 8XC196MC /MD M i c r ocont r oller (ord e r numbe r 27 2282). Chapter 1 0 — Pulse-wi dth Mo ...
1- 3 G UIDE TO THIS MANUAL Appendix C — Re gisters — provides a compilation of all device spe c i a l- fu nc t ion regis ters (SFRs) arrange d alphabetica l ly b y regist er m n e monic. It a l so includes t ables that list the w in- dowed di r e c t addresses for a l l SFR s in ea ch possible window . Glossary — defines term s with spec ial ...
8XC196MC, MD, MH USER’S MANUAL 1-4 number s Hexadecima l numbe rs are represented by a string of hexadecim a l digits followe d b y the chara c t er H . Decimal and binary numbers are represente d by thei r cus tomary nota t io n s . ( T hat is, 255 is a dec imal number a nd 1 11 1 1111 i s a b i nary number . In some cases, t h e lett er B is ap ...
1-5 G UIDE TO THIS MANUAL uni t s of measu r e The following a bbrevia tio n s are use d to represent units of m easure: A amps , ampe res DC V dire ct curr ent vol ts Kb y t es kil obytes kH z kil ohertz k Ω kilo - oh ms mA millia mps, m illiam peres Mb y t es megabyt es MHz me gahert z ms millis econd s mW mi l l iwat ts ns nano seco nds pF pic ...
8XC196MC, MD, MH USER’S MANUAL 1-6 T able 1- 1. Handb ooks and P roduct Information Titl e and Desc riptio n Orde r Numbe r I nte l Em bedd ed Qu i ck R efe re n ce G u ide 27 24 39 S oluti on s for E m bedd ed Appl icat io ns Guide 24 06 91 D at a on D em a nd fact sheet 24095 2 D at a on D em a nd a n nual subscription (6 issues; Windows* versi ...
1- 7 G UIDE TO THIS MANUAL A P-40 6, MCS ® 96 Ana log Acq uisi tion Prim er ††† 2703 65 A P-445, 8XC19 6K R Perip heral s: A Use r’s Po int o f View † 27 08 73 A P-449, A Compariso n o f the Event Processor Arra y (EP A) and Hig h S peed Inp ut / Output (HSI O) Un i t † 27 09 68 A P-475, Usin g t he 8 XC196NT †† 27 23 15 A P-477, L ...
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1-11 G UIDE TO THIS MANUAL 1.4 .4 World Wide Web W e of fer a v ariety o f information throug h th e W orld W ide W eb (URL:http://www . in tel.com/ ) . Se- lec t “Embedded Design Prod uc ts” from t he Intel home page. 1.5 T ECHNI CAL S UPPO RT In the U.S. a nd Cana da, technic al support representa tives are availabl e to a nswe r your que sti ...
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2 Ar chit ectural Overview ...
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2- 1 CH A PT ER 2 ARCHITECT URAL OVERV IEW The 16-bit 8XC196MC, 8XC196MD, and 8XC1 96MH C HMOS m i c rocontrollers are desi gned to ha n dl e high - s peed calcul a ti o ns and fast in p ut /output (I/O) ope rations. They share a com mon archit ecture and instruc t i on se t with othe r membe r s of the M CS ® 96 m ic rocontroll er fami ly . NOTE ...
8XC196MC, MD, MH USER’S MANUAL 2-2 2.3 F UNCTIONAL O VERVIEW Figure 2 -1 s hows the major blocks within the m i cr o controll er . The c ore of the microcont roller (Figure 2-2 ) c onsists of the cent ral processi ng unit (CPU) an d m emory control l e r . T he CPU con- tains the re gister file and the re gister arithme t i c-logic unit (RALU). A ...
2- 3 ARCHITECTURAL OVERVIEW Figure 2-1. 8XC19 6M x Block Diagram Figure 2- 2 . Block Di agram of the Core A2798-02 Optional ROM Core Clock and Power Mgmt. PTS WG PWM I/O A/D EPA WDT Interrupt Controller FG SIO Note: The frequency generator is unique to the 8XC196MD. The serial I/O port is unique to the 8XC196MH. A2797-01 Register Fi ...
8XC196MC, MD, MH USER’S MANUAL 2-4 2.3.1 CPU Contro l The CPU is cont rolled by the microcode engi ne, which instructs the RALU to pe rform operation s using b yt es , words, or double-words from e i ther the 256-byte l ower register fil e or throu gh a wi n- do w that di rectly access es the up p er regist er fil e . (See Ch apter 4, “ Memo r ...
2- 5 ARCHITECTURAL OVERVIEW The R ALU uses the up per- and lower-word registers toget h e r for the 32-bit instruct ions and a s temporary registers for many instruc t ions. These registers ha ve their own shi f t logic and are used for operatio n s that require logical shift s, incl uding n o rmalize, multiply , and divide operat ions. The six-bit ...
8XC196MC, MD, MH USER’S MANUAL 2-6 2.3.4 Mem ory Interface Unit The R ALU communi cates with a ll mem o ry , except the register fil e and peripheral SFRs , thr ough the memory cont r oller. (It com municates with the upper register file through the memory contr o l- ler except when w indo wing i s used; see Chapte r 4, “Mem ory Partitio n s.? ...
2- 7 ARCHITECTURAL OVERVIEW 2.4 INTERNAL TIMING The c lock ci rcuitry (Figure 2-3) re c e ives an input cloc k signal on XT AL1 provi ded b y an external crystal or oscillator and divi des the fre q ue ncy by two. T h e clock ge n erat ors accept the divided input frequency from the di vide-by-two circui t and produ ce two nonoverlapping internal t ...
8XC196MC, MD, MH USER’S MANUAL 2-8 Figure 2-4. Internal Clock Phases The combined peri od of phase 1 and pha se 2 of the internal CL KOUT s ig n al defines the ba sic t ime unit kn own as a state time or st at e . T abl e 2 -2 lists state time durations at various frequencies. The followi ng formulas calculate the frequenc y of PH1 and PH2, the d ...
2- 9 ARCHITECTURAL OVERVIEW 2.5.1 I/O Ports The 8XC1 96M x m i cr o controll ers have s even I/O p or t s, ports 0–6. The 8XC196MD ha s an ad d i - tional p o rt , port 7. Individual port pi ns are multiple xed to serve as s tandard I/O or to carry speci a l - functio n signals associ ated wit h an on-chip peripheral or an off-chip component. If ...
8XC196MC, MD, MH USER’S MANUAL 2-10 2.5.3 Event Proces sor Arra y (EP A) and T im e r/Co un ters The eve nt processor array (E P A) perfor ms hig h -speed input and output fun ctions associ ated with its tim er/ counte rs. I n t he i nput mode, the EP A m o nitors a n input for signal tra nsit i ons. W he n an event occ urs, the EP A rec ords the ...
2-11 ARCHITECTURAL OVERVIEW 2.5.7 Analog -to-digi tal Co nverter The analog-to-digi tal (A/D) converter converts an analog input volta ge to a digi t al equi valent. Resol u t ion is either 8 or 10 bits; sampl e and convert t imes are pr o gra mmable . Conversions can be performed on the analog grou nd an d ref e rence voltage , and the result s ca ...
8XC196MC, MD, MH USER’S MANUAL 2-12 2.6 .3 P rog ram m i ng the Nonvo lati le M em or y MCS 96 microco ntrollers tha t have internal OTPR OM provide several programming options: • Sl a v e prog ramm ing allows a ma st er EPR OM p ro gra mmer to pr o gra m and verify one or more slave MC S 96 microcont rollers. Programm ing vend ors and Intel di ...
3 Pr ogra mming Considerat ions ...
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3- 1 CH A PT ER 3 PROG RAMMI NG CO NSIDE RATIONS This se c tion p ro vides a n overvie w of the inst ruction set of the MCS ® 96 microcontrollers a n d of- fers guideli n es for program development. For de t ailed informa t ion a bout specific instruct ions, se e Appendix A. 3. 1 OV ERVI EW OF T HE I NS TRUCTION SET The ins truct ion se t supports ...
8XC196MC, MD, MH USER’S MANUAL 3-2 T able 3-2 lists the equivalent operand-type name s for b o th C prog ramm ing an d asse mbly lan- gu age . 3.1.1 BIT Oper ands A BI T i s a single-bit variabl e t hat ca n have t he Boole an values , “ true” and “fal se . ” The a rchit ec- ture requi res that BIT s be ad d resse d as components of BYTEs ...
3- 3 PROGRAMMING CONSIDERATI ON S WORDs must be al igned at even b yte b ou n daries in the a ddress spa ce. The l east-s ignifica nt byte of the WOR D i s in the eve n byte addre ss, and the most -significant byte is in the next hig h er ( odd) address. T he address of a WORD is that of its l e ast-signific ant byte (the even byte address ). WORD ...
8XC196MC, MD, MH USER’S MANUAL 3-4 3.1.7 LONG-IN TE GER Ope rand s A LONG - INT EGER is a 32-bit, signed va r iable that can take on v alues from –2,147,483,648 (– 2 31 ) thro ugh + 2,147,483 ,6 4 7 (+ 2 31 –1). The architecture dire c t ly sup ports LONG-INTEG E R operands only a s the o p erand i n shi ft operat ions, a s the divi dend in ...
3- 5 PROGRAMMING CONSIDERATI ON S 3.2 ADDRES SING MO DE S The inst ruction s et uses four bas ic addre ss i ng modes: • direct • im medi ate • indirect (with or witho u t a utoincrem ent) • indexed (short-, long-, or z e r o-in d ex ed) The sta ck pointer can be used with indire ct addressing to a cce ss the top of t he stack, and it can al ...
8XC196MC, MD, MH USER’S MANUAL 3-6 3.2.1 Direct Ad dressi ng Direct addressing di rectly ac c esse s a loca tion i n the 256-byte lower regi st er fil e, wi thout i nvolv- ing the memory co n t roller . W i ndowing allow s you to re m ap othe r sections of memory into the lower r egist er file for direc t access (see Cha pter 4, “ Me mory Parti ...
3- 7 PROGRAMMING CONSIDERATI ON S ADDB AL,BL,[CX] ; AL ← BL + ME M_BYTE(CX) POP [AX] ; MEM_WORD(AX) ← MEM_WORD(SP) ; SP ← SP + 2 3.2.3.1 Indirect Addr essing with Aut o increment Y ou can choose to automatical ly increment the indirect a d dre ss after the current access. Y ou spec- ify autoincre menting by adding a plus sign (+) to the end o ...
8XC196MC, MD, MH USER’S MANUAL 3-8 The inst r uctio n LD AX,12H[BX] loa ds AX with the contents of the me mory location tha t resides at ad d ress BX+12H. That i s, the instruct ion adds the c onstant 12H (the of fse t) to the conte nts o f BX (the base addre ss), the n loads AX with the contents of the resul tin g address. For e xampl e, i f BX ...
3- 9 PROGRAMMING CONSIDERATI ON S 3.3 ASSEMBLY LANGUAGE ADDRE SSING MODE SELECTIONS The assem bly l anguage simpl if i es the choice of addressin g modes . U se these features where v e r p o s sibl e. 3.3.1 Direct Ad dressi ng The asse mbly language chooses between di rect and zero-inde xed addressing depending on the memory location of t he opera ...
8XC196MC, MD, MH USER’S MANUAL 3-10 T o use t hese re gisters effective ly , you must have some overal l stra teg y fo r all o cat ing the m. The C programming language ad o pt s a simpl e , ef fe c t ive strat egy . It alloc ates t he eight byt es be g i nning at address 1CH as tempora ry sto r age and trea ts the rema ining area in the re g ist ...
3-11 PROGRAMMING CONSIDERATI ON S If a proced u re retu r ns a value to the cal l i ng code (a s oppo sed to modifying m ore global vari ables ) , the result i s re turned in the temporary stora ge space (TMPR EG0, in this exampl e) start ing a t 1CH. TMPRE G 0 is viewed as either an 8-, 16-, or 32bit variabl e, dependi ng on the type of the proce- ...
8XC196MC, MD, MH USER’S MANUAL 3-12 When using t h e watchdog timer (WDT) for software prote c t ion, we r e commend that you res e t t he WDT from only one plac e i n co de, reduci n g the chance of a n unde sire d WDT reset. The sect io n of code that resets the WD T sho uld monitor the other code sections for proper ope rat ion. This c an be d ...
4 Memory Partitions ...
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4- 1 CH A PT ER 4 MEMO RY PART I TIONS This cha pter desc ribes the address space , its major partiti o ns, and a w indowing tec h ni que for ac- cessing the upper re gist er file and perip heral SFRs with regist er-direct inst ructions. 4.1 ME MORY PA RTIT IONS T able 4-1 is a m emo ry ma p of the 8XC196M x devi ces. The rem a i nder of this secti ...
8XC196MC, MD, MH USER’S MANUAL 4-2 4.1 .3 Prog ram Mem o ry Prog ram memory oc cu p ies a memory p artition beg inning at 2080H. (See T able 4-1 for the ending address f o r e ach devic e . ) This entire pa rtitio n is available for storing e x e cutabl e code and dat a . The EA# s ignal control s access t o progr a m memory . Accesses to th is a ...
4- 3 MEMORY PARTITI ONS 4.1.4 S pecial - pur pos e Mem ory Special-purpose memory resides in loca t i ons 2000–2 07FH (T able 4-2). It conta ins several re- served memory locations, th e c hip configuratio n bytes (CCBs), and vectors f o r both peri phera l transaction server (P T S) and standard interrup t s. Ac c esse s to this a dd r e ss rang ...
8XC196MC, MD, MH USER’S MANUAL 4-4 4.1.4.3 Security Key The securi t y key prevents unauthorized programming acce ss t o the nonvo latil e m emory . See Chapter 16, “Programm ing the No nvolatile Memory ,” for deta ils. 4.1.4.4 Chip Configurat ion Bytes (CCBs) The chi p configurati on bytes (CC Bs) speci fy the operati ng environm ent. T h ey ...
4- 5 MEMORY PARTITI ONS 4.1.5.1 Memory-mapped SFRs Locat ions 1FE0–1FFFH cont ain mem ory-m apped SFR s (see T a ble 4-3). Loc ations in this ra nge that are omitt ed f rom t he table are re served. The me mory-mappe d S FRs must be a c cess ed with indirect or indexed addressing modes, and th ey cannot be w in dow ed. I f yo u read a locati on i ...
8XC196MC, MD, MH USER’S MANUAL 4-6 T a b le 4-4. Peripheral SFRs — 8XC196MC Po rt 2 SFRs EP A an d Timer SFRs Address High (Odd ) Byte Low (Even) Byte Address High ( Odd) Byte Low (Even) Byte 1FDE H Reserved Reserve d † 1F 7EH T IMER 2 ( H) TI MER 2 ( L) • • • • • • • • • 1F7CH Reserved T2CONTROL 1FD6 H Reserve d P2_PIN † ...
4- 7 MEMORY PARTITI ONS T a b le 4-5. Peripheral SFRs — 8XC196MD Po rts 2 a nd 7 SFRs E P A and T i mer SFR s Add ress High ( Odd) Byte Low (Even) Byte Address High (O dd) Byte Low (Even) Byte 1FDE H Reserved Reserve d † 1F 7EH T IM ER2 (H) T IMER 2 ( L) 1FDCH Reserved Reser v ed 1F7CH Reserved T2CONTROL 1FDA H Reserved Reserve d † 1F 7AH T I ...
8XC196MC, MD, MH USER’S MANUAL 4-8 T a b le 4-6. Peripheral SFRs — 8XC196MH Port 0 a nd 2 S FRs Po rt 1 SFRs Add ress High ( Odd) Byte Low ( Even) Byte Address High (Odd ) Byte Low (Even) Byte 1FDE H Reserve d Reserve d 1 F9EH P1 _PIN Re served 1FDCH Reser ved Reser ved 1F9CH P1_RE G Re served 1FDA H Reserve d P0_PIN 1F9 AH P1_DI R Re served 1F ...
4- 9 MEMORY PARTITI ONS 4.1.6 Register Fi le The regist er file (Figure 4- 1 ) is divi ded into an uppe r regist er file and a lowe r re gister fi l e . The upper regi ster file consi sts of genera l-purp ose re gister RAM . The lowe r registe r fi l e conta ins gen- eral-purpose register RA M a lo n g with the s t ack poi n ter (SP) and the CPU sp ...
8XC196MC, MD, MH USER’S MANUAL 4-10 4.1.6.1 Gene ral-pur pose Register RAM The lowe r registe r f ile c ontains ge neral -purpose registe r RAM. The s tack pointer l ocations can also be u sed as general-purpo se regi s ter RAM when stack operations are not b eing performed. The RA LU ca n access thi s mem ory direc tly , using regist er-direct a ...
4-11 MEMORY PARTITI ONS Y our prog ram must l oad a word-al igned (even) address into t he st a ck pointer . Select an address that is t wo byte s grea te r tha n the desi red s tarti ng ad d ress be cause the CP U aut omat i ca lly dec re- ments the s t a ck pointer bef o re it pushes the first byte of th e re t urn address onto the stac k. Remem- ...
8XC196MC, MD, MH USER’S MANUAL 4-12 4.2 W I NDOWING W indowing expands the a mount of m emory that is accessibl e with register-direct a ddressing. Regis t e r -di rect ad dressi ng can a c cess the lower regist er file with short, f a st-exec uting instr u c- tions. W i th wi nd owing, re gist e r -di rec t addressi ng c an a lso acce ss the u p ...
4-13 MEMORY PARTITI ONS 4.2.1 Selec ting a Wind ow The window se lection regist er (F i gure 4-3) sel e c ts a win d ow to be m apped into the t op of the low- er re giste r file. T able 4-9 provides a q u ick refe rence of WSR values for windowing the peripheral SFRs. T able 4-10 on page 4-14 lists the WSR values for windowing t he upper register ...
8XC196MC, MD, MH USER’S MANUAL 4-14 4.2.2 Add ressing a L ocation Thro ugh a Wi ndow After you have selected the desired window , you need to k now t he windowed direct address of the memory l ocation (the address in t he lowe r register file). Ca l c ulate the windowed di rect ad- dress as foll ow s: 1. Subtract the base address of the area to b ...
4-15 MEMORY PARTITI ONS T able 4-1 1. Windows Bas e Add re s s WS R V alu e fo r 32-by te Window ( 00E0– 00FF H) WSR Va l ue fo r 64-by te Window (00 C0–00 FFH ) WSR Value fo r 128 -by te Win dow (0 080– 00FF H) P erip heral SFRs 1FE0 H 7 FH (Note ) 3FH ( Note ) 1FH (Not e) 1F C0H 7 EH 1FA0H 7D H 3E H 1F 80H 7 CH 1F 60H 7 BH 3DH 1EH 1F 40H 7 ...
8XC196MC, MD, MH USER’S MANUAL 4-16 Ap p e ndix C incl udes a t able of t he windowabl e SFRs wi th the W SR values and direct a ddresse s for eac h window size. T h e foll owing exampl es ex p l ain how to de t e rmine the WSR value a nd di- rect addre ss for an y win do w able location. An a dditional exam ple shows how to set up a window by us ...
4-17 MEMORY PARTITI ONS 4.2.2.5 Using t h e Linker Locator t o Set Up a Win d o w In thi s exampl e, the l inker loca tor is u s ed to se t up a wi ndow . The linker l ocator l ocate s t he win- dow in t h e upper register file and dete r mines the value to loa d in t h e WSR for access to that win- dow . (Please consul t the man ual provided with ...
8XC196MC, MD, MH USER’S MANUAL 4-18 ldb wsr, #?WSR ;Prolog code for wsr add var1, var2, v ar3 ; ; ; ldb wsr, [sp] ;Epilog code for wsr add sp, #2 ;Epilog code for wsr ret end ********************** ******** The followi ng is an example o f a l inker invocati o n to link and loc a t e the modu les and to d e ter- mine the pr oper windowi n g. RL19 ...
4-19 MEMORY PARTITI ONS The C compi l e r can also take a d va n ta g e of this fea ture if the “windows” sw i t ch i s enable d. For details, see th e MC S 96 microc o ntr o ller archi t ecture software products in the Dev elopme nt T o ols Han dbook . 4.2.3 Windo wi ng and Add ressi ng Mod es Once win d owing is enabled, the windowed loc a t ...
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5 Standard and P TS Interrupts ...
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5- 1 CH A PT ER 5 STANDARD AND PTS INTE RRUPTS This c h a pter des cr i bes the int errupt control c i rcuitry , priority sc h e me, and t i m ing for standa r d and peripheral tr a nsaction se rver (P TS) inte rrup ts. I t disc usses t he three special i nterr u pt s and t h e sev- en P T S modes, four of which are us ed with the EP A to p rovide ...
8XC196MC, MD, MH USER’S MANUAL 5-2 Figure 5-1. Flow Diagram for PTS and Stan d ar d Interrupts No No PTS Enabled? PTSSEL. x Bit = 1? Yes Yes No Interrupt Pending or PTSSRV Bit Set NMI Pending ? Interrupts Enabled ? Yes No Return INT _MASK. x = 1? No Return Yes Return Reset INT_PEND. x Bit Reset PTSSRV. x Bit Priorit ...
5- 3 STANDARD AND PTS INTERRUPTS Figure 5-1 illust rates the interrupt pr o c essing flow . In this fl ow diagram, “INT_M ASK” rep r e - sents both the INT _MASK a nd INT_MA SK1 regi st e rs, and “INT_PEND” repre sents both the INT_PEND a nd INT_PEND1 regi st ers. 5.2 INTE RRUPT SIGNALS AND REG I ST ERS T abl e 5-1 desc ribes the external i ...
8XC196MC, MD, MH USER’S MANUAL 5-4 5.3 INTE RRUPT SOURCES AND PRI ORITIE S T able 5-3 lists the interrupts sources, their default priorit ies (30 is highest and 0 is lowe st), an d their vec tor addresses . The unimpl emente d opco d e and software trap i nterrupts a re not priori- tized; they go dire ctly to the i n te r rupt c ontroller for ser ...
5- 5 STANDARD AND PTS INTERRUPTS T able 5-3. Interrupt Sources, V ectors, and P riorities Interru pt So urce Mne monic Inte rrupt Con troller Se rvice PTS Se rvice Name Ve c t o r Priority Name Ve c t o r Priority No n maska ble I nterru pt NM I INT15 203 EH 30 — — — E XTINT Pi n EX TINT INT1 4 203 CH 14 PTS1 4 2 0 5 CH 29 WF Ge n (M C) WF Ge ...
8XC196MC, MD, MH USER’S MANUAL 5-6 5.3.1 Speci al Interr upts This micr ocontroller has three specia l in t errupt sourc es that a re a lwa ys enabled: unimpl em ente d opco d e, software tra p, and NMI. These interrupts are not affecte d by the E I (enable inte rrupts ) and DI (disable in terrupts) i nstructions , and t h ey ca nnot be maske d. ...
5- 7 STANDARD AND PTS INTERRUPTS When the leve l-s ensi tive eve nt is selecte d, t he externa l interrupt si gnal must rem ain asse rte d for at l east 24 T XTAL 1 (24 /F XT AL 1 ) to be recogniz ed a s a valid i nte rrupt. When t he s ignal i s a sse rte d, the l evel sam pler sa mple s the level of t he signa l thre e time s during a 24 T XTA L ...
8XC196MC, MD, MH USER’S MANUAL 5-8 The int errup t ser v ic e routi ne should read the PI_PEND (Figure 5 -12 on page 5-23) register to d e- termi n e the so u rc e o f the interrupt. Before exec utin g the ret urn ins truct ion, the inte rrupt se rvice routine should c heck to see if any of t he ot her inter rupt source s are pen ding. Genera lly ...
5- 9 STANDARD AND PTS INTERRUPTS 5.3.4 End-o f-PT S Interrupts When the P TSCOUNT regis ter decrem ents to zero at th e end of a s i ngle transfer , block transfer , A/D scan , or s erial I/O routi ne, hardware clea rs t he corresponding bi t in the P T SSEL regist er , (Figure 5- 6 on page 5 - 1 4) which disable s P TS servic e for t hat inte rrup ...
8XC196MC, MD, MH USER’S MANUAL 5-10 Each P TS cycle wi thin a P T S rout ine can not be inte rrupted. A P TS cycle i s the entire P T S re- spon s e to a singl e interrupt request . In block transfer mode, a P TS c y c l e c onsists of t he t ransfer of an ent i re block of byt es or words. This m e ans a w o rst-case latenc y of 500 st a tes if ...
5-11 STANDARD AND PTS INTERRUPTS Figure 5 -4. St andard Int err upt Response Time 5.4.2.2 PTS Int err upt Latency The maxim um delay for a P TS interrupt is 43 state t i mes (4 + 39) as shown in Figure 5-5. This delay t ime doe s not include the a d de d delay i f a protected i nstructio n is bein g execut ed or if a P TS request is alrea dy in pro ...
8XC196MC, MD, MH USER’S MANUAL 5-12 5.5 PROG RAM MING THE I NTERRUP TS The P TS s e l ect re g i ster (P T SSEL) sel ects eithe r P TS s ervice or a s tan d ar d software i n terrupt s er- vice routine fo r e a ch of t he maskabl e interrupt reque sts (s ee F igure 5 -6). The bi ts in the inte rrupt mask regi st ers, INT_MASK a nd INT_MASK1, enab ...
5-13 STANDARD AND PTS INTERRUPTS When you assign a n interrup t to the P TS, you must set up a P TS control block (P TSCB ) fo r e a ch interrupt source (see “ I ni t i a l izing the P TS Control B l ocks” o n pa ge 5-24) and us e t he EP TS i n- structi on to gl obally e nable the P T S. Whe n you assign an interrupt to a standard softwa r e s ...
8XC196MC, MD, MH USER’S MANUAL 5-14 P TSSEL Ad dress : Re s et S ta te: 00 04H 00 0 0 H The PTS se l ect (P T SSEL) re gist er se lects either a PTS m icroco d e ro utine o r a stan dard inte rrupt se rvice ro utine for e ach in terrup t req uest. Setti n g a bit sel ects a PT S micro code ro utin e; clea ring a bit se lects a sta ndard inte rrup ...
5-15 STANDARD AND PTS INTERRUPTS INT _ M ASK A d d ress: Reset Sta te: 00 08 H 00 H The interru p t mask (INT_MASK ) registe r e n ables o r disab les (m a s k s) individ ual i n terru pt requ ests. (Th e EI and DI instr uctio ns ena b le a n d disa ble servicin g of a ll maska ble in terrup ts.) INT_M ASK is the low byte o f t he processor status ...
8XC196MC, MD, MH USER’S MANUAL 5-16 INT_M ASK1 Address: Reset Sta te: 00 13 H 00 H The in terrup t mas k 1 (INT_M ASK1) re giste r enab les or d isable s (m asks) i n d i vidual i nterru pt re q uests. (Th e EI a nd DI instructi on s enab le and disabl e ser vicing o f a ll mas kable interr upt s.) INT_MASK 1 can be re a d from or writ t en t o a ...
5-17 STANDARD AND PTS INTERRUPTS PI_ MAS K Add ress : Rese t State: 1FBCH AAH The p er iphera l interr upt m ask (PI_M ASK) reg ister e n ables o r disab les ( m as k s) i nterru pt req u e sts as socia ted wi th the peri ph era l interru p t (PI), the seria l port int erru pt (SPI), and the overf low/un derfl ow time r inte rrup t (OV R T M). 7 0 ...
8XC196MC, MD, MH USER’S MANUAL 5-18 5.5.1 Modifyin g Interru pt P riori ties Y our software can m odify the de fault priorit i e s of ma skable inte rrupts by controllin g the inter ru pt mask registers (INT_M ASK and INT_MASK1). Fo r e xampl e, you can specify whi ch in terrupts, if any , can interrupt an inter ru pt s ervice r ou t in e. The fo ...
5-19 STANDARD AND PTS INTERRUPTS Note that loc atio n 2 0 02H i n the i nte rrupt ve ct o r tabl e must be l oaded wi th the value of the label AD_DONE_ISR before the i nterrupt request occ u rs a nd that th e A/D conversio n c om plete in ter- rupt m ust be enabl ed for this ro uti n e to e xecut e . This routine, like all int errupt servi ce rout ...
8XC196MC, MD, MH USER’S MANUAL 5-20 5.5.2 Determi n i ng the S ource of an I nterrupt When har d wa re detects an interrupt, i t s ets the corres p onding bi t in th e INT_PE ND or INT_PEN D1 register (Figures 5- 10 a nd 5-1 1 ). It s ets the bit even if the individua l interrupt i s disable d (masked). Ha rdware c lears the pending b it when the ...
5-21 STANDARD AND PTS INTERRUPTS INT _PE ND Address: Reset Sta te: 00 09 H 00 H When h ar d ware det ects an i nt e rrupt req uest, i t sets the correspo nding b it in the inter rupt pen d i ng (INT _PEND or IN T_PEND1) re giste rs . When the vector is t aken, th e h ardwar e cle ars the pen d i n g bit. Softwa re can gene rat e an interr up t by s ...
8XC196MC, MD, MH USER’S MANUAL 5-22 INT_PE ND1 Address: Reset Sta te: 00 12 H 00 H When hardwar e det ects a pendin g interru pt, i t set s the corr espo n ding b it in the i nterr u pt pen ding (INT _PEND or IN T_PEND1) re giste rs . When the vector is t aken, th e h ardwar e cle ars the pen d i n g bit. Softwa re can gene rat e an interr up t b ...
5-23 STANDARD AND PTS INTERRUPTS PI_PEND Add ress : Rese t State: 1FBEH AAH When hard ware dete cts a p end ing p eriph eral or timer inte rrupt, it se ts th e correspo ndin g bi t in t he interr upt pen d i n g (INT _PEND o r INT_PE ND1) r e g ister s a nd t h e p e riphe ral inte rrupt pe n d i n g (PI_ PEND) registe r . Whe n the vecto r is take ...
8XC196MC, MD, MH USER’S MANUAL 5-24 5.6 INITIALIZING THE P TS CONTRO L BLOCKS Each P T S in terrupt requires a block of data, in register RAM, called t h e P TS control block (P TS CB). The P TSCB i dentifi es whic h P T S microcode routine wi ll be i nvoked and sets up the specifi c parameters for t he r outine. Y ou must s et up the P T SC B fo ...
5-25 STANDARD AND PTS INTERRUPTS The address of the fi rst (lowest ) P TSC B byte i s s to r ed i n the P T S vect o r t a ble in s pecial -pur pose memory ( s ee “Spe c ial- p urpose Me mory” on page 4-3). Figure 5 -13 shows the P TSC B fo r e ach P T S mode. U n used P T SC B byte s can be use d a s extra RAM. NOTE The P TSC B mus t be l oca ...
8XC196MC, MD, MH USER’S MANUAL 5-26 PTSSRV Ad dress : Re s et S ta te: 00 06H 00 0 0 H The PTS servi ce (PTS SR V) re gist er is used b y the hard ware to ind icate th a t the final PTS inte rrupt h as bee n s erviced by the PTS routin e. When PTSCOUNT re aches ze ro , h ar d ware clears th e corre - sp ondi ng P T SSEL bit and sets the PTSSRV bi ...
5-27 STANDARD AND PTS INTERRUPTS 5.6.2 Selec ting th e PT S Mod e The second b y te of e ach P T SCB is a lways a n 8-bit value called P T SCON. Bi ts 5–7 select the P T S mode (Figure 5- 1 5). The funct ion of bits 0– 4 differ for e a ch P TS mode. Refe r to the sec t ions that describe each mode i n detail to see the f u nc tion of these bits ...
8XC196MC, MD, MH USER’S MANUAL 5-28 PTS Sin gle T ra nsfer Mo de Cont rol Bloc k In single transfe r m ode , t h e P TS contro l block contain s a so urce and desti nati on addres s (P T SSRC and PTS DST), a control r egister (PTSCON), a n d a tr ansfe r count (P T SCOUNT). 7 0 Unu sed 0 0 0 0 0 0 0 0 7 0 Unu sed 0 0 0 0 0 0 0 0 15 8 PTSDST (H) P ...
5-29 STANDARD AND PTS INTERRUPTS The P TSCB in T a b l e 5-5 define s nine P TS cycles. E a ch c yc le m o ves a sin g le word from loca ti on 20H to an e x terna l memory location. T he P TS transfers t he first word to l ocatio n 6000H. T hen it increme nts and upd a t es t he dest inat ion a ddress and decreme nts the P TSC OUNT regist er; i t d ...
8XC196MC, MD, MH USER’S MANUAL 5-30 5.6.4 Block T r ansfer Mod e In block transfer mode, an interrup t causes t he P TS to move a block of bytes o r words from one memory loca tion to anothe r . S ee AP-483, Ap p lication Exampl es Using the 8XC196M C/M D Mi- cr ocontr ol ler , for a pplication examples with code. F igure 5- 17 shows the P T S co ...
5-31 STANDARD AND PTS INTERRUPTS PTS Bloc k T ran sfer Mod e Contro l Block In b l ock transfe r mode, t h e PTS c o nt rol block contains a block size (P T SBL OC K), a source and destinati on a ddress (P T SSRC and PTSDST), a c o nt rol r egiste r (PTSCON), and a tran sfer count (P TSCOUNT). 7 0 Unu sed 0 0 0 0 0 0 0 0 7 0 PTSBL OCK PTS Block Si ...
8XC196MC, MD, MH USER’S MANUAL 5-32 5.6.5 A/D Scan Mod e In the A/ D scan mode, the P TS cause s the A/D converter t o perform mul t iple conversions on one or more c han n els and th en s tores the results in a t able in memory . Figure 5- 19 s ho ws the P TS con- trol bloc k f or A/D sc an mo de. Reg ister Lo cation Fun ction PTSCON PTSCB + 1 P ...
5-33 STANDARD AND PTS INTERRUPTS PT S A/D S can Mo de Control Bloc k In A/D scan mode, the P TS causes the A/D convert er to perform mult iple conve r sions on o ne or m ore cha nnels and then store s the results. The control bloc k contains pointe rs to both the AD_RESUL T regi ster (PTSPTR1) and a tabl e of A/D co nversio n com mands and resu lts ...
8XC196MC, MD, MH USER’S MANUAL 5-34 T o use the A/ D s can mo d e, you must first se t u p a command/da t a table in memory (T able 5-7). The co mm and/da ta table contains A/ D com mands t hat are inte rle ave d wit h blank me mory loca - tions. The P TS st o re s the conversio n r e sults in the se blank locations. Only the amo u nt of availabl ...
5-35 STANDARD AND PTS INTERRUPTS 5.6.5.1 A/D Scan Mode Cyc les Software must start the firs t A/D conversion. Af te r t he A/D conversi o n comple t e int errupt ini- tiates t he P TS r outine , the foll ow ing actions occ ur . 1. The P T S reads the first c om ma n d (from address XXXX), s tores it i n a t e mporary loca tio n, and increme nts the ...
8XC196MC, MD, MH USER’S MANUAL 5-36 version. Step 4 updates P TS P TR1 (P T SP TR1 now points t o 3004H) and step 5 decrement s P T SCO UNT to 3. The next cycle begins by st oring the channe l 5 command in the temporary lo- cation. During the last cycle (P T SCOUNT = 1), the dumm y command i s loaded into the AD_COM MAND regis ter an d no convers ...
5-37 STANDARD AND PTS INTERRUPTS 5.6.5.3 A/D Scan Mode Example 2 T abl e 5-1 1 sets up a s eries of te n P TS cycles , each of which reads a sin g le A/D c hannel and stores the res ul t in a s ingle location (3002H). The UPDT bit (P TSCON.3) i s cleared so that o r i ginal con - tents o f P T S P T R1 are restored afte r the cycl e. The comma nd/d ...
8XC196MC, MD, MH USER’S MANUAL 5-38 trans mi tted or rec eived i ncl udin g the parit y and st op bi ts in t he a synchronous modes. The seri al I/O modes require two P TS control bloc ks t o c onfigure all options (see Figures 5-19 and 5-20). These blocks need not be contig u ous, but t hey mus t e ach be locate d in regist er R AM o n a quad- w ...
5-39 STANDARD AND PTS INTERRUPTS Reg ister Lo c a tion Func tio n BAUD PTSC B1 + 4 Bau d V alue This registe r conta in s t he 16-bit valu e that the PTS uses to gene rate t h e de sired b aud rat e. Use t h e fo ll owin g for m ula to calcul ate t h e valu e to l oad in to th e BAUD register . whe re: B aud _va lu e is a 16- b it inte ger th at is ...
8XC196MC, MD, MH USER’S MANUAL 5-40 Reg ister Lo c a tion Func tio n PTSCOUNT PTSCB1 + 0 Con secuti ve PTS Cycles Defi ne s the n umb er of bi t s to be tran smit ted or rece ived , includ ing pari ty and stop b its, bu t not the start b it. Fo r asynchro nous m ode s, progr am a nu mber th at is b etwee n 1–16 . For synchrono us m o des, p rog ...
5-41 STANDARD AND PTS INTERRUPTS PT S Seria l I/O M ode Co ntrol Bloc k 2 (8 XC196 MC, M D) The P TS con trol blo ck 2 con tains p ointers to bot h the po rt reg ister (PORTREG) an d the da ta registe r (DA T A). It a l so conta ins a 1 6-bit valu e that is used to calcula te the sam ple tim e f or as ynchro nous re c eptio ns when m ajori ty s a m ...
8XC196MC, MD, MH USER’S MANUAL 5-42 Re gister Lo catio n F unc tion DA T A PTS CB2 + 4 Data Regi st er This 16 -bi t regi ster hold s the d ata to b e tran smi tte d or the data that has been rece ived . Durin g tran smi t mode , the least- signifi cant bit (b it 0) is tran smitted f i rst. Data shi fts to t he rig ht with e ach succe ssive tra n ...
5-43 STANDARD AND PTS INTERRUPTS 5.6.6.1 Synchro nous SI O T ransmi t Mode Example In synchr o nous se rial I/O (SSIO) transm it mode , a n EP A channel controls the transmi ss ion baud rate by ge nerating o r capturing a seria l clock signal (SCK). T o generat e t he SCK si gnal, co n fig u re the EP A channel in c ompare mode and set the output - ...
8XC196MC, MD, MH USER’S MANUAL 5-44 If the SC K signal is generat ed by the EP A channel, t h e first P TS c ycle must be start ed manua l l y . • Init ialize the TX D port pin an d t he SCK signal to the syste m-required logic l e vel bef o re starting a transmi ssion. • Ad d the cont ents of the t i mer regi s t er to the B aud_v a lu e (F ...
5-45 STANDARD AND PTS INTERRUPTS 7. Enable EP A0 inte r rupt. — Set INT_M ASK.2. 8. Load t h e number of bytes to transm i t into t he user_defi n ed t ransmit count register (T_COUNT) and clear the user -defi ned transfe r-done fl a g (TXDDONE). — LD T _COUNT , #1 6 — CLRB TXDD ONE 9. Select P T S servic e for EP A 0. — Set P TSSE L.2. 10. ...
8XC196MC, MD, MH USER’S MANUAL 5-46 time into the event-ti me regi ster . I f t his toggle occu r s , the clock pol arity will cha nge because of t h e o d d number of toggle s and erroneous data may be output. The inter ru pt service routine shoul d a l so load the next data byte, reload the P T SC OUNT and P T SC ON 1 registers, s elect P TS se ...
5-47 STANDARD AND PTS INTERRUPTS 5.6.6.2 Synchro nous SIO Receive M o de Example In sy nchr o nous se rial I/O (SSIO) receive m ode, an EP A c hannel cont rols the re ception baud ra t e by generat ing or capt u rin g a seria l clock si g nal (SC K). T o genera t e the SC K signal , config u re the EP A channe l in compare mode and set the o u tput ...
8XC196MC, MD, MH USER’S MANUAL 5-48 The f ollowin g exam ple uses E P A0 to capture the SCK signa l and P2.3 to rec eive the da t a (RXD ) . It s e ts up a synchron ous seri a l I/O P TS routi n e t hat re ceive s 16 bytes wit h eight data bits. Bec ause this exampl e use s an exte r nal serial clock i nput, the TIM E R 1 and BAU D regis ters are ...
5-49 STANDARD AND PTS INTERRUPTS 8. Select P T S servic e for EP A 0. — Set P TSSE L.2. 9. Set- u p EP A0 t o c apture on both risi ng and fal l i ng edges . — Set EP A0 _CON bits 4 and 5 (Figure 1 1 - 10 on page 1 1-1 9 ). 10. Enable the P T S and conventional interrup t s. — Use the EI inst ruction to ena ble all standard inte rrup ts and t ...
8XC196MC, MD, MH USER’S MANUAL 5-50 Figure 5-24. Synchronous SIO Receive Mode — End-of-PTS I nterr upt R outine Fl owch art 5.6.6.3 Asynchronous SIO T ransmi t Mode E x a m ple In asynchronou s serial I/ O (ASIO) transmit mode, an EP A chan n e l controls the t ransmission baud rate by generating an interrupt whenever a mat ch occurs betwee n t ...
5-51 STANDARD AND PTS INTERRUPTS Fig u r e 5-25. Asynchronous SIO T ransmit T iming The first P TS cycl e must be start ed manual ly b y g enera ting a start bit a n d then set ting u p the t im- ing for the first E P A interrupt. • Initialize t he T XD port pin to one before st arti n g a tra nsmi ssi on. • W ri te a zero to the TXD port pin t ...
8XC196MC, MD, MH USER’S MANUAL 5-52 5. Initiali ze and enable the timer; s ele ct up c o unting, in t ernal clock, and prescale r disable d. — Set T1CON TROL bits 6 and 7 (Figu re 1 1-8 on pa ge 1 1-1 6 ) . 6. In iti aliz e the P TS CB as sho wn i n T ab le 5-15 . 7. Enable EP A0 inte r rupt. — Set INT_M ASK.2. 8. Load t h e number of bytes t ...
5-53 STANDARD AND PTS INTERRUPTS 14. The transmi ssio n will be gin. Data is shifted out with the least -significant (rightm ost) bit first. Each t im e a timer matc h occurs betwe en EP A0_TIM E and TIMER 1, the EP A0 channel generates an interrupt and the P TS outp u ts the next bit of da ta on the p i n configured as T XD. W hen P TSC OUNT decre ...
8XC196MC, MD, MH USER’S MANUAL 5-54 Figure 5-26. Asynchronous SIO T ransmi t Mode — En d-of-PTS Inter rupt Routine Flowchart A3276-01 End-Of-PTS Interrupt Save Critical Data Set-up next data transfer - Load next data byte into DATA register - Reload PTSCOUNT and PTSCON1 registers - Create start bit (clear TXD) - Select PTS servic ...
5-55 STANDARD AND PTS INTERRUPTS 5.6.6.4 Asynchronous SIO Receive Mode Example In a s ynchronous serial I/O (ASIO) rec eive mode, an EP A chan nel i s set up t o capt ure the fall in g edge w h e n the dat a start bit to g gl es on a port pin that is configure d to function a s the Rec e i ve Data signal (RX D). When t he capture oc curs, the EP A ...
8XC196MC, MD, MH USER’S MANUAL 5-56 2. Set-u p the s tac k pointer . 3. Reset all interrupt mask regi sters. — Clear INT_M ASK, INT_M ASK1a nd PI_MAS K. 4. I nitia lize P2. 0 to func ti o n as the RXD signal . — Set P2_DIR.0 (selects input) . — Clear P2_MODE .0 (sel ects LSIO funct io n). — Set P2_REG. 0 (init ializes RXD input to “1” ...
5-57 STANDARD AND PTS INTERRUPTS 1 1. Enable t he P TS and conventional interrup ts. — Use the EI inst ruction to ena ble all standard inte rrup ts and the E P T S instr u ction to enabl e the P T S. 12. T o ggle the RXD input to st art the reception. T he EP A wi l l generate a conventional interrupt. This interrup t se rv ice r ou tine shou ld ...
8XC196MC, MD, MH USER’S MANUAL 5-58 Figure 5-28. Asynchronous SIO Receive Mode — End-of-PTS Int err up t Routine Flowchart A3277-01 End-Of-PTS Interrupt Save Critical Data Set-up next data reception - Clear DATA register - Reload PTSCOUNT and PTSCON1 registers - Select PTS service for EPA channel - Re-initialize the EPA channel ? ...
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6- 1 CH A PT ER 6 I/O P ORTS I/O ports pr o vi de a mechanism to transfer in f orma tion betwee n the device and the surrounding system c ircuitry . T hey c an read system stat u s, monit or syste m operation, output devi ce status, configure system opti ons, g enera t e contr o l signals, prov ide s eria l comm u nica t i on, and so o n . Their us ...
8XC196MC, MD, MH USER’S MANUAL 6-2 6.2 INP UT-ONL Y PO RTS 1 (MC, MD O NLY) AND 0 Port 0 is an eight-bit , hi gh-impe dance, input -only port that prov i des analo g an d digit a l inputs . The input-only pins can be read as digita l inputs ; most of them are also inputs to t he A/D converter . The in p ut- only ports differ from the other st and ...
6- 3 I/O PORTS 6.2.1 Sta ndard Inpu t -only Po rt Ope ratio n Figure 6-1 is a schem atic of an input-only port pin. Tr a nsi stors Q1 and Q2 ser ve as electrost atic discharge (ESD) p r ot ection devic es ; they are re ferenced t o V REF an d ANGND. T ransi stor Q3 is an additio n a l ESD prot e c t io n de vice; it is reference d to V SS (digi t a ...
8XC196MC, MD, MH USER’S MANUAL 6-4 6.2.2 Sta ndard Inpu t -only Po rt Cons iderati ons Port 0 and 1 pins a r e uni que in that t hey may indi v i dually be u s ed as digital inputs and analog inputs at the sam e time. However , reading the port i nduces n oise into the A/ D converte r , dec re as- ing the accurac y of any conversion i n progr e s ...
6- 5 I/O PORTS T abl e 6-4. Bidirect ional Port Pins Port Pin Sp e c ial-fun cti on S ignal(s ) S pecial-fu nction Sig nal T yp e As socia ted P eriphe ral P1.0 (M H) TXD 0 O SIO P1.1 (M H) RXD0 I/O SIO P1.2 (M H) TXD 1 O SIO P1.3 (M H) RXD1 I/O SIO P2 .0 E P A0 I /O EP A P2 .1 E P A1 (MC , MD) I/ O EP A SCL K 0# (MH ) BCL K0 (M H) I/O I SIO SIO P2 ...
8XC196MC, MD, MH USER’S MANUAL 6-6 T abl e 6 -5 l i sts the regis ters associ a t ed with the bidirectional ports. E a ch port has three control reg- ist ers (P x _MODE, P x _DIR , and P x _REG); t h ey can be bo th read and writte n. The P x _P IN regis- ter is a s ta tus register that retu r ns t he logic level present o n t he pins; it can onl ...
6- 7 I/O PORTS In I/O m ode (selec t e d by clearing P x _ MODE . y) , P x _R EG and P x _DIR are inp ut to the multiplex- ers. The se signal s combine to d rive the ga tes of Q1 an d Q2 so tha t the o utput is high, low , or high impedanc e. T able 6-6 is a l ogic table for I/O operation of these ports. In special -function mo d e (selec t ed by s ...
8XC196MC, MD, MH USER’S MANUAL 6-8 Figure 6 -2. Bidirectional Port Structur e Vcc Q2 Q1 Px_REG Px_DIR Sample Latch PH1 Clock Internal Bus SFDATA SFDIR Px_MODE Px_PIN D Q 0 1 0 1 Vcc Vcc Q R S Any Write to Px_MODE Weak Pullup Medium Pullup RESET# RESET# Q3 Q4 Vss Read Port LE 300ns Delay I/O Pin A0238-04 150 Ω to 200 Ω R1 ...
6- 9 I/O PORTS 6.3.2 Bid ir ectio nal Port Pi n Con figurati ons Each bidi rec tio nal port pin can be indi vidual ly config ured to operate ei ther a s an I/O pin or as a pin for a spec ia l-function signal . In t he spec ial-funct ion configurat ion, the signal i s controlled by an on -chip peri pheral or an of f-chip c omponent . In e it h e r c ...
8XC196MC, MD, MH USER’S MANUAL 6-10 T o prevent the CMOS inputs f r om floatin g , t he bidirectional port pins are we akly p u ll ed high dur- ing and after reset, until yo u r software writ es to P x _M ODE. The defa u lt va lues of the control reg - is te rs after reset configure the pins as high-impedance inputs with weak pull-ups. T o ensure ...
6-11 I/O PORTS 6.3.3 Bid ir ectio nal Port Pi n Con figurati on Exam p le Assume t hat you wish t o configure the pins of a bidi rectional port as sh o w n in T abl e 6 -9. T o do so, you c ould use the followi n g exampl e code segme nt. T a ble 6- 10 sho ws the st ate of each pin after res et and after exec uti on of each line of t he exa mple co ...
8XC196MC, MD, MH USER’S MANUAL 6-12 6.3.4 Bidir ectio nal Po rt Co ns id erati ons This sect ion outlines spec ia l considera tions for using the pins of the se ports. Port 1 (8XC196M H) After reset, your s o ftware must co nf igure the devic e t o match the external system. Thi s is accomplishe d by writing appropriate config- uration data into ...
6-13 I/O PORTS P5.0/ ALE If EA# is hi g h on rese t (interna l a ccess), the pi n is we akly held high until your software writes to P5_MODE. If EA# is low on rese t (external acc ess), eithe r ALE or ADV # is activat ed as a system control pin, depe n di ng on the ALE bi t of CCR 0. In e ither case, the pin become s a true compl ementa ry output. ...
8XC196MC, MD, MH USER’S MANUAL 6-14 6.4 BIDI RECT IO NAL PORT S 3 AND 4 (ADDRE S S/DAT A BUS) Ports 3 and 4 are e ight-bit, bi directional , me mory- m apped I/O ports. They ca n be addres sed on ly with indirect or in d e xed addressing and can n ot b e windowed. P o rt s 3 and 4 provide the mul t i- plexed ad dr e ss / data bus. In programming ...
6-15 I/O PORTS 6.4.1 Bidir ectio nal Ports 3 and 4 (Address/ Data Bus) Op eratio n Figure 6-3 shows the ports 3 a nd 4 logic. During reset, t h e active -low leve l of R ESET# turns of f Q1 and Q2 and turns on tra n s istor Q 3 , w h i ch weakl y pulls the pin high. (Q1 ca n s ource at leas t – 3 mA a t V CC – 0.7 volts; Q2 can sink at least 3 ...
8XC196MC, MD, MH USER’S MANUAL 6-16 6.4.2 Usi ng Ports 3 and 4 as I/O T o use a port pin as a n output, wri t e the out put data t o t he cor r e spond ing P x_ REG bit. When the device require s acc ess to ex ternal memory , it t akes cont ro l of t he port a n d d rives the addres s/data bit o n to the pin. The ad dress/dat a bit repla ces y o ...
6-17 I/O PORTS 6.5.1 Output-o nly Por t Operati on Figure 6-4 shows a simplified circuit schema tic for port 6. Port 6 has a single co nf ig uration an d control regi ster , WG_OUT PUT . T rans i stor Q1 c an source at least –200 µA at V CC –0.3 volts. For pins P6.0–P6.5, transist o r Q2 can sink at least 10 mA at 0.45 v ol ts. For pi ns P6. ...
8XC196MC, MD, MH USER’S MANUAL 6-18 Figure 6-4. Output-only Port WG_OUTPUT (Po rt 6) Address: Reset Sta te: 1FC0 H 000 0 H The po rt 6 o utput con figura t ion (WG_OUT PUT) reg ister co ntro ls po rt 6 f u n ctio ns. If y ou are usin g port 6 for genera l-p urp ose outpu ts, write C0H (for active-h igh outpu ts) or 00H (for active -lo w output s) ...
6-19 I/O PORTS 7 :0 D7: 0 Dat a In gener al -pu rpose o utpu t m ode, t h ese bits hold the values to be drive n out on th e pins. Write t he d esired values t o the se bits (bit s 7:0 co rrespond to p i ns P6.7:0). WG_ OUTPUT (Po rt 6) (Con tinued ) Address: Reset Sta te: 1FC0 H 000 0 H The po rt 6 o utput con figura t ion (WG_OUT PUT) reg ister c ...
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7 Serial I/O (SIO) Port ...
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7- 1 CH A PT ER 7 SE RIAL I/O (S IO) PO RT A serial input/ output (SIO) port provides a m e a ns for th e syst em to comm un i c a te wi t h external devices . The 8XC1 96 M H device has a two-channel serial I/O port tha t sha r es pins wi th po r ts 1 and 2. (The 8XC196M C and 8XC196M D devi ces do not have seria l I/O ports.) T his chapter d e- s ...
8XC196MC, MD, MH USER’S MANUAL 7-2 An independent, 15-bit b au d- rate g e nerator control s the bau d ra t e of the serial p o rt . Either XT A L1 or BCLK x can provide the c lock signal for modes 0–3. In mode 4, the interna l shi ft clock is output o n SC LK x # or an external shift c lock i s input on SCLK x # (i n which ca s e the baud-rate ...
7- 3 SERIAL I/O (SI O) PORT INT_ PEND 1 0 012H I nte rru pt Pendi ng 1 Wh en s et , the TI x b it indi cates a pend ing t ra nsmi t interru pt. Wh en s et , the RI x b it in d ica tes a pen d ing rece ive in terrup t. Whe n set, the SP E b it i ndicat es a pen ding seria l port receive error inte rrupt. Y ou m ust rea d the PI_ PEND re giste r to d ...
8XC196MC, MD, MH USER’S MANUAL 7-4 7.3 SE RIAL PORT MO DES The serial p o rt has both synch r onous and asynchronous operating modes for transmi s sion and re- ception. This se ction des cribes t he operat ion of e ach m ode. PI_MA SK 1 FBCH Perip heral I nt erru pt Mas k Thi s register enab l es an d disa bles m u ltiple xed pe ri pheral interru ...
7- 5 SERIAL I/O (SI O) PORT 7.3.1 Synch ron ou s Mo des (Mo des 0 an d 4) The 8XC196MH serial p ort has two sync h ronous modes, mo d e 0 and mo d e 4. M o de 0 is the syn- chrono us m ode available on a l l the 8XC 196 devices th a t have serial p orts. Mod e 4 is an enha nced, full-duplex synchronous mode. 7.3.1.1 Mode 0 The most com mon u se o f ...
8XC196MC, MD, MH USER’S MANUAL 7-6 Dur ing a rec ep tio n, t he R I fla g in S P x _S T A TUS is set aft er the sto p bit i s sample d . The RI x pend- ing bit in the interrupt pending register is se t immedi a tely before the RI flag is set. During a tr ans- missi on, the TI fla g is se t imme diately aft er the e nd of the last (ei ghth) da t a ...
7- 7 SERIAL I/O (SI O) PORT In mode 4, writing to SBUF x _TX starts a t ransmission regardle ss of whether RXD x is ena bl ed. However , RXD x m ust be ena ble d t o all ow a re cept ion. If RX D x is ena bled, either a risin g e dge on th e RX D x input or c le ari ng the recei ve int errupt (RI) f lag st arts a recept ion. Dis abli ng RX D x stop ...
8XC196MC, MD, MH USER’S MANUAL 7-8 Fi g u re 7-4. Ser ial Port Fr ames fo r Mode 1 The transmi t and receive functions are controlled by separa t e shift clocks. The transmi t shift clock starts when the ba ud-rate generat or is initia l i zed. The rece ive shift cloc k is re set when a s t art bit (high-to-low transition) is received. The refore ...
7- 9 SERIAL I/O (SI O) PORT Figure 7-5. Serial Port Frames in Mode 2 and 3 7.3.2.3 Mode 3 Mo de 3 i s t he asynchronous, nint h -bit mo de. The data fram e for this mo de is identic al to tha t of mode 2 . Mode 3 differs from mode 2 du rin g trans m issi o ns in that pari ty can b e e n able d, in whic h case the ninth bi t be comes the pari ty bit ...
8XC196MC, MD, MH USER’S MANUAL 7-10 7.4 PROG RAMMING THE SERIAL P ORT T o use t he SIO port, y o u m ust co n fig ure the po rt pins to serve as special -fun ction signals and set up the SIO channe ls. 7.4 .1 Config uri ng th e Seri al Po rt P ins Before you can use the seri a l port, you must config ur e the as sociated p o rt pins to serve as s ...
7-11 SERIAL I/O (SI O) PORT 3 REN Re ceive Enab le Sett i ng thi s bit en a bles rece ptions. W hen thi s bit is set, a f alling e dge on th e R XD x pin starts a r eception in mo de 1, 2, or 3. In m o de 0, th is bit must be clea r for transm i ssion to begi n a nd m ust be set for recepti on to b egin . C le ari ng t h is b it st ops a rec ep tio ...
8XC196MC, MD, MH USER’S MANUAL 7-12 7.4.3 Program mi ng the Baud Rate and Clock Source The SP x _BAUD regist e r (Figure 7-7) selects the clock input for the baud-rat e generator and de- fines the baud rate for a ll serial I/O modes . (For mode 4 with SC LK x # configured for input, the baud-r ate genera tor i s no t used.) Thi s re gister acts a ...
7-13 SERIAL I/O (SI O) PORT 14:0 BV14 :0 These bits co nstit u t e th e BAUD_ V AL UE. Us e t he fo llow i ng equa ti ons t o det er mi ne th e B AUD _V ALU E f or a g iven ba ud r a te . Sy nch ron ous mo de 0 : † or Asynch r o nous mod es 1, 2, a n d 3: or Sy nch ron ous mo de 4 (S CL K x # outp ut ): † For mode 0 r e cept ions, the BAUD_V AL ...
8XC196MC, MD, MH USER’S MANUAL 7-14 CAUT ION For mo d e 0 receptions, t he BAUD_V ALUE must be 0002H or grea t er . Othe rwise, t h e re sulting da ta in t he re c e ive shi f t regist er wil l be inc orre c t . The reason for this restric t ion is t hat t he rece ive shift registe r is c locke d from an internal signal rathe r tha n the signal o ...
7-15 SERIAL I/O (SI O) PORT 7.4.5 Determi n ing S erial P ort S tatus Y ou can read the SP x _ST A T US register (F igure 7-8) to determi ne the sta tus of the seri a l port. Readi ng SP x _ST A TUS c lears all bits exce pt TXE. For this r eason, we recomm end that you copy the conte nts of the SP x _ST A T US registe r into a shadow register a nd ...
8XC196MC, MD, MH USER’S MANUAL 7-16 The rece iver chec ks for a valid st op bit. Unle ss a stop bit is f ound w ithin the appropr iate time, t he framing error ( F E) b it in th e SP x _ST A TUS regist er is set. Whe n the s top bit is detected, t he data in t he receive shift registe r is loaded into SBU F x _R X and the re ceive int errupt ( RI ...
8 Fr equ ency Generator ...
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8- 1 CH A PT ER 8 FREQUE NCY GENE RATOR The 8XC 19 6MD has a peripheral not fo und on other 8XC 196M x devic es — the freque ncy gen- erator . This peri pheral produce s a waveform wi th a fixed duty cycle (50%) and a programma ble frequency (rangin g fr o m 4 kHz to 1 MHz w ith a 16-MHz input clock). One appl i c a t ion for the frequency genera ...
8XC196MC, MD, MH USER’S MANUAL 8-2 The freque ncy register (FREQ_GEN) c ontrols the output freq u e ncy . The frequenc y g e nerator loads the FR EQ_GEN value into t he counter . The counter c o unt s down un til it reac hes zero, a t which time the value is reloaded from the FREQ_GEN regi ster . Each load toggle s the D flip-flo p , producing t ...
8- 3 FREQUENCY GENERATOR 8.2 PROG RAM MING THE F REQ UENC Y G E NE RATOR This secti on explains h ow to configure the frequency generator and dete rmine i ts status. 8.2.1 Con figuring the O utput The frequency generat or’ s output is multiplexe d with P7.7, so you m ust c onfi gure it as a spe cial - function output signal. T o do so, follow thi ...
8XC196MC, MD, MH USER’S MANUAL 8-4 8.2.3 Determi ning th e Curren t V a l ue o f the Do wn-c ounter Y ou can rea d the FR EQ_CNT regi ster (Figure 8-3) to dete r m ine the current value of the down- counter . 8.3 AP PLI CATI ON EX AMP L E One ap p li c a t i on for the frequency genera tor is to drive an infrare d LED to transmit rem ote control ...
8-5 FREQUENCY GENERATOR Figure 8-4. Inf rare d Remote C ontrol Appli catio n Bl ock Diagr am Fi gure 8-5. Data En coding Ex ample Thi s p rogr am exam ple was designed t o run on an 8XC1 96MD de mo b oa rd. It uses an EP A ti mer (t ime r 1) a nd com pare c hanne l (COM P3) to pr ovide t he tim ebase f or the one s and z eros. $deb ug $nolist $incl ...
8XC196MC, MD, MH USER’S MANUAL 8-6 ; followed by a short (1 ms) pause, thus generating a MFM waveform. ; ; This program is asse mbled to run on the MD demo board. ; ;********************* ***************** ; CONSTANT AND VARIABL E DECLARATIONS ;********************* ***************** ; Program equates ; This section defines the constants used by ...
8- 7 FREQUENCY GENERATOR ; temp: dsw 1 temp1: dsw 1 temp2: dsw 1 buf_start: dsw 1 buf_cnt: dsb 1 bit_cnt: dsb 1 flag: dsb 1 ;bit 0 = zero being sent ;bit 1 = one being sent ;bit 5 = get next bit ;bit 6 = get next byte ;bit 7 = buffer send in progress ; xmit_buf: dsb bu f_size ;block of data to send shift_reg: dsb 1 ; ;********************* ******** ...
8XC196MC, MD, MH USER’S MANUAL 8-8 stb te mp,freq_gen[0] ;into freq gen ei ;enable interrupts ; ; ;********************* ******************** ; Now send buffer out as serial data bytes ;********************* ******************** ; This section issues a 1 millisecond pulse on P2.0 ; for use with an osci lloscope monitor. ;********************* *** ...
8- 9 FREQUENCY GENERATOR cmpb bu f_cnt,#0 ;see if last byte has been sent jne de c_buf_cnt ;no! ljmp al l_done ;yes! dec_buf_cnt: decb bu f_cnt ;decrement byte count ; get_bit: andb fl ag,#11011111b ;clear get bit flag shlb sh ift_reg,#1 ;shift MSB into carry flag jc se nd_one ;send a one ;else send zero ; send_zero: orb fl ag,#00000001b ;set zero& ...
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9 W aveform Gen erator ...
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9- 1 CH A PT ER 9 W AVE FOR M GE N ERA TOR A waveform generator si mplifie s the t ask of generat ing synchronize d, pulse-widt h modulate d (PWM) out pu ts. This waveform ge n e rator is optimi z e d for motion c ontrol applic a tions s uch as driving 3-ph ase AC induction mot ors, 3-phase DC br ushles s moto r s, or 4-phase step p ing motors. The ...
8XC196MC, MD, MH USER’S MANUAL 9-2 Figure 9-1. W av eform Generator Blo ck Diagram A2637-01 Timebase Generator Phase Driver One of Three Channels WG_RELOAD Buffer WG_RELOAD Update WG_RELOAD WG_COUNTER = 1 WG Interrupt WG_COUNTER = WG_RELOAD WG_COUNTER Phase Comparator Reload Comparator Dead-time & Output Circuitry P6.0 / ...
9- 3 W AVEFORM GENERATOR 9.2 WAVEFORM GENE RATO R SIGNAL S AND REGISTER S T abl e 9-1 desc ribes t he wave form generat o r ’ s sig n al s, and T a ble 9 -2 briefl y desc ribes t he cont rol and sta tus regis ters. . T able 9- 1. W avefor m Generator Signals Port Pi n Wa v efo rm Gen erator S ignal T yp e Des criptio n P 6 .0 WG1 # O Wavefo r m g ...
8XC196MC, MD, MH USER’S MANUAL 9-4 9.3 WAVEFORM GENE RATO R OPERATION This s ectio n describe s the major comp o ne n ts of the wave form ge nerator: the timeba se gene rator , the phase driver c hannels, and the c ontrol and prote c t ion circuit ry . It als o explai n s how t he bu ff- ered re gisters are upda ted and desc ribes the similari ti ...
9- 5 W AVEFORM GENERATOR 9.3.2 Phase Dri ver Ch anne ls The phase driver cha nnels determi n e the duty cyc l e of the outp u t s. Y o u spe cify the duty cycl e by writing a val ue to each phase ’ s c o m pare register (WG_C OMP x ). In all operatin g mode s , t he out- puts are initial ly asse rted, and the y r e main assert ed until the c ount ...
8XC196MC, MD, MH USER’S MANUAL 9-6 The protect ion circ u it r y ( Fig u re 9-3) monitors t he EXT INT pin. When it detects a valid e vent on the input, i t simultaneousl y disables the ou tputs and generate s an EXTINT inte r rupt request. S o ft - ware can also disable t he outputs by clearing the ena ble outputs (EO) bit in the pr o t e ct ion ...
9- 7 W AVEFORM GENERATOR The WG_RE LOAD register is u p da t ed whe n the counte r val ue reache s the reload val u e. The WG_COUNTE R register i s loaded wit h the updated WG_RE LOAD value, so a new reload value takes effect for t he next cyc le. In mo de 3 (and mo de 4 for the 8XC196MH), t he WG_REL OA D register c an be up d ated when an EP A ev ...
8XC196MC, MD, MH USER’S MANUAL 9-8 The mai n differences be twe en the c enter-aligne d mo des an d among t he edge-aligned m ode s are the event s tha t cont rol regi ster u pda tes. T able 9- 4 lists the e vents t hat can cause regi ste r upda tes and the registers t h at ar e updated in e a ch mode. T able 9-3. Ope ratio n i n Center -aligned ...
9- 9 W AVEFORM GENERATOR 9.3.5.1 Center-aligned M odes In the center- a ligned modes, the co un t er counts down from the WG _ RE LOAD value t o 1, t h en counts back up from 1 to WG_RELO AD. When you wri t e to t he WG_RE LOAD re gister , WG_COUNTE R i s loaded with the rel oad value. When you s et the e nable bit in t he control reg- ister, t h e ...
8XC196MC, MD, MH USER’S MANUAL 9-10 Figure 9-5. Center-ali g n ed Mode s — Output Operation 9.3.5.2 Edge-Alig n ed M odes In the edge-aligned modes, the co u nt er begins at 1 and counts up to the W G_RELOAD val ue. When yo u wri t e to the WG_R ELOAD registe r , WG_COUNTE R i s loaded with 0 0 01H. When you set the enable bit in the c ontrol r ...
9-11 W AVEFORM GENERATOR Figure 9-6. Edge-alig n ed Modes — Cou nter Ope ration Fig u r e 9 - 7 . E d ge- a ligned Modes — Output Oper ation 8XC1 96MH only : The 8XC1 9 6MH devi ce has an additio n al edge - a l i gned mode, mode 4. This mode pre vents the output “ j i t t er” that c an occur in mode 3 when an E P A eve nt reloads WG_COUNTE ...
8XC196MC, MD, MH USER’S MANUAL 9-12 9.4 PROG RAMMING THE W AV EFO RM GENERATOR This sect ion expla ins how to configure the wave fo rm generat or and dete rmi ne its status. 9.4.1 Con figuring the O utput s The waveform gene rator ’ s outputs are m ul tipl exed with gene ral-purpose output port 6, so you must c onfigure t hem as spe cial-functi ...
9-13 W AVEFORM GENERATOR WG_ OUTPUT (Waveform Genera tor) Address: Reset Sta te: 1FC0 H 000 0 H The wavef orm g enerato r output configura tion (WG_OUTPU T) regi ster cont rols t he configur ation of the wavefo rm g enera to r and PWM m o dule pins. Bot h t he wa vefo rm ge nerat or and the PWM modu le sha re pin s with p ort 6. H avin g these cont ...
8XC196MC, MD, MH USER’S MANUAL 9-14 10 P H3.2 Pha se 3 Functi on S elects eith er the p ort functio n or the wavefo rm gene rat or ou tpu t fun ctio n for p i ns P6 .4/WG3# a nd P6 .5/WG3 . 0 = P6 .4, P6 .5 1 = WG3#, WG3 9 P H2.2 P hase 2 Fu nction S elects eith er the p ort functio n or the wavefo rm gene rat or ou tpu t fun ctio n for p i ns P6 ...
9-15 W AVEFORM GENERATOR 9.4.2 Control ling the Pro tectio n Circui try and EXTINT I nterr upt Gen erati on The protect ion register (Figure 9 -9) controls the prote c t ion circuitry a nd EXTINT inte rr upt r e - qu ests . WG_PROTECT Address: Re set State (M C, MD) R eset Sta te (M H): 1FC EH F0 H E0 H The wa vefo rm p rotectio n (WG_ PROTECT) re ...
8XC196MC, MD, MH USER’S MANUAL 9-16 9.4.3 Speci fyin g the Carrier Peri od a nd Duty Cycl e The reload regi ster (WG _RELOAD) and the phase c ompare regist ers (WG_COM P x ) co ntrol the car r ie r period an d duty cycl e. Write a val ue to the re load registe r (Figure 9 - 10) to es tablish the car r i er period. Write a val ue t o each phase co ...
9-17 W AVEFORM GENERATOR 9.4.4 Speci fyin g the Operati ng Mod e and Dead Time and S tarti ng the Co unter The contr o l regist er (Figure 9- 12) specifies the dead time a n d o p e rating mode and enables an d disable s the counte rs. A read -only bit (CS) indic ates the curre nt count direc tio n. WG_COMP x x = 1–3 Ad dress : Re s et S ta te: 1 ...
8XC196MC, MD, MH USER’S MANUAL 9-18 WG_CONTROL Address: Re s et S ta te ( MC, M D): R eset Sta te (M H): 1FC CH 00 C0 H 800 0 H The wavef orm g enerato r control (WG_CONT ROL) registe r con trol s th e ope ra tin g mode , dea d tim e , and coun t d irectio n, and enab les and disa bl es the counte r . 15 8 — M2 M1 M0 CS EC DT 9 DT8 7 0 DT7 DT6 ...
9-19 W AVEFORM GENERATOR 9.5 DET ERM I NING THE W AVEFORM GENE RATO R ’ S STATUS Read WG_CONTROL (Figure 9 -12 on page 9-18) to det ermine the current dead-ti me val ue, counter status, count direc tion, a nd operating mode. Read WG_COUNT ER (F igure 9 -13) to d e - termi n e the current counter value . 9.6 ENABL ING THE W AVEFORM GENER ATOR INTE ...
8XC196MC, MD, MH USER’S MANUAL 9-20 T o ena b l e the i nterrupts, set the corresponding ma sk bi ts in the m ask register (se e T a ble 9-2 on page 9-3) and exec ute t he EI inst ruc tion to enable i nte rrupt s ervic ing. Y ou c an read the inte rr upt pending regist er to det ermine whether there a re any pending i nterrupt s. Refer to Chapter ...
9-21 W AVEFORM GENERATOR 9.7 .2 E XTINT I nter rupts an d Protec tion Circu itry The protect ion regi ster contai n s two bits, disabl e pr otectio n (DP ) and ena ble out p ut (EO), t hat t o- get h er enabl e and disa ble the wa veform genera tor ’ s o u t puts. The E XTINT event gen erat es a s i n- gl e short pulse t hat cle ars the E O bi t, ...
8XC196MC, MD, MH USER’S MANUAL 9-22 ph3: dsw 1 ;P6.4,5 config eo: dsw 1 ;0=disable output, 1=enable output dp: dsw 1 ;0=enable protection, 1=disable it: dsw 1 ;0=falling edge trig, 1=rising edge es: dsw 1 ;0=edge, 1=sample ec: dsw 1 ;0=stop cntr, 1=start dead: dsw 1 ;10-bit dead time reload: dsw 1 comp1: dsw 1 comp2: dsw 1 comp3: dsw 1 temp: dsw ...
9-23 W AVEFORM GENERATOR ;load WFG registers ; call wgout ;initialize WG_OUTPUT reg ister call loadregs ;initialize reload & comp are regs call protect ;initialize protection call wgcon ;initialize WG_CONTROL ; ;enable interrupts & l oop here ; ei sjmp $ ; ;********************* ******************* ; form WG_OUTPUT value from variable data ...
8XC196MC, MD, MH USER’S MANUAL 9-24 or temp1,temp ;combine ld temp,p6 ;get p6 bit and temp,#0001h ;mask shl temp,#6 ;move to correct location or temp1,temp ;combine ld temp,ph3 ;get ph3 bits again and temp,#0003h ;mask for ph3.0 & 1 shl temp,#4h ;move or temp1,temp ;combine1 ld temp,ph2 ;get ph2 bits again and temp,#0003h ;mask for ph2.0 & ...
9-25 W AVEFORM GENERATOR and temp,#0001h ;mask shl temp,#3 ;shift to correct location ld temp1,it ;interrupt type bit and temp1,#0001h ;mask shl temp1,#2 ;shift to correct locatio n or temp,temp1 ;combine into temp ld temp1,dp ;disable protection bit and temp1,#0001h ;mask shl temp1,#1 ;shift to correct locatio n or temp,temp1 ;combine into temp ld ...
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10 Pulse-width Modulator ...
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10 -1 CHAPTER 10 PUL SE -W IDT H MO DUL AT O R The pulse -width modula tor (PWM ) module has two output pins, eac h of which can out put a PWM si gnal w ith a fixed, p rogram mable fre que ncy and a variabl e duty cycle. These out puts can be used to drive motors that require an unfiltered PWM waveform for optima l ef fici ency , or they can be fi ...
8XC196MC, MD, MH USER’S MANUAL 10 -2 Figure 10-1. P W M Block Diagram 10.2 P WM SIGNAL S AND REGI S TE RS T abl e 10- 1 de scribes t he PWM’ s signa ls and T able 1 0 -2 briefl y d esc r ibes t he control and st a t us registe rs. T able 10-1. PWM Signals Port P in PW M Sig n a l PW M Si gnal T y pe De s c ripti on P6.6 PWM 0 O Pu lse- wid th m ...
10 -3 PULSE-WIDTH M ODULATOR 10.3 P WM OP E RATI ON The period re gister ( P WM _PERIOD) c ontrols the output freq u e ncy of both PWM output s. Each control regi ster (P WM x _C ONTROL ) contr o ls the duty cycl e (the p ulsewidt h stated a s a perce nt- age of the period) of the correspon di ng PWM output. Each control regist er contains a n 8-bi ...
8XC196MC, MD, MH USER’S MANUAL 10 -4 The counter counts down to 00H, at which time the PWM o u tput is driven high, the counter value is re loaded from t he PWM _PERIOD re g ister , an d the content s of the control registers are loaded into the bu ffers. The PWM out p ut remains high unti l the c ou nter va lue ma tches the val ue i n the buf fe ...
10 -5 PULSE-WIDTH M ODULATOR where: PWM_PERIOD = 8-b it v alue to l o ad i n to the PWM_PERIOD reg ister F XTAL 1 = in put fr e q uency on XT AL 1 p in, i n MHz T PWM = ou t put p eriod o n the P WM o ut put pi ns, in µ s F PWM = ou tp ut freq u ency o n t he PWM outp ut pi ns, in MHz T able 10 -3. PWM Out put Frequencies (F PWM ) PW M_PE RIOD XT ...
8XC196MC, MD, MH USER’S MANUAL 10 -6 10.5 P ROGRAM MING TH E DUTY CY CLE The va lues wri t t en to the PWM x _CO NTR OL and PWM_PE RIOD registers control the width of the hi gh pulse, e f fec t ivel y cont rolling the duty cycle . The 8-bit val ue writ ten to the co n trol regis- ter is loaded into a buf fer , and this v alue is used during th e ...
10 -7 PULSE-WIDTH M ODULATOR 10.5.1 Sam ple C alcula tions For example , assume that F XTAL 1 equa ls 16 MHz a nd the value wri t t en to the PWM_ PER I O D reg - ister is FFH, thus the des ired period of the PWM output wavef o rm i s 8. 19 ms. If PWM x _CONTROL equals 8AH ( 138 decima l), the pulse width i s held hi gh for 4.42 ms (and low for 3.7 ...
8XC196MC, MD, MH USER’S MANUAL 10 -8 10.5.3 Enab l ing the P WM Outp uts Each PWM outp ut is multiplexed with a port pi n, so yo u must configure it as a specia l-function output signa l before u s ing the PWM function . T o dete r m ine whe ther the cor re sponding pin fun c- tions as a standard I/O p ort pin or as a PWM output you must make t h ...
10 -9 PULSE-WIDTH M ODULATOR WG_ OUTPUT (Waveform Genera tor) Address: Reset Sta te: 1FC0 H 000 0 H The wavef orm g enerato r output configura tion (WG_OUTPU T) regi ster cont rols t he configur ation of the wavefo rm g enera to r and PWM m o dule pins. Bot h t he wa vefo rm ge nerat or and the PWM modu le sha re pin s with p ort 6. H avin g these ...
8XC196MC, MD, MH USER’S MANUAL 10 -10 10.5.4 Generati ng An alog Ou tputs PWM m odules ca n genera te a recta n g ul ar pul se t rai n that varie s in duty c ycle an d period. Filt er- ing this output will create a smo o th analo g signal. T o make a signal swing ove r the desired ana log range, firs t buffer the si gna l and then filter it with ...
11 Event Pr ocessor Array (EP A) ...
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11 -1 C HAPT ER 1 1 EVENT PRO CESSOR ARRAY (E P A ) Contr o l applications often req u i re high-speed eve n t control. For example , t h e controller may need to periodic a l ly genera t e pulse-width modulated o u tputs o r an interrupt. In another applicati on, the controlle r may monit or an inp u t s ignal to determi ne the s t a tus of an ext ...
8XC196MC, MD, MH USER’S MANUAL 11 -2 Figure 1 1- 1. EP A Block Diagram 1 1.2 E P A AND T IMER/ COUNT ER SI GNALS AND REGISTERS T abl e 1 1 -2 de scribes t he EP A and time r/counter input a nd output signals. E a ch signal i s multi- plexed wi th a port pi n as shown in t he first co lumn. T able 1 1-3 bri efly de sc ribes the registers for the E ...
11 -3 EVENT PROCESSOR ARRAY (EP A) P2 .4 P2 .5 P2 .6 P2 .7 — — P2 .4 P2 .5 P2 .6 P2 .7 P7 .2 P7 .3 P 2.4 P 2.5 P 2.6 P 2.3 — — COMP0 COMP1 COMP2 COMP3 COMP4 COMP5 O Ou tput of the compare-o nly chan nels. T able 1 1-3. E P A Control and Status Registers Mne moni c Ad dress De s c ription MC MD MH COMP0 _CON COMP1 _CON COMP2 _CON COMP3 _CON ...
8XC196MC, MD, MH USER’S MANUAL 11 -4 INT_ PEN D 0 009H 0009 H 000 9H In terrup t Pend ing Any set b it in thi s 8-bit reg iste r i ndicat es a pend ing inte rrupt re quest. INT_ PEND1 0 0 12H 0012H 0 0 12H Interr upt Pend i ng 1 Any set b it in thi s 8-bit reg iste r i ndicat es a pend ing inte rrupt re quest. P2 _DI R P7 _DI R 1F D2H — 1FD2 H ...
11 -5 EVENT PROCESSOR ARRAY (EP A) 1 1.3 TIMER/C OUNT ER FUNCTIONAL OVERVIEW The EP A has tw o 1 6 -bi t up/down timer/counters , time r 1 and timer 2, which can be clocked in- ter n ally o r external ly . Eac h is calle d a time r if it is c locked internal ly an d a counte r if it i s cl ock ed external ly . Fi g ure 1 1 -2 i llust ra tes the tim ...
8XC196MC, MD, MH USER’S MANUAL 11 -6 Fig u re 1 1-2. EP A Timer/ Counte rs The timer/ counters can be used as time bases for input capture s, output compares , and p ro- grammed i n t er rupts (sof twa r e timers). W hen a c ounter increments from FFFEH t o FFFFH or dec- rements from 0001H to 0000H, the counte r-ov erflow/ u nderflow inte rrupt p ...
11 -7 EVENT PROCESSOR ARRAY (EP A) where: pre s caler_d ivisor is th e clock pres cale r d ivisor from the T x CONTROL re gisters (see “Ti m er 1 Control (T 1CONTROL) Reg ister” on p age 1 1- 16 a nd “Ti m er 2 Control (T 2CONTROL) Register” on p age 1 1- 17). F XTAL 1 is th e in p u t fre quen cy on XTA L 1. 1 1.3.1 Cascade Mode (T i mer 2 ...
8XC196MC, MD, MH USER’S MANUAL 11 -8 Figure 1 1- 3. Quadrature Mode I nterfa ce T ab le 1 1-4. Quad r atur e Mode T ruth T able Sta te o f X_i nte rnal (T1CLK) S tate of Y_ inte rnal (T1DIR) Co unt Direc tio n ↑ 0 Increm ent ↓ 1 Increm ent 0 ↓ Increm ent 1 ↑ Increm ent ↓ 0 D ec reme nt ↑ 1 D ec reme nt 0 ↑ De c re ment 1 ↓ De c re ...
11 -9 EVENT PROCESSOR ARRAY (EP A) Figure 1 1-4. Quadrature Mode Ti min g an d Count 1 1.4 E P A CHANNEL FUNCTIONAL OV ERV IEW The EP A has both programmable c a pture/compa re and compare-only chan n e ls. E a ch cap- ture/c ompare channe l can per f orm the f o ll o w ing tasks. (The compare-only c h annel s have the same functionality exc ept t ...
8XC196MC, MD, MH USER’S MANUAL 11 -10 Each EP A channel has a contr o l register , E P A x _C ON (capture/ compare c hannels) o r COM P x _CON (compare -only channels) ; an eve nt-time regist er , E P A x _T IME (c apt ure/compare channe ls) or COM P x _TIME (compare- only channels); and a time r input (Figure 11-5). T h e con - trol regi ster se ...
11-11 EVENT PROCESSOR ARRAY (EP A) Figure 1 1-6. EP A Simpli fied Input- c apture Structure If a third event occ urs befo r e the CPU reads the event-time re giste r , the ove r writ e b it (EP A x _CON. 0) determines how the EP A will handl e the event. If the bi t is c l ea r , the EP A i gnore s the thi rd event. If the bit is set, the third eve ...
8XC196MC, MD, MH USER’S MANUAL 11 -12 An input c ap ture e vent does n o t s e t t he interrupt pen d i ng bit until the captured t i me va lue ac tuall y moves from the capture bu f fer into the EP A x _T IME re gist er . I f t he b u ffer cont ains da ta a n d the P T S i s used t o service the i nterrupts , then two P T S inter rupts occur alm ...
11-13 EVENT PROCESSOR ARRAY (EP A) 1 1.4. 1.2 Preventi ng EP A Overru ns An y one of the following methods can be used t o prevent or recover from an EP A overrun si tua- t ion. • Cle ar EP A x _CON.0 Wh e n the overw ri t e bit ( EP A x _C ON.0) is zero, the EP A does no t co n sider the captured e dge un til t he E P A x _T I M E re gister is r ...
8XC196MC, MD, MH USER’S MANUAL 11 -14 The ma ximum output f re quency depends up o n the total interrupt l a t e ncy and the i nt errup t-se r vi ce executi on tim es used b y your system. As additional EP A cha n nels and the other functions o f the microcont r olle r are u sed, the m axi mum PWM frequency decreas es beca use t h e t otal i n te ...
11-15 EVENT PROCESSOR ARRAY (EP A) W i th thi s method, the resolut ion o f the EP A (sel ec ted by the T x CO NT R OL regi ste rs; se e Fig ure 1 1 -8 on page 1 1- 16 and Figure 11-9 on page 1 1 - 17) det ermine s t he maximum PWM output f r e - quenc y . (Res oluti o n is the m ini mum t ime re q uired betwe en conse cut ive c apt ures or com par ...
8XC196MC, MD, MH USER’S MANUAL 11 -16 T1CONTROL Address: Reset Sta te: 1F 78 H 00 H The t i mer 1 con trol (T1CONTROL ) registe r determ ines the clo c k sou rce, coun ti ng dire ction, an d count ra te for tim e r 1 . 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Num b e r Bit Mne moni c F unction 7 CE Cou nt er E nabl e Thi s bit e n ables or disabl es the t ...
11-17 EVENT PROCESSOR ARRAY (EP A) T2CONTROL Address: Reset Sta te: 1F 7CH 00 H The t i mer 2 con trol (T2CONTROL ) registe r determ ines the clo c k sou rce, coun ti ng dire ction, an d count ra te for tim e r 2 . 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Num b e r Bit Mne moni c F unction 7 CE Cou nt er E nabl e Thi s bit e n ables or disabl es the t imer ...
8XC196MC, MD, MH USER’S MANUAL 11 -18 1 1. 5. 3 Prog ram mi ng the Capture/ Co m pare Ch ann els The EP A x _C ON register control s the function of its ass igned capture / com pare channel . The reg- isters are i dentic a l w ith the except ion of bit 2. For EP A c hannels 0, 2, a n d 4, se t t ing this bit ena bles an EP A eve n t to cause a wa ...
11-19 EVENT PROCESSOR ARRAY (EP A) EP A x _CON x = 0 –1 ( 8XC196 MH) x = 0 –3 ( 8XC196 MC) x = 0 –5 ( 8XC196 MD) Address: Reset Sta te: S ee T abl e 1 1- 3 o n pa ge 1 1- 3 00H The EP A control (EP A x _CON) registe rs cont ro l the f unctio ns of th eir a s signed capture /comp are cha n n els. 7 0 x = 0, 2, 4 TB CE M1 M0 RE WGR ROT ON/RT 7 ...
8XC196MC, MD, MH USER’S MANUAL 11 -20 3 R E Re -en ab le Re- enab le applie s to the comp are mode on ly . It allows a compa re even t to continue to e xecute each time the e vent-ti me re gist er (EP A x _ TIME) match es the ref ere nce time r rather tha n o nly up on the first time match. 0 = comp are f uncti o n i s disa bled after a si ngle e ...
11-21 EVENT PROCESSOR ARRAY (EP A) 1 ROT Rese t Oppo site Ti m er Con trols d iffer e n t functi ons for cap ture a nd com pare mod es. In Cap ture Mode: 0 = ca uses no actio n 1 = re sets the opposite timer In Compa re Mo de: Sele c ts the time r that is t o be reset if th e R T bi t is set . 0 = se lects t h e re ference time r for p ossible rese ...
8XC196MC, MD, MH USER’S MANUAL 11 -22 1 1. 5.4 Prog ramm ing the Compare -only Chan nel s T o program a compar e ev e n t, you must f irst write t o the COM P x _C ON regist er (Figure 1 1- 1 1) to configure the c ompare-only channe l a nd then load the event tim e i nto COMP x _TIM E. COM P x _CON has the sa me bits and settings as EP A x _CON. ...
11-23 EVENT PROCESSOR ARRAY (EP A) 1 1.6 E NABLING THE E P A IN TERRUPTS T o enabl e the interrupts, se t the corre sponding bits in t he INT _ MASK register (Figure 5-7 o n page 5- 15). T o e nable the in d ividua l source s of the multiple xed PI (MC , M D) , SPI (M H), and OVR T M (M x ) in terrupts, s et th e cor respon ding b its in the PI_MAS ...
8XC196MC, MD, MH USER’S MANUAL 11 -24 1 1.7 DE TERMINING EV ENT S TATUS In compare mode, an in te r rupt p e nding bit is s et each time a matc h oc curs on an enabled event (even if the inte r rupt is spec ifically ma sked in the ma sk r e giste r ). In capture mo d e , an inter ru pt pending bit is set eac h time a programme d event is captured ...
12 Analog-to-d igital Converter ...
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12 -1 CHAPTER 12 ANALO G -TO -DIG ITA L (A/D) CON VER TE R The anal o g-to- digital (A/D) c onve rter can convert an analog input volt age to a digit al value and set the A/D interrupt pendin g bit when it stores the resul t. It ca n a lso m onit o r a pin and s e t the A/D interrupt pending bit when the input voltage crosse s over or under a progr ...
8XC196MC, MD, MH USER’S MANUAL 12 -2 12.2 A/ D CONV ERTE R SIGNAL S AND REGIS TER S T abl e 12 -1 lists the A/ D signal s and T abl e 12- 2 describe s the contr o l a nd status r e gisters . Al - though the analog inputs are multiplexed with I/O port pins, no configuration is necessar y . T able 12-1. A/D Co nverter Pi ns Port Pin A/D Signal A/D ...
12 -3 ANA LOG-TO- DIGI TAL (A /D) CONVERTER 12.3 A/ D CONV E RTE R OPER ATI ON An A/ D conversion c o nverts a n analog input vo ltage to a digital val u e , stores t h e result in the AD_RESUL T re gister , and se t s t he A/ D inte rr upt pendin g bit. A n 8-bit conversion provide s 20 mV resol ution, while a 10-bit conversion prov ides 5 mV re s ...
8XC196MC, MD, MH USER’S MANUAL 12 -4 Once the A/D co nverte r receives the c omma nd to s ta rt a c on version, a delay t ime elapse s before sampli ng begins. (EP A-i nitiated con v e rsions begin afte r t he capture / c ompare e vent. Immedia t e conversio n s, those init iated direct ly by a write to AD_COM MAND, begin within three s t a te ti ...
12 -5 ANA LOG-TO- DIGI TAL (A /D) CONVERTER 12.4.1 Prog ram mi ng the A/D T es t Register The AD_TEST regist er (Fig u re 12 - 2) anal og speci fies an o f fset voltage to be a pplied t o the r esi s- tor ladde r . T o use the z ero-of fset adjust men t, first perform two conversi ons, on e on ANGND and on e o n V REF . W i th the results of these ...
8XC196MC, MD, MH USER’S MANUAL 12 -6 12.4.3 Prog ramm ing the A/ D Tim e Re g ister T wo parame ters, sam ple t im e and conversion ti me, control the t im e required for an A/D conver- sion. The sampl e time i s the length of time that the anal og in put voltage i s ac tua lly conne ct ed to the sa mple c apacito r . If this tim e is too short, ...
12 -7 ANA LOG-TO- DIGI TAL (A /D) CONVERTER 12.4.4 Prog ram mi ng the A/D Comm an d Regis ter The A/D comm and regist er c ontr ols the operat ing mode, the a nal og in p ut channel, an d the con- version trig ger . AD_TIM E Ad dress: Reset Sta te: 1F AFH FF H The A/D tim e (AD_ TIME) registe r prog r ams the s ample wind ow time a n d the con vers ...
8XC196MC, MD, MH USER’S MANUAL 12 -8 12.4.5 Enab ling the A/ D Inte rrupt The A/D converter can set t he A/D int errup t pen d ing bit when it c ompletes a con v ersion or wh en the i np u t voltage cross es the thres hold va lue in the se l ect ed dire ction. T o enable the interrupt, set the corresponding m ask bit in the i nterrupt m ask regis ...
12 -9 ANA LOG-TO- DIGI TAL (A /D) CONVERTER 12.5 DE T ERMI NING A / D ST ATUS AND CONVE RSION RESULT S Y ou can re ad the AD_ RESUL T register (Fig u re 12-6) to determine the s tatus of the A/D c o nvert- er . T he AD _RE SUL T regi ster is cleare d when a new conversion i s started; therefore, to prevent losin g dat a, yo u must read both bytes b ...
8XC196MC, MD, MH USER’S MANUAL 12 -10 12. 6 DE SIG N C ONS IDER AT ION S This secti on descri bes consi dera tio ns for the exte r nal inte rface circuit ry and descri bes t he errors that can occ ur in any A/D convert er . The d a t ashee t lists the a bsol ute err o r specification, which includes a l l de viations betwee n the actual conversio ...
12-11 ANA LOG-TO- DIGI TAL (A /D) CONVERTER T ypic a lly , the (R F / A V + 1) te rm is the ma jor contribut or to t he tot al resi st ance an d t h e factor that determi nes the mini mum sam ple tim e specifie d in the da tashee t. 12.6.1.1 Mini mizing the Ef fect of Hi gh Input Source Resist ance Under som e cond i tions, the input source re sist ...
8XC196MC, MD, MH USER’S MANUAL 12 -12 12.6.1.2 Su ggested A/D I nput Circui t The sugges ted A /D inp ut c i rcui t s ho wn in Figu r e 12-8 provides limited prot e c t i on against o v e r - volt age cond i tions on the analog in pu t . Sho ul d the input v o ltage be driven signi f i c antly bel o w ANGND or above V REF , diode D2 or D1 w ill f ...
12-13 ANA LOG-TO- DIGI TAL (A /D) CONVERTER ANGND should be w i t hin about ± 5 0 mV of V SS . V REF should be well regulated a nd use d only for the A/D c onverte r . The V REF supply can be betwee n 4.5 and 5.5 volts and must be able t o sour ce approximately 5 mA (see the datashee t for actual specifications). V RE F should be ap prox- imat e l ...
8XC196MC, MD, MH USER’S MANUAL 12 -14 In many appli cations, i t i s less c ritical to re cord the absolut e a c curacy of a n input than it i s t o de- tect tha t a cha n ge has oc curred. This a pproa ch is accepta ble as lon g as the convert er is mono t onic and has n o m issing code s . That is, increa s ing i nput voltages produce adj a c e ...
12-15 ANA LOG-TO- DIGI TAL (A /D) CONVERTER Figure 12-9. Ideal A/D Conversion Character isti c Note t hat t he idea l characteri stic posse sses unique qualities: • its first code transi tio n occurs when t he input v oltage is 0.5 LSB; • its full-sc ale co d e transitio n occurs whe n the input vol tage eq u als the full-sca le reference volt ...
8XC196MC, MD, MH USER’S MANUAL 12 -16 Figure 12-10. Actual a nd Ideal A/D Conversi o n Characteristi cs The actua l c hara cteristic o f a hypothetica l 3 -bit convert er i s not perfec t. Whe n the i deal c harac - terist ic is overla id with t h e ac tual charac t e ristic, the a c tual converter is seen to exhibi t e rrors in the loc ations of ...
12-17 ANA LOG-TO- DIGI TAL (A /D) CONVERTER Differentia l nonlinea r i ty i s the degre e to which a c tual code w idths dif fer from the idea l one -LSB width. It provides a meas u re of how muc h the i nput voltage m ay have changed in order to produce a o ne-count cha nge i n t he c o nversi on resul t. In the 1 0-bit convert er , t he c ode wid ...
8XC196MC, MD, MH USER’S MANUAL 12 -18 Figure 12-1 1. T erminal-based A/D Conv ersion Characteristic IDEAL FULL-SCALE CODE TRANSITION ACTUAL FIRST TRANSITION 1 / 2 123 45 67 8 6 1/2 0 1 2 3 4 5 6 7 INPUT VOLTAGE (LSBs) Ø OUTPUT CODE, Q IDEAL STRAIGHT LINE TRANSFER FUNCTION NON-LINEARITY DIFFERENTIAL NON-LINEARITY (POSITIVE) IDEAL C ...
13 Minimum H ardwar e Considerat ions ...
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13 -1 CHAPTER 13 MINIM UM HARDWARE CONSIDE RAT IONS The 8X C196MC , MD, and M H have se veral basic require ments for opera t i on within a system. This chapt er describes o p tions for p roviding the basic req u irements and discusses other hardware considerat ions. 13.1 M INIM U M CO NNECTI ONS T able 13-1 lists t he sig n als that are re quired ...
8XC196MC, MD, MH USER’S MANUAL 13 -2 13.1.1 Unused I npu ts For predic tabl e performanc e , it i s i mportant to tie unused in pu t s to V CC or V SS . Othe rwise, they can floa t t o a mid -v ol tage l e vel and draw excessive current . Unuse d interrupt inputs may generate spur ious i nte r r upt s i f left unconnected. 13.1.2 I/O Port P in Co ...
13 -3 MINIMUM HARDWARE CONSIDERATI ON S Figure 13 -1. Minimum Hardware Conn ect ions ALE ANGND INST XTAL1 XTAL2 V CC (Note 2) 0.01 µF BUSWIDTH NMI READY V CC Port 5 / Bus Control (Note 4) 20 pF 20 pF (Note 1) 4.7 µF + V CC + 1 µF 1 M RESET# BHE# WR# RD# EA# + 1 µF V CC V CC A2643-03 V SS V PP V REF 8XC196 Device V CC Notes: 1. See the ...
8XC196MC, MD, MH USER’S MANUAL 13 -4 13.2 AP PLYI NG AND REMOVI NG POWER When power is first applied to the device, RESE T# must re m ain conti nuously low for at least one state ti me aft er the p ower supply is wit hin tole ranc e an d the oscilla tor/ clock ha s stabi lized; oth - erwise, operat ion might b e un p re dictable. Similarly , when ...
13 -5 MINIMUM HARDWARE CONSIDERATI ON S If the A/D converter wil l be used, conne ct V REF to a separa te reference supply to m ini mi ze noise durin g A/ D conve rs ions. Eve n if the A/D converte r wil l not be use d, V REF and ANGND must be connected to provide power t o po rt 0. On the 8XC1 9 6M C and MD, th e y a l so provide power to por t 1. ...
8XC196MC, MD, MH USER’S MANUAL 13 -6 Figure 13-4 shows the c o nnections betwe en the external crystal and the device. When designing an external osc i l la t or circuit, conside r the effects of p arasi tic board c apac i t ance, extended oper - ating tempe ratures, and cryst a l specifications. Co n s ult the manufac turer ’ s dat asheet for ...
13 -7 MINIMUM HARDWARE CONSIDERATI ON S 13.5 US ING AN E XTERNAL C LOCK SOURCE T o use an external c l ock source, apply a cloc k s ig n al to XT AL1 and le t XT AL2 f loat (Figure 13-5). T o ensure proper o peration, the ext ernal clock so u rc e must meet the m inimum high a nd low ti mes (T XH XX and T XLXX ) and the m axi mum ri se and fall tra ...
8XC196MC, MD, MH USER’S MANUAL 13 -8 13.6 R E SE TT ING THE DE VICE Res et f o r ces the device into a known state. As soon as RESET# is asserted, the I/O pins, the con- trol pins, a nd the regist ers are dri ven to their re s et states. (T ables in Appendix B l i st the rese t s t ates of the pins (see T abl e B-8 on page B- 2 3 for the 8XC196M ...
13 -9 MINIMUM HARDWARE CONSIDERATI ON S The 8XC196M H provides the o ption of an internal-only re set or an internal rese t that is also re- flect ed exte rnally ( by the RESE T# pin). T he GEN_C ON re gister controls w hether a n interna l re- set ass erts the e x t erna l R ESET# si g na l and i ndicate s the s o urc e of the most rec ent reset. ...
8XC196MC, MD, MH USER’S MANUAL 13 -10 Figur e 13 -9. Internal Reset Circuit ry 13.6.1 Generati ng an E xternal Res et T o re se t the de v ic e, hold the R ESET # pin l ow for at least one st a te t ime af ter the powe r supply i s within tol erance and the osci llator has sta bilized. When RESET# is first ass erted, the device t urns on a pul l- ...
13-11 MINIMUM HARDWARE CONSIDERATI ON S Figure 13-10. Minim um R eset Circuit Other device s in the sys t e m may not be reset because the capa citor will keep the voltage a bove V IL . Since RE SET# i s asserted fo r on ly 16 state times, it may be ne c essa ry to le ngthen an d buf fer the syst em-reset pul se . Fi g ure 13-1 1 sho ws an example ...
8XC196MC, MD, MH USER’S MANUAL 13 -12 13.6.2 Issui ng the Res et (RST) I n struc tion The RST inst ruct ion (o pcode FFH) resets t he devi ce by pulli ng RES ET# lo w f or 16 state times. It also c le ars the p r o cess o r sta tus word (PSW), sets the master program counter (PC ) t o 2 080H, and resets the spec ial function regist ers (SFRs). Se ...
13-13 MINIMUM HARDWARE CONSIDERATI ON S Y ou mus t write two consec utive bytes to the wa tch d o g re gist er (location 0AH) to cl ear it. For the 8XC196MC a n d MD, the first byte must be 1EH and the second must be E1H. For the 8XC196MH, t h e first byte must also be 1EH; however , the second byte can be one of four values. The second by te deter ...
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14 Special Op erating Modes ...
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14 -1 CHAPTER 14 SPE CIA L OPE RATI NG M ODES The 8XC1 9 6MC , MD, and MH provide two power savin g mode s : id le and powerdown. They also provide an on-circ uit emulation (ONC E) mode t hat electricall y isolate s the device from the other syste m component s. This cha pte r describes ea ch m o de an d explains h ow to e nte r and exit each. (Re ...
8XC196MC, MD, MH USER’S MANUAL 14 -2 P5.4 ONCE# I On- circuit Em u lation Ho l d ing ON CE# low d urin g t h e risin g edge of RES ET# p laces the device int o on-circuit emu latio n (ONCE) m ode . This mode puts all pins, e xcept XT AL1 and XT AL2, into a h igh-imp e d ance state, th ereby iso latin g t he device from other co mpo ne nts in the ...
14 -3 SPECIAL OPERATING MODES 14.2 RE DUCI NG POWE R CONS UM PTI ON Both p o w er -sa v i ng modes conserve power by disa bling portions of t h e internal cloc k c ircui try (Figure 14-1). The following paragraphs descri be both modes i n detail. P 1 _ DIR (M H) P2 _DI R P5 _DI R P 7 _ DIR (M D) 1F 9BH 1FD2 H 1FF3 H 1FD3 H Po rt x Di rection Eac h ...
8XC196MC, MD, MH USER’S MANUAL 14 -4 Figure 14-1. Clock Control Dur ing Pow er-saving Modes 14.3 I DLE MOD E In idle m o de , the devic e’ s power consumption d ecrease s to approximat ely 40% of normal con- sumption. Inte rnal logic holds the CPU clocks a t logi c z ero, ca u s ing the C PU to stop execut ing instruct ions. Neit her the periph ...
14 -5 SPECIAL OPERATING MODES The device ent ers i dle mode after executi ng the IDLPD # 1 instruct ion. Any enabled inte rrupt sour ce, eithe r internal or exter n al, o r a hardware reset can c ause the device t o exit idle mode. When an int errupt oc curs, t he C PU clocks res tart a n d the CP U execute s the c orre spon ding i nter- rupt se rv ...
8XC196MC, MD, MH USER’S MANUAL 14 -6 14.4.2 Enteri ng P owerd own Mo de Before ente ring powerdown, compl ete the following tasks: • Comple te all seri a l port transmis sions or recepti o ns. Ot herwise, when the de v i ce exits power dow n, t he se ria l port activit y will continue where i t left off and i ncorrec t data may be tra nsmi tt e ...
14 -7 SPECIAL OPERATING MODES 14.4.3.3 As sertin g the Ext ernal Inter rupt Signal The final way to e xit powerdown mode is t o assert the exte rnal interrupt signal (EXTINT ) for a t least 50 ns. Al thoug h E XTINT is norma l l y a sampled input, the powe r down circui try uses it as a level-sensitive input. The i nt e rrupt need not be enabled to ...
8XC196MC, MD, MH USER’S MANUAL 14 -8 Figure 14-3. E x ternal RC Circuit During normal operation (before entering powerdown mode), an internal pull-up holds the V PP pin at V CC . When an external i nterrupt si gnal is asserte d, the inte rnal oscillato r circ uitry is enabled and turns on a weak inte rnal pul l-down . This weak pull-down ca uses ...
14 -9 SPECIAL OPERATING MODES Fig u r e 14-4. T ypical V ol tage on th e V PP Pin W hile E xiting Powerdown Selec t a resi st or t hat wi ll n ot int erfe re wi th the disc h arge current. In most c as es, val ues bet ween 20 0 k Ω and 1 M Ω should pe r form satisfac torily . V PP , Volts 1 2 3 4 5 200 µ A C 1 Discharge Pullup On Code Execu ...
8XC196MC, MD, MH USER’S MANUAL 14 -10 When sele c ting the c apacito r , determ ine the wo r s t-case di scharge time ne eded for the osci llator to stabilize, t hen use this form ula to calculate an appropria te va l ue for C 1 . where: C 1 is th e capa citor val ue, in f arads T DIS is the worst-case dis charge t ime , in seconds I is th e disc ...
14-11 SPECIAL OPERATING MODES Holding the ONC E# signal low during the rising edge of R E SET# cause s t he d e vice to enter ONCE m ode. T o prevent accidenta l entr y into ONCE mode, we highl y rec omme nd con figuring this pi n a s a n output . If you choose to configure this pin a s an input, always hold i t hi gh during reset a n d ens ure tha ...
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15 Interfacing with External M emory ...
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15 -1 CHAPTER 15 INTERFAC ING WIT H EXTERN AL MEMORY The mi crocontroller ca n interfac e w ith a va riety of ext ernal m emory devices. It suppor t s e i t her a fixed 8-bit data bus width, a fixed 16-bit data bus width, or a dynamic 8-bit/16-bit data bus width; internal control of wa i t states fo r slow exte rnal me mory device s; a n d several ...
8XC196MC, MD, MH USER’S MANUAL 15 -2 ALE P5. 0 O Addre ss L atch En able This active -high output sig nal is asserted o nly durin g extern a l mem ory cycles. ALE signa ls the start of an exte rn al b u s cycle a n d indica tes th at v alid address inf ormation is availabl e o n the system address/data bus. ALE differs fro m ADV# i n t hat i t do ...
15 -3 INTERFACING WITH EXTERNAL MEM ORY EA# — I Extern al Access This i n p ut de ter m i n es wheth er memor y access es to special-purp ose and pro gra m mem ory par titi on s are dire ct ed to i n te rna l or extern a l memory . (See T abl e 4-1 o n p age 4-2 for address ra nges of speci al- purpo se a n d prog ram me mory p arti tions.) These ...
8XC196MC, MD, MH USER’S MANUAL 15 -4 WRH# P5.5 O Wr ite Hig h † Duri ng 16-bit bus cycles, this active-lo w outpu t signal is asserte d for high -byte writ es and wo rd wr i t es to e xternal m emor y . Durin g 8-b it bus cycles, WRH# is as s erte d f o r a l l write op er ati o ns. † The chip config uratio n registe r 0 (CCR0) d eterm ines w ...
15 -5 INTERFACING WITH EXTERNAL MEM ORY 15.2 CHI P CONFIGURAT IO N REG ISTERS AND CHIP CONF IGURATI ON BY TES T w o chi p configuration re gisters (CC Rs) have bi ts that set param eters for c h i p operati o n a nd ex- ternal bus cycles. The CCR s cannot be access ed by code. They are l oaded from the chip config - uration bytes (CCBs ) , which re ...
8XC196MC, MD, MH USER’S MANUAL 15 -6 When the m icrocontroll er retu rns from reset, the bus controll er fetche s the CCBs a nd loads them into the CCRs . From this point, thes e CCR bit val ues defi ne the chip confi guratio n until the mi- crocontrol l e r is rese t again. T he CCR bi ts ar e desc ribed in Fi gures 15 -1 and 1 5-2. (R efer to C ...
15 -7 INTERFACING WITH EXTERNAL MEM ORY CCR0 no direct ac c e ss† The chip config ura tion 0 ( CCR0) registe r contro ls power do wn m o de , b us-con tro l sig nals, an d i nt ern al mem ory prot ection . Three o f its bi ts comb in e wi th two b its of CCR1 to contro l wait s tates an d bu s wid th. 7 0 LOC1 LOC0 IRC1 IR C0 ALE WR BW0 PD Bit Nu ...
8XC196MC, MD, MH USER’S MANUAL 15 -8 3 AL E Addre s s V alid Strob e a n d Write Stro be The se b its defi ne which bu s-con tro l si gnal s will be g ener ate d du rin g ext ernal read and write cy c l es. ALE W R 0 0 a ddress valid with write strobe mode (AD V#, RD#, WRL # , WR H#) 0 1 add ress valid strobe mode (AD V#, RD#, WR# , BHE# ) 1 0 wr ...
15 -9 INTERFACING WITH EXTERNAL MEM ORY CCR1 no direct access † The chip con fi gurati on 1 (CCR1) re gister e n a b l es the wat chdog ti mer a nd sele cts the b us timin g mod e. T wo o f its bit s combi ne with three bits of CCR0 to control wait states and bus widt h. 7 0 1 1 0 1 WDE BW 1 IRC2 0 Bit Num b e r Bit Mn em on ic Fu nction 7:6 1 T ...
8XC196MC, MD, MH USER’S MANUAL 15 -10 15.3 BUS WIDT H AND MULT IPL EXI NG The exte rnal b us ca n operat e a s eit her a 16-bit mul tiplexed addres s/da ta b u s o r as a mul tiple xed 16-bit address/8-bit data bus ( Fig ure 15-3). 1 IRC2 Ready Co n t r ol This bi t, along with IRC0 (CCR0 . 4 ), IRC1 (CCR 0.5), an d the READY pin d ete rm ine t h ...
15-11 INTERFACING WITH EXTERNAL MEM ORY Figure 15-3. Multipl exing and Bus Width Options After reset, but befo r e the CCB fet ch, the m icrocont r oller i s configure d for 8-bit bus mode, re- gardless of the BUSWIDTH inp u t. The up p er address lines (AD15:8) are weakly drive n thr o ugh- out the CC B0 and CCB 1 bus cycles . T o prevent b us c o ...
8XC196MC, MD, MH USER’S MANUAL 15 -12 Figure 15-4. BUSWI D TH T i ming Diagram (8XC196MC, MD) Figure 15-5. BUSWIDTH Ti m ing Di agram ( 8XC196MH) AD15:0 XTAL1 BUSWIDTH ALE CLKOUT † T AVGV T CLGX (min) Valid A3162-01 Address Out Data In † The CLKOUT pin is available only on the 8XC196MC, MD. T XTAL1 XTAL1 T XTAL1 BUSWIDTH Address Out AD15:0 ...
15-13 INTERFACING WITH EXTERNAL MEM ORY . The B USWIDTH sig n a l can be used i n numer o us applications. For e x a mple, a syst em could st o re code in a 16-bit memo ry device and data in an 8-bit me mory de vice. The BUSWIDT H si gnal could be tied to the chip-select inp ut of t he 8 -bi t m emory device (shown in Figure 15-13 on page 15-24). W ...
8XC196MC, MD, MH USER’S MANUAL 15 -14 15.3.2 16-bit Bu s Timings When the microc ontroller is configured to operat e in the 16 - bi t bus-width mo de, l ines AD15 :0 fo rm a 16-b it mult ip l exed add r e ss / data bus. Figure 15 -6 s h o ws an ide a liz ed timing dia gram for the external read a nd write c ycles. Comprehe nsive timing spec ifica ...
15-15 INTERFACING WITH EXTERNAL MEM ORY Figure 15 -6. Timings for 1 6 - bit Buses XTAL1 CLKOUT † ALE BUSWIDTH AD15:0 (read) RD# INST AD15:0 (write) WR# Address Out Data Out Data In Address Out Valid Valid A3163-01 † The CLKOUT pin is available only on the 8XC196MC, MD. ...
8XC196MC, MD, MH USER’S MANUAL 15 -16 15.3.3 8-bit Bu s Timings When the microc ontroller i s configured to opera t e in t h e 8-bit bus mode, l ines AD7:0 form a m ul- tiplexed lowe r address and data bus. Lines AD15:8 are not mult ip lexed; the upper a ddress is latched and rema ins valid throughout th e b us cycle. F igure 15-7 shows a n idea ...
15-17 INTERFACING WITH EXTERNAL MEM ORY Figure 15-7. T imin gs for 8-bit Buses 15.4 W AIT ST A TES (R EADY CONTR OL ) An externa l device c a n use the READ Y input to lengthe n an exte rnal bus cycl e. When an external address is placed o n the bus, the external devic e can pull the READY si gnal low to indica te it is not ready . In re sponse, th ...
8XC196MC, MD, MH USER’S MANUAL 15 -18 After t he CCB1 fe tch, th e intern al ready cont rol c ircuitry allows slow e xterna l me mory device s to increase the lengt h of the read and wri t e bus cycles. If the external me mory device is not ready for access, it pulls the RE ADY sig nal low a nd holds it low until i t i s ready to com plete the op ...
15-19 INTERFACING WITH EXTERNAL MEM ORY Figure 1 5 -8. READY Timing Diagr a m — One W ait Stat e (8XC196MC, MD) T AVYV T CLYX (max) T CLYX (min) Address Out Data Out Address Out Data Address AD15:0 (write) WR# AD15:0 (read) RD# READY ALE CLKOUT † A3165-01 † The CLKOUT pin is available only on the 8XC196MC, MD. ...
8XC196MC, MD, MH USER’S MANUAL 15 -20 Figure 15-9. R EADY T iming Diagram — One W ai t State (8XC196 M H ) T a ble 15-5. READ Y Signal Tim ing Defi niti o n s Symb ol De finitio n T AV YV Addr e ss V a lid to R EA DY Se tu p Maxi m um tim e the externa l device h as to dea s sert READ Y after th e mi c r ocon tr oller o ut put s the a d dres s ...
15-21 INTERFACING WITH EXTERNAL MEM ORY 15.5 BUS-CON TROL M ODES The ALE and WR bi ts ( CCR 0.3 an d CCR0.2) define which bus-control signals wi l l be generated durin g external read and write c ycles. T a ble 15-6 lists the f our bus-c ontrol modes and shows the CCR0.3 and CCR0. 2 settings for each. . T LLY X †† READY Ho ld afte r ALE L ow Mi ...
8XC196MC, MD, MH USER’S MANUAL 15 -22 15.5.1 Standa rd Bus-contro l Mod e In the s t anda rd bus-control m o de , the microc ontroll er genera tes the sta ndard bus-c on tr o l signal s: ALE, RD#, WR #, an d BHE# (see Figure 15- 10). ALE is asserted while the addre ss is driven, and it can b e used to latch the address e x t ernally . RD# is asse ...
15-23 INTERFACING WITH EXTERNAL MEM ORY Figure 15- 12 shows an 8-bit system with both flash and RAM . T h e f la sh is the lower half of mem- ory , an d the RAM is t he uppe r half. This syst em config uration uses the most-signifi ca nt addres s bit (A D15) a s the c hip-select si gnal and ALE a s the a ddress-l a tch signal. Fig ure 15-12. 8- bit ...
8XC196MC, MD, MH USER’S MANUAL 15 -24 Figure 15-13 shows a s yste m t hat uses the dynamic bus-width feature. (The C C R b it s, B W 0 and BW1, are set.) Code is exe cuted from the two E PROMs and data is stored in the byte -wide RAM. The RAM i s in hi g h me mory . It i s selected by driving AD15 high, which a lso se lects the 8-bit bus-width mo ...
15-25 INTERFACING WITH EXTERNAL MEM ORY 15.5.2 Write Strobe M od e The writ e s trobe m ode e limi nat es the nee d to e xte rnally deco de hi gh- an d low-byte writes to a n external 16-bit R AM or fla sh device in 16-bit bus mode. W hen the write strobe mode i s sele c te d , the micr o controll er generates WR L# and W RH # inste ad o f WR # and ...
8XC196MC, MD, MH USER’S MANUAL 15 -26 Figure 15- 15 shows a 16-bit syste m with two EPROM s and two R AMs. It is config u re d to use the write strobe m ode. ALE latches the address; AD 15 is the chi p-select signa l for t he me mory devices . W RL# i s a s serted duri n g l ow byte wri t e s and wo r d writes. WRH# i s asserted during high byte ...
15-27 INTERFACING WITH EXTERNAL MEM ORY 15.5.3 Address V al id Stro be Mode When the addres s valid st r obe m ode is s elec ted, the mi crocont roller gene rat es the a ddre ss va lid signal ( AD V#) inst e ad of the addre ss latch e nable signal (AL E). ADV# i s asserted a fter a n ext er- nal ad dress is val id (see Figure 15 - 16). This signal ...
8XC196MC, MD, MH USER’S MANUAL 15 -28 Figure 15- 18 a n d F igure 15- 1 9 show sa mple circui ts that u s e t he addres s valid strobe mode. Fig- ure 15-18 shows a s i mple 8-bit system wi th a single flash. It is c onfigured for the address valid strobe mode. This syst e m configurat ion uses the ADV# signal as b oth the f lash chip-s e lect sig ...
15-29 INTERFACING WITH EXTERNAL MEM ORY Figure 15-19 s h ows a 1 6 -bi t syste m with two EP ROMs. T his syst em confi g ura t io n uses the ADV# signal as both the EPROM chi p -select signal and the ad d ress-latch signal . Figure 15-19. 16- b it System with EPROM A3095-01 V CC AD7:0 AD15:8 RD# ADV# 74AC 373 74AC 373 A13:7 A13:7 D15:8 D7:0 A ...
8XC196MC, MD, MH USER’S MANUAL 15 -30 15.5.4 Address V al id with Write Strob e Mode When the a ddress vali d with write s t robe mode is sel e cte d, the mic ro controll er generat es the ADV#, RD#, WRL #, a n d WRH# bus-contr ol s ignal s. This mo de i s used for a simpl e system us- ing an ext ernal 16-bit d ata bus. Figure 15-20 sh ows th e t ...
15-31 INTERFACING WITH EXTERNAL MEM ORY Figure 15- 2 1. 16-bit System with RAM 15 . 6 SYSTEM BUS A C T IMING S PECIFI CATIONS Refer to the lates t datas h eet fo r the AC t i mings to make sure your system meets specific a t ions. The ma jor exte rnal bus t iming s pecificat ions are shown in Fi g ure 15- 22 . AD7:0 AD15:8 WRL# ADV# 74AC 373 74A ...
8XC196MC, MD, MH USER’S MANUAL 15 -32 Figure 15 -22. System Bus Timing XTAL1 CLKOUT † ALE/ADV# RD# WR# BHE#, INST T XTAL1 T XHCH T CHCL T CLCL T CLLH T LLCH T LHLH T LHLL T LLRL T RLRH T RHLH T RHDZ T AVLL T LLAX T RLDV Address Out Data In T AVDV T LLWL T WLWH T WHLH T QVWH T WHQX Data Out Address Out Address Out Valid Address Out T WHBX , T RH ...
15-33 INTERFACING WITH EXTERNAL MEM ORY 15.6.1 Expl anation of AC S ymbo ls Each s ymbol consis ts of t wo pai rs of letters prefixe d by “T” (for time). The cha rac ters i n a pai r indicat e a signal and its condit ion, re spectivel y . Symbols repre sent the t ime bet ween the t wo sig- nal/condition points. For e xample, T LL RL i s th e ti ...
8XC196MC, MD, MH USER’S MANUAL 15 -34 T a b l e 15-9. Mi crocontroller Meets Th e se Specif icatio n s Symb ol Defin ition T AV LL Add ress Setup to A LE / ADV# Low Le ng th of t im e a d dr ess is valid b e fore ALE/ ADV# falls. Usefu l when using a n e xter nal latch to de multipl ex th e addre s s from the add ress data bus . T C HCL † C LKO ...
15-35 INTERFACING WITH EXTERNAL MEM ORY T WHA X Address (high byte) Hold a fter WR# High Mi ni mum time the high byte o f th e addre s s ( whe n u sin g a n 8-bit da ta bus) is val id af ter the mi crocon trolle r deasse rts WR# . T WH B X BH E#, INS T Hold af ter WR# High Mi nimu m tim e th ese signal s are val id af ter the m icro con trolle r d ...
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16 Pr ogra mming the Nonvolatil e Memory ...
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16 -1 CHAPTER 16 PROG RAM MI NG THE NONVO L AT ILE ME MO RY The 87C 1 96MC and 87C196M D contain 16 Kbyte s of one-time-programmable re ad - onl y mem- ory (OTP ROM ); the 87C1 96MH c ontains 32 Kbytes. OT PROM i s s imi lar to EPR OM, but i t comes i n a n unwin d owed pac kage and cannot be erase d. Y ou can eithe r p rogram t he OT PR OM yoursel ...
8XC196MC, MD, MH USER’S MANUAL 16 -2 mode, you can program and verify single or multip le words in the OTPROM. This m o de allows y o u t o re ad t h e s i gnatu r e word and program ming voltages and to program the PCCBs and unera sabl e PROM (UPR OM ) bits. Pr o grammi ng vendors a nd Intel distributor s typica l l y use t his mode to progr am ...
16 -3 PRO GRAMMING THE NONVOLATILE MEM ORY 16.3 S ECURITY F EATURES Several security features enable you t o control access to both internal and external memory . Read and write pr o tection bit s in the chip configurat ion register ( CCR0), combined with a securit y key , allow vari ous level s of inte rnal mem ory protection. T w o UPROM bits di ...
8XC196MC, MD, MH USER’S MANUAL 16 -4 16.3.1.1 Contr o l l ing Acces s to th e OTPROM Dur ing Normal Operation Du r ing norm al operat ion, the loc k bits in CCB0 cont r ol rea d and write ac c esse s to the OTP ROM. T abl e 1 6 -2 descri bes t he options. Y ou c an program the CCBs using any of the prog ra mming methods. Clearing C CB0. 6 e nable ...
16 -5 PRO GRAMMING THE NONVOLATILE MEM ORY These p r otectio n leve ls are provided by the PCC B0 lock bits, the CC B0 lock bits, an d the internal securit y key (T abl e 16-3). When entering programming modes, the rese t s eq u ence l oads the PCCB s into t he chi p confi guratio n regi s ters. It a lso loa ds CCB0 in to in t e rnal RAM to provide ...
8XC196MC, MD, MH USER’S MANUAL 16 -6 Y ou can prog ram th e in t ernal secu r i ty key in either aut o or slave prog ramm ing mode. Onc e the securit y key is prog ramm ed, y ou must provide a matchi ng key to gai n access to any prog ramming mode. For auto programm ing and ROM-dump modes , a ma tc h ing secu r ity key must reside in ex- ternal m ...
16 -7 PRO GRAMMING THE NONVOLATILE MEM ORY Y ou can verify a UPRO M b i t to ma ke sure it p rogram med, but you cannot erase it. For this reas on, Intel cannot test the bits before shipment. Howe ver , Intel does test t he fea tures that the UPR OM bits enabl e, so the o n ly undetec t able defects are ( unlikely) defec ts within the UPROM c ells ...
8XC196MC, MD, MH USER’S MANUAL 16 -8 16.4 P ROG RAMMI NG P ULSE WIDTH The programming p u l se w idth is controlled in dif ferent ways, dependi n g o n t he prog ramming mode. In slave programming mode, the pulse width is c ontrolle d b y the P AL E# signal . In a uto programmin g mode, it is loaded from the external EPR OM into the PPW regi s te ...
16 -9 PRO GRAMMING THE NONVOLATILE MEM ORY 16.5 M ODIFIE D QUIC K-PULS E ALGORI THM Both the slave and auto progr a mming routin e s use the modified quick -p ulse a lgorithm (Fig u re 16-3) . The modi f ied quick-pulse algorithm se n ds p ro gra m ming pulses t o each OTPROM word location. Afte r the required number o f programmin g p u l ses, a v ...
8XC196MC, MD, MH USER’S MANUAL 16 -10 Figur e 16-3. Modi fi ed Quick-pulse Algori thm Auto prog ra mm ing repeats the p u lse twice (for the 87C196MC, MD) o r fi ve times (for the 87C196MH ), us ing t he pulse w idth you s peci fy in the externa l EPROM . Slave mode repea ts the pulse unti l PROG# is deasserted. In sl ave prog ramm ing mode , the ...
16-11 PRO GRAMMING THE NONVOLATILE MEM ORY 16.6 P R OG R AM MING M ODE PINS Figure 16-4 illustrates the signals used in programming and T able 16-6 de scri bes them. The EA#, V PP , and PMODE pins combine t o control entry into programm ing modes . Y ou m u s t co n figure the PMODE (P0.7:4) pins to se l e c t t he desired programmi n g mode (se e ...
8XC196MC, MD, MH USER’S MANUAL 16 -12 P2.2 PROG# I Sl ave Progr amming Duri n g p rogramm ing, a falli n g ed g e l atches data o n t h e P BUS an d be gins prog ram m ing, whi le a r isi n g edge e n ds pro g r a mmi n g . The current lo c ation is progra mmed wit h the same dat a as lon g as P ROG# remains as serte d, so th e data on th e PBUS ...
16-13 PRO GRAMMING THE NONVOLATILE MEM ORY 16.7 E NT ERING PROG RAMM I NG MODE S T o execute programs p roperl y , the devic e must have thes e m i nimum hardware c onnections: XT A L1 dr iven, u nu sed input pins strapped, an d power and grounds applied. Follow the operating conditions spec ified i n the datas heet. Place the de vice into programm ...
8XC196MC, MD, MH USER’S MANUAL 16 -14 16.7.2 Powe r-up an d Power-dow n Sequ ence s When you are ready t o be g in pr o gra mming, foll ow these power-up and power -down procedures. W ARNING Fail ure to observe these warnings will cause permane nt devic e damage. • V olt age must no t be applied t o V PP whi l e V CC is low . • The V PP volt ...
16-15 PRO GRAMMING THE NONVOLATILE MEM ORY 16.8 SLA VE PRO GRAM M ING M ODE Sl ave prog ramm ing mode allows you t o program and verify th e entire OTPROM array , including the PCC Bs and UPR OM bits, by usin g an EPR OM programmer . In this mode, ports 3 and 4 serve as t he PB US, transferri ng comma nds, a d dresse s, and data. The leas t-si gn i ...
8XC196MC, MD, MH USER’S MANUAL 16 -16 16.8.2 Slave Pro gram mi ng Circu it an d Mem o ry Ma p Figure 16- 5 shows the circuit diagram an d T abl e 16-9 shows the m emory map f o r slave p ro gra m- min g mode. The external cloc k signal can be supplied by eithe r a clock or a c rystal. Refe r to the device datashe e t for a ccept able cloc k frequ ...
16-17 PRO GRAMMING THE NONVOLATILE MEM ORY 16.8.3 Operati ng Envi ro nm en t The chip c onfi g ura tio n re gisters (C CR s) define the sys t e m envi ronment. Si n ce t he programming environment is not necessarily the same as t h e applicatio n environment, the de vice provides a means for spe cifying dif ferent configurat ions. Spe cify your app ...
8XC196MC, MD, MH USER’S MANUAL 16 -18 CCR1, CCR0 no d irect a cce ss The chip conf igura tio n registe rs (CC Rs ) control wait st ates, powe rdown mo de, an d i ntern al m emor y protecti o n. T hese regi sters are loaded fro m the P CCBs durin g pro gramming modes a n d fr om the CCBs for norm al opera ti on . 7 0 1 1 0 1 WDE BW1 IR C2 0 7 0 LO ...
16-19 PRO GRAMMING THE NONVOLATILE MEM ORY 16.8.4 Slave Pro gramm ing Routi nes The sla ve pr ogrammi ng mode algorithm c onsists of three ro ut ines: the address/co mmand decod- ing routine, the program word rou tine, and t he dump word rou tin e. The ad d re ss / command dec oding rout ine (Fig ur e 1 6 - 7) reads the PBUS an d transfe r s contro ...
8XC196MC, MD, MH USER’S MANUAL 16 -20 Figure 16 -7. Addre ss/Command Deco ding Routi ne Yes No Other Modes A0193-02 PMODE = 05H ? PALE# (P2.1) = 0 ? Yes PVER (P2.0) = 1 ? Yes Read Data From PBUS No PALE# (P2.1)= 0 ? Check Address P3.0 = 1 ? Yes Program Word Routine No Dump Word Routine No No Deassert CPVER A ...
16-21 PRO GRAMMING THE NONVOLATILE MEM ORY Figure 16- 8 . Progr am Word Rout ine A0194-03 No PROG# (P2.2)=0 ? From Address/ Command Decoder Read Data from PBUS No Lock Bits Enabled ? Yes Verify Security Key Keys Match ? Yes Programming Verifies ? Yes No Loop Forever No Deassert PVER (P2.0 = 0) PROG# (P2.2) ...
8XC196MC, MD, MH USER’S MANUAL 16 -22 Figure 16- 9 shows the t i m ings of the program w o rd com m a nd wi th a repeated progr amm ing pulse and auto incre ment. Ass erting P ALE# l atches the c omm and and address on t he PB US. Assert ing PROG# l atc hes the data on the PB US and starts t he pr ogrammi n g sequence . The PROG# signal controls ...
16-23 PRO GRAMMING THE NONVOLATILE MEM ORY Figure 16-10. Dump Word Routine A0189-03 Yes Lock Bits Enabled ? No PROG# (P2.2) = 0 ? Yes Get Data from OPTROM Yes PROG# (P2.2) = 1 ? PALE# (P2.1) = 0 ? Yes No No Increment Address by 2 AINC# (P2.4) = 0 ? No Yes To Address/ Command Decoder From Address/ Command De ...
8XC196MC, MD, MH USER’S MANUAL 16 -24 Figure 16- 1 1 shows th e timings of the dump w or d com mand. P ROG# governs when the device drives the bus. T he timi ngs bef o re the dump word co mmand are the same as those sho wn in F ig- ure 16-9 . In the dump word mode, the AINC # pin can rema in active and toggli ng. The P RO G# pin automa tically i ...
16-25 PRO GRAMMING THE NONVOLATILE MEM ORY 16.9 AUT O PROGRAMMING MODE The auto program ming mode is a low-cost prog ramming a lte rnative . Using thi s prog ramming mode, the device program s i tse lf with da ta from an e xterna l EPROM (ext ernal locations 4000H and above; se e T able 16 -1 on page 1 6-3). A bank switc hing me chani sm provided b ...
8XC196MC, MD, MH USER’S MANUAL 16 -26 Figure 16-12. Auto Programming Circuit 270k Ω +5.0V XTAL1 20 pF 20 pF XTAL2 P2.7/PACT# P2.5 P2.4 P2.3 P2.2 P2.1 P2.0/PVER RESET# +12.50V 100 k Ω 1 k Ω 10µF 74HC14 1.0µF Reset EA# V PP V REF P0.7/ PMODE.3 P0.6/ PMODE.2 P0.5/ PMODE.1 P0.4/ PMODE.0 ANGND READY/P5.6 NMI BUSWIDTH/P5 ...
16-27 PRO GRAMMING THE NONVOLATILE MEM ORY 16.9.2 Operati ng Envi ro nm en t In the au to prog r amm ing mode, the PC C Bs are loa ded into the chip confi guration regist e rs. Since the device gets progr amm ing da ta through the ext ernal bus, the me mory devi ce i n the program- min g system must correspond to the default configuratio n (Figure ...
8XC196MC, MD, MH USER’S MANUAL 16 -28 Fig ure 16-13. Aut o Programmi ng Routine No Other Modes Loop Forever A0191-03 PMODE = 0CH ? No Lock Bits Enabled ? Load PPW Yes No Pass ? Yes Verify Security Key Assert PACT# Get External Data No Yes Data = 0FFFFH ? Execute Modified Quick-Pulse Algorithm then Return Yes Top of? ...
16-29 PRO GRAMMING THE NONVOLATILE MEM ORY If the s ecurit y key verific a ti on is successful , the routine loads the progra mming p u l se width (PPW) va lue from the external EPROM into the interna l PPW re gister . It then ass erts P ACT#, in- dicating that programming has begun. (P A CT# is also active during reset, alth ough no program- ming ...
8XC196MC, MD, MH USER’S MANUAL 16 -30 2. Using anothe r blan k EPROM devic e, follow thes e ste ps to progra m only CCB 0. — Place the programmin g pu lse w idth (PP W) in ext ernal locati ons 14H–15 H . — Pl ace the appro priate C C B0 va lue in external loca tio n 40 18H. — Place the securit y key to b e verified in e x te r na l EPR OM ...
16-31 PRO GRAMMING THE NONVOLATILE MEM ORY Figure 1 6-14 shows the rec ommended c ircuit for PCC B and UPROM progr amm ing. I n these cir - cuits, the PBUS hol ds data to be w r i tten to the OTPR OM, P AL E# begins programming, and PVER drives an LED tha t lights to indicat e success f ul programm ing. Figure 16-14. PCCB and UPROM P r ogramming Ci ...
8XC196MC, MD, MH USER’S MANUAL 16 -32 Assert P A LE# to begi n prog ramm ing. The alg o ri thm sends five progra mming pulses that wri t e the port 3 d ata to t h e OT P ROM , then it compares t h e in p ut data wi th the programmed data. If the programmin g verifi es, the PVER sig n al lig h ts the LE D to indicat e succe ssful programming. O th ...
16-33 PRO GRAMMING THE NONVOLATILE MEM ORY The calli ng routi ne must pass tw o para mete rs t o this routine — the dat a to be prog rammed ( in DA T A _T EMP) and the ad dress (in ADDR_T EMP). Figure 16-15. Run-time Pr og ramming Code Example PROGRAM: PUSHA ;clear PSW, WSR, INT_MASK, INT_MASK1 LD WSR,#7BH ;select 32-byte window wi th EPA0_CON LD ...
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A Instruction Set Re fer enc e ...
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A- 1 APPENDI X A INST RUCT ION SET REF ERENCE This appe n dix p r ovi des referenc e i nforma t ion for the instructi o n s et of the family o f MCS ® 96 microcont r ol l er s. It defines the processor status word (PSW) flags, des cribes each instruc t i on, shows the relatio n ships bet ween inst r uc tions an d P SW flags, and shows hexade cimal ...
8XC196MC, MD, MH USER’S MANUAL A-2 T able A -1. Opcode Map ( L eft Half) Opco de x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 0 x SKIP CLR NOT NEG X CH di DEC EXT IN C 1 x CLRB NOTB NEGB XC HB di DECB EXTB INCB 2 x SJMP 3 x JBC b i t 0 b i t 1b i t 2b i t 3b i t 4 b i t 5 b i t 6b i t 7 4 x AND 3op AD D 3op di im in ix di im i n ix 5 x AN DB 3op ADDB 3op di i ...
A- 3 INSTRUCTION SET REFERENCE T able A-1. O pcode M ap (Right Half) Opco de x 8 x 9 x A x B x C x D x E x F 0 x SHR SHL SHRA XCH ix SHRL SHLL SHRAL NORML 1x SHRB SHLB SHRAB X CHB ix 2 x SCAL L 3 x JBS b i t 0 b i t 1b i t 2b i t 3b i t 4 b i t 5 b i t 6b i t 7 4 x SUB 3o p MU L U 3o p (N ote 2) di im in ix di im i n ix 5 x SU BB 3 o p MULUB 3o p ( ...
8XC196MC, MD, MH USER’S MANUAL A-4 T able A-2. Processor S t atus Word (PSW) Flags Mne moni c Desc ription C The carry f lag is set t o i nd icat e a n arith metic carr y fr o m th e M SB of the ALU or th e state of t h e la st bit shift ed ou t of a n op erand . If a subtracti on op era tion ge nerate s a b orro w , th e carry fl ag is c lear ed ...
A- 5 INSTRUCTION SET REFERENCE T abl e A-3 sh o ws the effect of the PSW flags or a spec i fied condit ion o n condi t io n al jump instr u c- tions. T able A-4 define s t he symbol s used in T able A-6 to show th e effect of e ach instruc tion on the PSW flags. . T able A- 3. Effect of PSW Flags or Specified Conditi o ns on Condit ional Jump Instr ...
8XC196MC, MD, MH USER’S MANUAL A-6 T abl e A-5 defines the vari abl es that are used in T able A-6 t o repre se nt t he inst r uction opera n ds. T able A-5. Operand V ariables V aria bl e Descri ption aa A 2-b it fie l d withi n an opco de th at se l e cts the basic a ddre ssing mo de use d. Thi s fie ld is pr esen t only in those opcod es th at ...
A- 7 INSTRUCTION SET REFERENCE T able A- 6. Inst ruction Set Mne monic Operati on Instruc tion Forma t ADD (2 ope ran ds) ADD WORDS. Adds the source a n d destin atio n word oper a n ds a n d store s the sum i nto th e de stin ati on o pe rand. (DEST) ← (DEST ) + (SRC) D EST , SRC A DD w reg, wa op (0 1 100 1aa) (w aop) (w reg) P SW Fla g Settin ...
8XC196MC, MD, MH USER’S MANUAL A-8 A DDCB ADD BY TES WITH CA RRY . A dds the sou rce and de stinat i o n b y te op e rands a n d the carry f lag (0 o r 1 ) a nd st ores th e s um in to the destin atio n ope rand. (DEST) ← (DEST ) + (SRC) + C D EST , SRC A DD CB bre g, ba op ( 1 01 1 01aa ) (bao p) (bre g) P SW Fla g Settin gs ZN CV V T S T ↓ ...
A- 9 INSTRUCTION SET REFERENCE AND B (3 ope ran ds) L O GI CAL AND BYTES . ANDs the two sou rce byte o perands a nd sto res the result in to the destin atio n ope rand. T he resu lt h as o nes in only t he bi t posi ti o ns in wh ich bo th oper ands had a “1” and zeros in all othe r bit positio ns . (DEST) ← (SRC1) AND (SRC2) D EST , SRC1, SR ...
8XC196MC, MD, MH USER’S MANUAL A-10 B MOVI INT ERRUPTIBLE B LOCK MOV E. Mo v es a block of word data fro m o n e l ocat ion in memo r y to a n oth e r . The instructio n is identi cal t o BMOV , excep t that BMOVI is inte rrup ti ble. The source an d d esti natio n add resses are calcul ated usin g the in d irect wit h autoi ncreme n t addr essin ...
A-11 INSTRUCTION SET REFERENCE CL RB CL EAR B YTE. Cle ars t he val u e of the ope ran d. (DEST) ← 0 DE S T CL RB bre g (0 0010 001) (br e g) P SW Fla g Settin gs ZN CV V T S T 1000 — — CLRC CLEAR CA RR Y FLA G. Clear s th e carry fla g . C ← 0C L R C ( 1111 1 0 0 0 ) P SW Fla g Settin gs ZN CV V T S T —— 0 — —— CLRV T CL EAR OVER ...
8XC196MC, MD, MH USER’S MANUAL A-12 CMPL COMP ARE LONG. Compare s th e mag ni tu des of two doub le -word (lon g) ope rands. T h e ope rands a re specif ied u sing the direct add re ssin g mode . The flags are a ltered , b ut th e opera nd s rem a in un affe cted . If a borrow occurs, the carry flag i s cl ea red; otherwise , it is se t. (DEST) ? ...
A-13 INSTRUCTION SET REFERENCE DIV DIV IDE INTEGERS . Divide s the con t ents of th e de st ina ti on long-i nte ger op er a nd b y th e con t e nts o f the so urce integ er wo r d op er and , usi n g s igned ar ithm et ic. It sto res th e q u o t i e n t into the low -ord er word o f the dest in ati on (i .e., the word wi th the lowe r addre ss) a ...
8XC196MC, MD, MH USER’S MANUAL A-14 DIV UB DIV IDE BYTES, UNSIGNED. Thi s instru ction divid es th e cont e nts of the desti nation word ope rand by the cont ent s o f t h e source byt e ope rand, using unsign e d arith meti c. It store s t he q uot ie nt into th e l ow- ord er by te (i. e. , th e byte wi th the lowe r address) o f the destin at ...
A-15 INSTRUCTION SET REFERENCE DPTS DIS ABLE PER IPHERAL TRANSAC TION SERVER (PTS). Di sab les the p e riph eral transa ction ser ver (PTS). PTS Di sable (PSW.2) ← 0 DPTS (1 1 1 01 100 ) P SW Fla g Settin gs ZN CV V T S T ———— —— E I ENA BLE INTE RRUPTS. Enabl es in te rrup ts followi n g the e xecution of t h e next sta tement . Inte ...
8XC196MC, MD, MH USER’S MANUAL A-16 EXTB SIGN- EXTE ND SHORT -INT EGER INTO INTEGER. Sig n-exten ds the low-o rde r byte of the operan d throu ghout the high-o rder byte o f th e ope ra nd. if DE ST .7 = 1 then (hig h byte DEST) ← 0FFH else (hig h byte DEST) ← 0 en d_ if EXTB w reg ( 0 0 0101 10) (wre g) P SW Fla g Settin gs ZN CV V T S T ✓ ...
A-17 INSTRUCTION SET REFERENCE IN CB INCREME NT BYTE. Increm e n ts the va l u e o f the byte op eran d by 1. (DEST) ← (DEST ) + 1 INCB b r e g (0 0010 1 1 1) (br eg) P SW Fla g Settin gs ZN CV V T S T ✓✓✓✓ ↑ — JBC JUMP IF BIT IS CLEAR. T es ts the spe cified bit. If the bit is set, control pa sses to the next seq u e ntial instru c t ...
8XC196MC, MD, MH USER’S MANUAL A-18 JC JUMP I F CARRY FL AG I S SET . T e sts the carry fla g. If the carry flag i s clear , con trol pa sses to the n ext se q uenti al in s tructi o n. If the c arry fl ag is set , t his i nstructio n a dds to the progra m cou nter t he offset betwe en th e end of th is instructi on a nd th e targ et la bel, effe ...
A-19 INSTRUCTION SET REFERENCE JGT JUMP IF SIGNE D GREA TER THAN. T ests b oth the ze ro fla g an d the neg ati ve f la g. If eith er flag is set, control pas ses to th e next seq u ential instru ction. I f bot h fla gs are cle ar , this instru ct ion adds to the progra m counte r the offset be twe en the e nd of this instru ctio n and th e targ et ...
8XC196MC, MD, MH USER’S MANUAL A-20 JL T JUMP IF SIGNED LE SS THAN. T ests th e neg ati ve fl ag . If t he flag is c lear, co ntrol pa sses to the n ext se q uenti al in s tructi o n. If the n e g a tive f l a g is set , this i nstru c tion add s t o th e pro gram co unt er t he of fs et bet wee n t he end of th is instructi on a nd th e targ et ...
A-21 INSTRUCTION SET REFERENCE JNH JUMP IF NOT H IGHER (UNSIGNED). T ests both the zero f lag and the carry f la g. If the carry f l ag is s et and th e zero f l ag is clear , con tr ol passes to th e ne x t seq u ential instructi on. If either the carr y fl a g is clea r o r the zero flag is set, this instruct i on adds to the prog ram coun ter th ...
8XC196MC, MD, MH USER’S MANUAL A-22 JNVT JUMP IF OVERF LOW-TRAP FL AG IS CL EAR. T ests the overf low-tra p f la g. If t he flag is set, t his instru ction cl ear s the flag and pa sses con trol to th e ne xt seq ue ntial instructi on. If the over flow-tra p flag i s c lea r , this instru ct ion adds to the progra m counte r the offset be twe en ...
A-23 INSTRUCTION SET REFERENCE JVT JUMP IF OVERF LOW-TRAP FL AG IS SE T . T e sts t he overf l ow-tra p flag. If the flag is clear , con tr ol passes to th e ne x t seq u ential instructi o n . If the o verflow-t rap flag is set, this instructi on cle ars the fla g and a d ds to the prog ram coun ter the offse t b et wee n the e nd of th is i nstru ...
8XC196MC, MD, MH USER’S MANUAL A-24 LDBSE LOAD BYT E SIGN-EXT ENDED. Sign- exte nds th e valu e of t h e sou rce shor t- in teger op eran d a nd l oa ds i t i nto th e destin atio n inte ger op era nd . (low b yte DEST) ← (SRC ) if DEST .15 = 1 then (hig h w ord DEST ) ← 0F FH else (hig h w ord DEST ) ← 0 en d_ if D EST , SRC LD B SE wre g, ...
A-25 INSTRUCTION SET REFERENCE MUL (2 ope ran ds) M UL TIPL Y I NTEGE RS. Mu l t i p l ies t h e sou rce and destin ation i nteg er op e ra nd s, u si ng sig n ed arith m etic, and stores the 3 2-bit re sult in to the de stina ti on long-i nte ger op e ra nd . T he s tic ky bi t f l ag i s unde fin ed af ter th e instructi o n i s execut e d. (DEST ...
8XC196MC, MD, MH USER’S MANUAL A-26 MULU (2 ope ran ds) M UL T IP L Y WORDS, UNSIGNED . M ulti plies the source a nd dest inati on word op e rands, usi n g un signed a rithm etic, a nd sto res th e 32 - bit r esul t into the dest inati o n do uble-wo rd op era nd . Th e s tic ky bit fla g is un defi ne d af ter the instr uctio n is execu ted. (DE ...
A-27 INSTRUCTION SET REFERENCE NEG NEGA TE INTEGER. Negat es t he value of the in teger op eran d. (DEST) ← – ( DEST) NEG w reg ( 0 0 00001 1) (wre g) P SW Fla g Settin gs ZN CV V T S T ✓✓✓✓ ↑ — NEG B NEGA TE SH OR T -INTEGER. Negates t he val ue of th e sh o rt-integer oper a nd . (DEST) ← – ( DEST) NEGB b r e g (0 0010 01 1) ( ...
8XC196MC, MD, MH USER’S MANUAL A-28 NOT COM PLEME NT WORD. Co mplemen ts the val u e of th e wor d opera nd (rep laces each “1” wit h a “0 ” and each “0” with a “1”). (DEST) ← NOT (DE ST) NOT wreg ( 0 0 000010 ) (wreg) P SW Fla g Settin gs ZN CV V T S T ✓✓ 00 — — NOT B COM PLEME NT BYTE. Comp lement s the val u e of the ...
A-29 INSTRUCTION SET REFERENCE PO P POP WORD. Pops the wo rd on top of th e stack a n d place s it a t the de stinatio n ope ran d. (DEST) ← (SP) SP ← SP + 2 POP waop (1 1001 1aa) ( waop) P SW Fla g Settin gs ZN CV V T S T ———— —— P OP A POP ALL . This instr uctio n is used inste ad of POPF , to sup port t h e ei g ht ad di tiona l ...
8XC196MC, MD, MH USER’S MANUAL A-30 P USHA PUS H ALL. This instru ctio n is used inste ad of PUS HF , to sup po rt the e ight ad ditio na l inte rrupts. I t pushe s two wo rds — PSW /INT_MAS K and INT_MASK 1/WSR — o nto th e sta ck. This i nstru ction cle ar s the PSW, I NT_MAS K, and INT_MASK1 re gisters a nd d ecreme nts the SP by 4 . Inter ...
A-31 INSTRUCTION SET REFERENCE RS T RES ET SYSTE M. Initial izes t h e PSW to zero , the PC to 2080H, and the p ins and SFRs to thei r reset va lues. Exe cuting t h is instructi on cau s es th e RE SET# p in to be p u lled l ow for 16 sta te tim es. SF R ← Reset Status Pi n ← Reset St atus PSW ← 0 PC ← 20 8 0H RST ( 1111 1111 ) P SW Fla g S ...
8XC196MC, MD, MH USER’S MANUAL A-32 S HL SHI F T WORD LEF T . Shif ts the d esti na tion w or d ope ran d t o t he l ef t as ma ny ti mes as spe c ified by the c ount o perand . The count may b e specif ied e it her as an im mediat e val u e in t he ran ge of 0 to 15 (0F H), inclu sive, or as t he con tent of any reg ister (10 H – 0FFH) with a ...
A-33 INSTRUCTION SET REFERENCE SHLL SHI F T DOUBLE -WORD LEF T . Shifts the destin at i on d oub le-word o p eran d to the le ft as ma ny tim es as sp ecified b y the cou nt ope rand. Th e coun t may b e specif ied eit her as a n imm edia te v al ue in th e ra ng e of 0 to 15 (0FH), inclusive, or as t he con te nt of a ny re giste r (10 H – 0FFH) ...
8XC196MC, MD, MH USER’S MANUAL A-34 SH RA ARITHMETI C RIGHT SHIF T W ORD. Shifts t he d esti n atio n w or d op eran d t o the ri gh t as many ti m es as spe cified by th e c o unt ope rand. Th e coun t may b e specif ied eit her as a n imm edia te v al ue in th e ra ng e of 0 to 15 (0FH), inclusive, or as t he con te nt of a ny re giste r (10 H ...
A-35 INSTRUCTION SET REFERENCE SH RAL ARI THMETI C RIGHT SHIF T DOUB LE- WORD. Sh ifts the d estina ti o n do u b le-word op era nd to th e r ig h t as man y time s as spe c ified by the c ount o perand . The count may b e specif ied e it her as an im mediat e val u e in t he ran ge of 0 to 15 (0F H), inclu sive, or as t he con tent of any reg iste ...
8XC196MC, MD, MH USER’S MANUAL A-36 SH RL L OGI CAL RIGHT SHIF T DOUBLE-W ORD. Sh ifts the dest i n ati on d o u bl e-word ope ran d to t he r igh t as ma ny ti mes as sp eci fie d b y the cou n t opera nd. The cou nt may b e sp ecified eith er as an im mediat e value i n th e range of 0 to 15 (0 FH) , in clu si ve, o r a s the c on tent of any r ...
A-37 INSTRUCTION SET REFERENCE ST STORE W ORD. S tore s th e va l ue o f the sou r c e (l eftm o s t) wo rd op era nd i nto th e destin atio n ( ri ght most) o p era nd . (DEST) ← (SRC) SRC, DE ST S T w reg, wa op (1 10 000a a) ( wao p) ( wre g) P SW Fla g Settin gs ZN CV V T S T ———— —— S TB STORE BYTE. Sto res t he val ue of t he so ...
8XC196MC, MD, MH USER’S MANUAL A-38 SU BB (2 ope ran ds) SUB TRACT BYT ES. Su b tr a c ts the sou rce byte o peran d fro m the desti natio n byte ope rand, store s the re sul t in the destin ation ope ra n d , and sets the carry flag as the com p leme nt of borro w . (DEST) ← (DEST ) – (SRC) D EST , SRC S UB B b re g, ba op (0 1 1 1 10 aa) (b ...
A-39 INSTRUCTION SET REFERENCE TIJMP T ABLE INDI RECT JUMP . Cau ses executi o n t o c ont inu e at an add r es s sel ect ed f rom a ta bl e of ad dr e ss e s. The first word regist er , TBAS E, contain s the 16 -bi t a ddr ess of th e be gin ni ng of t he jump tabl e. TBA SE can b e loca te d in RA M u p t o FE H without wi n d o wing or a b o ve ...
8XC196MC, MD, MH USER’S MANUAL A-40 XCH EXC HANGE WORD. Excha n ges the va l ue of the source word o p erand wit h that o f the destin at i on wo rd op eran d. (DEST) ↔ (SRC) D EST , SRC X CH w reg, wa op ( 0 0 000100 ) (waop) (wre g) direct (0 0001 01 1) ( wao p) ( wre g) i nd exe d P SW Fla g Settin gs ZN CV V T S T ———— —— XC HB ...
A-41 INSTRUCTION SET REFERENCE T able A- 7 lists the instruction opcodes, in hexadecimal order , along wi th the corresponding i n- structio n mnemonic s. T able A- 7. Inst ructio n Opcod es He x Code I nstruc tion Mnemon ic 00 SKI P 01 CLR 02 NOT 03 NEG 04 XCH Dire ct 05 DEC 06 EXT 07 INC 08 SHR 09 SHL 0A S HRA 0B X CH Inde xe d 0C S HRL 0D S HLL ...
8XC196MC, MD, MH USER’S MANUAL A-42 45 ADD I mme di ate (3 o ps) 46 ADD I ndirect (3 op s) 4 7 A D D In de xe d ( 3 ops) 48 SU B Direct (3 ops) 49 SUB Imme diat e ( 3 o ps ) 4A S UB Indirect (3 op s ) 4B S UB Inde xed (3 ops) 4C M ULU Dir ect (3 o ps) 4 D MULU I mme di at e ( 3 o ps ) 4E MUL U Indirect (3 o ps) 4F MULU I nd exed ( 3 o ps ) 50 AN ...
A-43 INSTRUCTION SET REFERENCE 6E MUL U Indirect (2 o ps) 6F MULU I nd exed ( 2 o ps ) 70 AN DB Direct (2 ops) 71 ANDB Imm e diat e (2 o ps) 72 AN DB Indi rect (2 ops) 73 AN DB Indexed (2 op s) 74 AD DB Direct (2 ops) 75 ADDB Imm e diat e (2 o ps) 76 AD DB Indi rect (2 ops) 77 AD DB Indexed (2 op s) 78 SUBB Di rect (2 ops) 79 SUBB Im med ia te ( 2 ...
8XC196MC, MD, MH USER’S MANUAL A-44 97 X OR B Inde xed 98 CM PB Dire ct 99 CMP B Imm e diat e 9A CM PB In dire ct 9B CM PB In dexe d 9C DI VUB Direct 9D DI VUB Imme d i ate 9E DIVUB I ndirect 9F DI VUB Ind exed A0 LD Direct A1 LD I mme di at e A2 L D In dir ect A3 L D In dex ed A4 A DDC Direct A5 ADD C I mme di ate A6 AD DC Indirect A7 AD DC Inde ...
A-45 INSTRUCTION SET REFERENCE C0 S T Direct C1 BMOV C2 S T I ndirect C3 S T Inde xed C4 S TB Direct C5 CMPL C6 ST B In dir ec t C7 S TB Ind exed C8 P USH Direct C9 PU S H I mme di ate CA PUSH In d irect CB P US H In d exe d CC P OP Dir ect CD B MOVI CE POP I ndirect CF POP I nd exe d D0 JNST D1 JNH D2 JGT D3 JNC D4 JNVT D5 JNV D6 JGE D7 JNE D8 JST ...
8XC196MC, MD, MH USER’S MANUAL A-46 F0 RET F2 P USHF F3 PO PF F4 P USHA F5 PO P A F6 IDL PD F7 TRA P F8 CLR C F9 SE TC FA D I FB E I FC CL R V T FD NOP FE DI V/DIV B/MU L/MU LB (Note 2 ) FF RS T NOTES: 1. This opcod e is reser ved, but it d o es not gene rat e a n unimpl eme nte d opcode i nterru pt. 2. Signe d multipl ication a n d divisio n are ...
A-47 INSTRUCTION SET REFERENCE T able A-8 lists inst ructions along with thei r lengt hs and opc o des for each a pplicable addressing mode. A dash (—) in any column indica tes “n ot a pplica ble.” T able A-8. Instr uction L e ngths and Hexadecimal Opcodes Ari thm etic ( Group I) Mn em on ic Direc t Im medi ate In dire ct In dex ed (Note 1 ) ...
8XC196MC, MD, MH USER’S MANUAL A-48 Arithme tic (Group I I) Mn em on ic Direc t Im medi ate In dire ct In dex ed (Note 1 ) Len gth Opcode L ength Opco de Length Op co d e Length S/ L Opc ode DI V 4 FE 8C 5 F E 8D 4 FE 8E 5 /6 FE 8F DI VB 4 FE 9C 4 F E 9D 4 FE 9E 5 /6 FE 9F DIVU 3 8C 4 8 D 3 8E 4/5 8F DIVUB 3 9C 3 9 D 3 9E 4/5 9F MUL (2 o ps ) 4 F ...
A-49 INSTRUCTION SET REFERENCE S tack Mn em on ic Direc t Im medi ate In dire ct In dexe d (Note 1 ) Len gth Opcode L ength Opco de Length Op co d e Length S/ L Opc ode PO P 2 CC — — 2 CE 3/4 CF P O P A 1 F 5 —————— P O P F 1 F 3 ——— ——— PUSH 2 C8 3 C9 2 CA 3/4 CB P U S H A 1 F 4 —————— P U S H F 1 F 2 —— ...
8XC196MC, MD, MH USER’S MANUAL A-50 Ca ll Mn em on ic Direc t Im medi ate In dire ct In dexe d (Note 1 ) Len gth Opcode L ength Opco de Leng th Op code Le ngth Opcod e L C A L L —————— 3 E F R E T ———— 1 F 0 —— S C A L L ( N o t e 2 ) —————— 2 2 8 – 2 F T R A P 1 F 7 —————— Con dit ion al Jump Mn ...
A-51 INSTRUCTION SET REFERENCE Shi ft Mn em on ic Direc t Im medi ate In dire ct Index ed Len gth Opcode L ength Opco de Leng th Op code Le ngth Opcod e NORML 3 0 F ————— — S H L 3 0 9 —————— S H L B 3 1 9 —————— S H L L 3 0 D ————— — S H R 3 0 8 —————— S H R A 3 0 A —————— S H ...
8XC196MC, MD, MH USER’S MANUAL A-52 T able A -9 list s instruct ions alp h a be ticall y within groups, a l o ng wit h the ir e xecutio n t ime s, e x- presse d in state t i me s. T abl e A-9. Instr uct ion Execution Ti m es (in State T imes) Ari thm etic ( Group I) Mne monic Dire ct Immed . I ndirec t Inde xed Norm a l Au toinc. Sh ort Long R e ...
A-53 INSTRUCTION SET REFERENCE Arithme tic (Group I I) Mne monic Dire ct Immed . I ndirec t Inde xed Norm a l Au toinc. Sh ort Long R e g .M e m .R e g .M e m .R e g .M e m .R e g .M e m . D I V 2 6 2 7 2 83 12 93 22 93 23 03 3 DI VB 18 1 8 2 0 23 2 1 24 21 24 22 25 DI VU 24 25 26 29 2 7 30 27 3 0 28 31 DI VUB 16 1 6 1 8 21 19 22 19 2 2 20 23 MU L ...
8XC196MC, MD, MH USER’S MANUAL A-54 Sta c k (Re gis ter) Mne monic Dire ct Immed . I ndirec t Inde xed Norm a l Au toinc. Sh ort Long R e g .M e m .R e g .M e m .R e g .M e m .R e g .M e m . P OP 8 — 10 12 1 1 13 1 1 1 3 12 14 P O P A 1 2 — — ——— ———— P O P F 7 — — —————— — P U S H 6 7 9 1 21 01 31 01 3 1 1 1 ...
A-55 INSTRUCTION SET REFERENCE Data Mne moni c I ndirec t B MOV re gist er/reg ister 6 + 8 per word me m ory/reg ister 6 + 1 1 per word me m ory/m e m ory 6 + 14 per word B MOV I re gi st er/ reg iste r 7 + 8 per word + 1 4 p er int erru pt me m ory/reg ister 7 + 1 1 per word + 14 p er int errupt me mo ry/m emo ry 7 + 14 p er word + 1 4 p er int er ...
8XC196MC, MD, MH USER’S MANUAL A-56 Call (Mem ory) Mne monic Dire ct Immed . In dire ct Ind exed Norm a l Au toinc. Sh ort Lon g LCAL L — — — — — 13 RET —— 1 4 — — — S CALL — — — — — 13 T R A P 1 8 — ———— Con dit ion al Jump Mne monic Sho rt-Ind e x e d DJ NZ 5 (j ump n ot ta ken), 9 (j u mp taken) DJNZW 6 ...
A-57 INSTRUCTION SET REFERENCE Shi ft Mne moni c Di rec t NORML 8 + 1 p e r shi ft ( 9 for 0 shift) S HL 6 + 1 pe r shi ft (7 fo r 0 shi ft) S HLB 6 + 1 pe r shi ft (7 fo r 0 shi ft) S HLL 7 + 1 pe r shi ft (8 fo r 0 shi ft) S HR 6 + 1 per shift (7 fo r 0 shift ) S HRA 6 + 1 pe r shi ft (7 fo r 0 shi ft) S HRAB 6 + 1 pe r shi ft (7 for 0 shi ft) S ...
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B Signal Des criptions ...
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B- 1 APPENDI X B SIGNAL DE SCRI PTIONS This appendix provides ref erenc e i nfor m a t ion f or the pin func t i ons of the 8XC1 96MC, 8XC196MD, and 8XC19 6 MH . B.1 SIGNAL NAME CHANGES The names of some 8XC196MC and 8XC 196MD signa ls have been change d for consi st ency with ot her M CS ® 96 microcont r ollers. T able B-1 lists the old an d new ...
8XC196MC, MD, MH USER’S MANUAL B-2 T able B -2. 8XC196MC Signals Ar ra nged b y F unctional Categories Addre s s & Data Pro gramm ing Con trol Input/ Output I nput/Outp ut (Cont’ d) AD15 :0 AINC# P0.7:0/ACH7: 0 P6.5 / W G3 CPVER P1.0/ACH8 P 6. 6 /P WM 0 Bu s Contro l & Statu s P ACT # P1 .1 / ACH9 P 6 .7/PW M1 ALE/ ADV# P ALE# P1 . 2/AC ...
B- 3 SIGNA L DESCRIPTIONS Figure B-1. 8XC19 6MC 64-lead Shr ink DIP ( SDIP) Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.6 / READY P5.4 / ONCE# EXTINT V SS XTAL1 XTAL2 P6.6 / PWM0 P6 ...
8XC196MC, MD, MH USER’S MANUAL B-4 Figure B-2. 8XC196 MC 84-lead PLCC Package P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# NC NC P2.7 / COMP3 P2.3 / EPA3 P2.2 / EPA2 / PROG# NC NC P2.1 / EPA1 / PALE# P2.0 / EPA0 / PVER NC P0.0 / ACH0 P0.1 / ACH1 P0.2 / ACH2 P0.3 / ACH3 P0.4 / ACH4 / PMODE.0 P0.5 / A ...
B- 5 SIGNA L DESCRIPTIONS Figure B-3. 8XC196MC 80-lead Shrink EIAJ/QFP Pa ckage A3104-01 P6.7 / PWM1 P2.6 / COMP2 / CPVER P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# NC NC P2.7 / COMP3 P2.3 / EPA3 P2.2 / EPA2 / PROG# NC NC P2.1 / EPA1 / PALE# P2.0 / EPA0 / PVER NC P0.0 / ACH0 P0.1 / ACH1 P0.2 / ACH2 ...
8XC196MC, MD, MH USER’S MANUAL B-6 T able B -3. 8XC196MD Signals Ar ra nged b y F unctional Categories Addre s s & Data Pro gramm ing Con trol Input/ Output I nput/Outp ut (Cont’ d) AD15 :0 AINC# P0 . 7:0/ ACH7:0 P 7. 1 : 0 /EP A5: 4 CPVER P1 . 1:0/ ACH9:8 P 7. 3 : 2 /COMP5:4 Bu s Contro l & Statu s P ACT # P1 .2 / ACH1 0 /T1CL K P7.6:4 ...
B- 7 SIGNA L DESCRIPTIONS Figure B-4. 8XC196 MD 84-lead PLCC Package P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# P7.3 / COMP5 P7.2 / COMP4 P2.7 / COMP3 P2.3 / EPA3 P2.2 / EPA2 / PROG# P7.1 / EPA5 P7.0 / EPA4 P2.1 / EPA1 / PALE# P2.0 / EPA0 / PVER P7.7 / FREQOUT P0.0 / ACH0 P0.1 / ACH1 P0.2 / ACH2 P0.3 / AC ...
8XC196MC, MD, MH USER’S MANUAL B-8 Figure B-5. 8XC196MD 80-lead Shrink EIAJ/QFP Pa ckage A3105-01 P6.7 / PWM1 P2.6 / COMP2 / CPVER P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# P7.3 / COMP5 P7.2 / COMP4 P2.7 / COMP3 P2.3 / EPA3 P2.2 / EPA2 / PROG# P7.1 / EPA5 P7.0 / EPA4 P2.1 / EPA1 / PALE# P2.0 / EPA0 / PVER P7 ...
B- 9 SIGNA L DESCRIPTIONS T able B -4. 8XC196MH Signals Ar ra nged b y F unctional Categories Addre s s & Data Pro gramm ing Con trol Input/ Output I nput/Outp ut (Cont’ d) AD15 :0 AINC# P0.5:0/ACH5: 0 P5.0 CPVER P0.6/ ACH6/T1CLK P5. 1 Bu s Contro l & Statu s P ACT # P0 .7 / ACH7 / T1DIR P 5.7:2 ALE/ ADV# P ALE# P1 .0 /TXD0 P 6.0/WG1# BHE ...
8XC196MC, MD, MH USER’S MANUAL B-10 Figure B-6. 8XC196MH 64-lead Shr ink DIP (SDIP) Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.6 / READY P5.4 / ONCE# EXTINT V SS XTAL1 XTAL2 P6.6 / ...
B-11 SIGNA L DESCRIPTIONS Figure B-7. 8XC196 MH 84-lead PLCC Package P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# NC NC P2.7 / SCLK1# / BCLK1 P2.3 / COMP3 P2.2 / EPA1 / PROG# NC NC P2.1 / SCLK0# / BCLK0 / PALE# P2.0 / EPA0 / PVER NC P0.0 / ACH0 P0.1 / ACH1 P0.2 / ACH2 P0.3 / ACH3 P0.4 / ACH4 / PMODE.0 ...
8XC196MC, MD, MH USER’S MANUAL B-12 Figure B-8. 8XC196MH 80-lead Shrink EIAJ/QFP Pa ckage B.3 SI GNAL DES CRIPTIO NS T abl e B-5 define s t he colum ns used in T able B-6, which descri bes the si gna ls. A2574-02 P6.7 / PWM1 P2.6 / COMP2 / CPVER P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# NC NC P2.7 / SCLK1# / BCLK1 P2.3 / COMP ...
B-13 SIGNA L DESCRIPTIONS T able B -5. Description of Column s of T able B-6 Col u mn He ading Desc ription Nam e L ists the sig n als, a rrang e d alpha betical ly . M a ny p ins ha ve two f u nction s, so th ere a re m ore entrie s in thi s col umn th a n th ere are pin s. Ev er y si g nal is listed in th is column . Ty p e Id entif ies t he p in ...
8XC196MC, MD, MH USER’S MANUAL B-14 A INC# I Au to Incre ment Duri n g sla ve prog ra mmin g, this a ctive-l ow inp ut enab l es th e a u to-increm ent featu re. (Au to incr ement a llows re a d i n g or w riting o f sequent ial OTP ROM loca ti ons, with o ut req ui rin g a ddre ss tr an sact io ns acro s s t he PBUS for each read or write .) AIN ...
B-15 SIGNA L DESCRIPTIONS BUSWI DTH I Bus W i d th T wo chip confi gurati on regi st er bits, CCR0.1 and CCR1.2 , alo ng with the BUSWIDTH pi n, control the d a ta b u s width. W h en both CCR b i t s ar e set, th e BUSW IDTH sign al selects the ext ernal da t a bu s width. W hen onl y one CCR bit is set, th e bus width is fixed at either 16 o r 8 ...
8XC196MC, MD, MH USER’S MANUAL B-16 EP A3: 0 ( MC) E P A5 :0 (M D ) E P A1 :0 (M H ) I/O Even t Processor Array (EP A) Cap tur e/Co m pa re Cha nnel s High-sp eed input /output signal s for t h e E P A capture / compare channe ls. EP A 5: 0 a re mu l tiplexed as follows: EP A0/ P2.0/PVER, EP A1 /P2.1/P A LE # (M C, MD), EP A1 /P2.2/PROG# ( MH), E ...
B-17 SIGNA L DESCRIPTIONS ONCE # I On-circu it Emulation Holding ONCE# lo w during th e rising edge of RESE T# places t he device i nto on-circui t e mulatio n (ONCE) m ode . This mod e puts all p in s, except XT AL 1 and X T AL 2, in to a hi gh- i mpe danc e s t ate, the r eb y is ol at ing t he de v ic e fr om o th er com p o nent s in the sy s t ...
8XC196MC, MD, MH USER’S MANUAL B-18 P 2. 7 :0 I/ O Port 2 This is a stan dard , 8-bi t, bid irectio nal port th at is m ulti plexed with individ uall y sele ctable special -functio n si g nals. P2.6 i s multipl exed wit h a spe cial test-m ode-en try functi on. If thi s pin is h el d lo w durin g reset , the device wil l enter a reser v ed test m ...
B-19 SIGNA L DESCRIPTIONS P 7.7:0 (MD only) I/O Po rt 7 This is a standard , 8-bi t, bidire ctio na l port with Schm it t-tri gg er inpu ts. Port 7 is m u ltiple xed as f ollow s: P7.0/EP A4 , P7.1/EPA 5, P7 .2/COM P4, P7.3/COMP5 , and P7.7/FREQOUT . P 7.6:4 a re not m ultiplexed. Port 7 is n ot im p l e m e nt ed o n th e 8XC1 9 6MC and 8XC19 6MH. ...
8XC196MC, MD, MH USER’S MANUAL B-20 PROG# I Progr a m m in g S tart Duri n g p rogram ming, a fal l ing ed ge l atches d ata o n the PB US and begins pro gr am ming , whil e a r isin g edg e ends prog ram min g. The cu rren t loca tio n is programmed with t h e same data as lon g a s PROG# rema i n s asserted, so the data on the PBUS must remain ...
B-21 SIGNA L DESCRIPTIONS S CLK1:0 # (MH only) I/ O Sh ift Clo ck 0 and 1 In S IO mode 4, S CLK x # are bidirectio n al shift clock signal s that synchronize the serial data transfer . The DIR b i t in th e SP_CON re g ister control s the d i recti o n o f SCL K x #. DIR = 1 al l ow s an e xt ernal shift clock t o be i nput o n SCLK x #. DIR = 0 ca ...
8XC196MC, MD, MH USER’S MANUAL B-22 B.4 DEF AULT CO NDITIO N S T abl e B-8 lists t he value s of the signals of the 8XC1 96MC and 8XC1 9 6MD durin g vari ous oper- ating cond itions. The sha ded rows i n di cate t hose s igna l s that a re available only on the WG3: 1 O W avef or m Gene rator Phase 1 –3 Po sitive Outpu ts 3-pha se outpu t signa ...
B-23 SIGNA L DESCRIPTIONS 8XC196MD. T abl e B-9 lists the same information for the 8XC 196MH. T a bl e B -7 define s the symbols used to repres ent the pin stat us. Refer to the DC Charact eristic s t able in the datashee t for actua l specifica tio ns for V OL , V IL , V OH , and V IH . T able B-7. Defi nit ion of Status Symbols Symbo l Defin itio ...
8XC196MC, MD, MH USER’S MANUAL B-24 P 6.3 W G2 WK 1 WK1 (No te 13 ) (No te 13 ) P 6.4 W G3# WK 1 W K1 (N o te 13 ) (N o te 13 ) P 6.5 W G3 WK 1 WK1 (No te 13 ) (No te 13 ) P 6.6 P W M0 W K 0 — (No te 13 ) (No te 13 ) P 6.7 P W M1 W K 0 — (No te 13 ) (No te 13 ) P 7.1 :0 (No te 15 ) E P A5: 4 W K1 (Not e 1) — (No te 12 ) (No te 12 ) P 7.3 :2 ...
B-25 SIGNA L DESCRIPTIONS T able B -9. 8XC196MH Default Sign al Condit ions Po rt Signals Alte rnat e F unctio ns Du ring RESET# Act i v e Upon RE SET# In activ e (Note 12) Idle Po werdown P 0 .5:0 ACH5: 0 HiZ — H iZ HiZ P0.6 ACH6/ T1CLK HiZ — H i Z HiZ P0.7 ACH7/ T1DIR HiZ — H iZ HiZ P1.0 TXD0 WK1 WK 1 (Note 10) (No te 10) P1.1 RXD0 WK1 WK 1 ...
8XC196MC, MD, MH USER’S MANUAL B-26 — XT AL1 Osc in p u t, HiZ — O s c inp u t, Hi Z Os c input, HiZ — XT A L2 O sc o utpu t, L oZ0/1 — Osc out p ut , LoZ0/ 1 ( Note 5 ) NOTES: 1. Th ese pins a lso c ont rol t e s t mo de e ntr y . 2. If Disa ble Reset Out = 0 , pin i s LoZ0. Else if Disabl e Reset Out =1, pin is Hi Z. 3. If EA# = 0, Port ...
C Registers ...
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C-1 APPENDI X C REGI STERS This appendix provid es re ferenc e in formation abou t the device regis ters. T able C-1 lists the mod- ules a n d ma jor comp onents of the devi ce with their re lated configurat ion and stat us regist ers. T a- ble C-2 l i sts the r e giste r s , arra n g ed alpha betical ly by mnem o ni c , al o ng wi th their nam es, ...
8XC196MC, MD, MH USER’S MANUAL C-2 T able C -2. Register Name, Address, an d Reset Status Re giste r Mn emoni c Re gis ter Nam e He x Addr Bin ary Res et V a l ue High Low AD_COM MAND A/D Comman d 1 F AC 1000 0 000 AD_RESU L T (MC, MD) AD_RESU L T ( MH) A/D Resul t 1F AA 1111 111 1 11 0 0 0 0 0 0 01 1 1 1 1 1 1 1 100 00 00 AD_ TEST (M C, M D) AD_ ...
C-3 REGISTERS EP A1_TI ME EP A Captu re /Comp 1 Ti m e 1F46 X XXX X XXX XXXX X XXX EP A2 _T IM E (MC , MD) E P A C ap t ure /Co mp 2 T i me 1F4A XXX X XXX X XXX X XX XX EP A3 _T IM E (MC , MD) E P A C ap t ure /Co mp 3 T i me 1F4 E XXX X XX XX XXX X XXX X EP A4_TI ME (M D) EP A Capture/ Comp 4 Ti m e 1F52 X XXX X XXX XXXX XXXX EP A5_TI ME (M D) EP ...
8XC196MC, MD, MH USER’S MANUAL C-4 P 7_PI N ( MD) Por t 7 P in In put 1FD 7 XX X X XXX X P1_RE G (M H) Po rt 1 Da ta Outp ut 1F9D 1 1 1 1 1 1 1 1 P2_RE G Po rt 2 Da ta Outp ut 1FD4 1 1 1 1 1 1 1 1 P3_RE G Po rt 3 Da ta Outp ut 1F FC 1 1 1 1 1 1 1 1 P4_RE G Po rt 4 Da ta Outp ut 1F FD 1 1 1 1 1 1 1 1 P5_RE G (M C, MD) P5_RE G (M H) Po rt 5 Da ta O ...
C-5 REGISTERS T1CONTROL T imer 1 Control 1F78 00 00 0000 T2CONTROL T imer 2 Control 1F7C 0000 0000 T1REL OAD T im er 1 Reloa d 1F 72 X XXX X XXX X XXX X XXX TI MER1 T i me r 1 V al ue 1 F7 A 00 00 00 00 00 00 00 00 TI MER2 T i me r 2 V al ue 1 F7 E 00 00 00 00 00 00 00 00 USF R (MC, MD) USF R (MH) UPROM Sp ecial Functio n 1F F6 00 00 00 10 XXX X XX ...
8XC196MC, MD, MH USER’S MANUAL C-6 AD_COMM AND AD_CO MMAND Address: Reset Sta te: 1F A C H 80 H The A/D comma nd (AD_COMM A N D) registe r selects the A/D c han nel numb er to b e converte d, con trols whe ther th e A/ D converte r star ts imm e d iatel y or with an E P A co m m and, a n d selects th e con v ersion mo de. 7 0 — M1 M0 GO ACH 3 A ...
C-7 REGISTERS AD_ RE SUL T (Read ) AD_RESULT (Read) Address: Re s et S ta te ( MC, M D): R eset Sta te (M H): 1F AAH FFC0 H 7FC0 H The A/D resul t (AD_RESU L T ) registe r consists of two b yt e s. The h i gh b yt e con t ains t h e e i g ht mo st- sign i f icant bits f rom t he A/D c onverter. The low byte conta ins the two least-si gnificant bits ...
8XC196MC, MD, MH USER’S MANUAL C-8 AD_RES UL T ( Write) AD_ RESUL T (Write ) Address: Re s et S ta te ( MC, M D): R eset Sta te (M H): 1F AAH FFC0 H 7FC0 H The high byte o f th e A/D resul t (AD_RES UL T ) re giste r can b e writt en to set the r e feren ce volta ge for the A /D t hr eshol d- detecti on m o des. 15 8 REFV7 REFV 6 REFV5 REFV4 REF ...
C-9 REGISTERS AD_TEST AD_TEST Address: Re s et S ta te ( MC, M D): R eset Sta te (M H): 1F AEH C0 H 88 H The A/D test (AD_T EST) reg iste r specifies adju stm ents for DC o ffset e rro rs. 7 0 — — — OFF1 — OFF0 — — Bit Num b e r Bit Mne moni c F unction 7:5 — Re served ; for compatib ility with future d evices, write zeros to these bi ...
8XC196MC, MD, MH USER’S MANUAL C-10 AD_TIM E AD_TIM E Ad dress: Reset Sta te: 1F AFH FF H The A/D tim e (AD_ TIME) registe r prog r ams the s ample wind ow time a n d the con version ti m e for e ach bit. T his reg ister pro gram s the spee d at wh ich the A/D can r un — n ot the sp eed at whi c h it can convert corre c tly . Co nsu lt the d at ...
C-11 REGISTERS CCR0 CCR0 no direct ac c e ss† The chip config ura tion 0 ( CCR0) registe r contro ls power do wn m o de , b us-con tro l sig nals, an d i nt ern al mem ory prot ection . Three o f its bi ts comb in e wi th two b its of CCR1 to contro l wait s tates an d bu s wid th. 7 0 LOC1 LOC0 IRC1 IR C0 ALE WR BW0 PD Bit Num b e r Bit Mn em on ...
8XC196MC, MD, MH USER’S MANUAL C-12 CCR0 3 AL E Addre s s V alid Strob e a n d Write Stro be The se b its defi ne which bu s-con tro l si gnal s will be g ener ate d du rin g ext ernal read and write cy c l es. ALE W R 0 0 a ddress valid with write strobe mode (AD V#, RD#, WRL # , WR H#) 0 1 add ress valid strobe mode (AD V#, RD#, WR# , BHE# ) 1 ...
C-13 REGISTERS CCR1 CCR1 no direct access † The chip con fi gurati on 1 (CCR1) re gister e n a b l es the wat chdog ti mer a nd sele cts the b us timin g mod e. T wo o f its bit s combi ne with three bits of CCR0 to control wait states and bus widt h. 7 0 1 1 0 1 WDE BW 1 IRC2 0 Bit Num b e r Bit Mn em on ic Fu nction 7:6 1 T o g uara nte e prope ...
8XC196MC, MD, MH USER’S MANUAL C-14 CCR1 1 IRC2 Ready Co n t r ol This bi t, along with IRC0 (CCR0 . 4 ), IRC1 (CCR 0.5), an d the READY pin d ete rm ine t he num ber of wa it st ates th at can be ins er ted in to th e b us cycle. W h ile READY is held low , wait states are inse rted i nto the b u s cycle until the progra m med num b er of wait s ...
C-15 REGISTERS COMP x_CON COMP x _CON x = 0–3 (8XC19 6MC, MH ) x = 0–5 (8XC19 6MD) Address: Re set State: T a ble C -3 The EP A com pare con tro l (C O M P x _CON) registers determin e the fu nction of the EP A com p are ch an ne ls. 7 0 x = 0, 2, 4 TB CE M1 M0 RE WGR ROT RT 7 0 x = 1, 3, 5 TB CE M1 M0 RE AD ROT RT 7 T B Ti m e Base Sele ct Spe ...
8XC196MC, MD, MH USER’S MANUAL C-16 COMP x_CON 2W G R AD A/ D Conversio n, Wavefor m Gen er ator Reload The functio n of this bi t dep e nds o n the EP A ch annel. Fo r EP A ca pture/ compa re ch annel s 0, 2, 4 : The WGR bit all ows you to use the EP A activitie s to c ause the re l o a d of new va lues in the waveform gen erato r . 0 = no acti ...
C-17 REGISTERS CO M P x_TIME COMP x _ TIME x = 0– 3 (8X C 19 6M C, MH ) x = 0– 5 (8X C 19 6M D Address: Reset Sta te: T a bl e C -3 The EP A co m p are x tim e (COMP x _TIM E) reg iste rs are the even t-ti me reg isters for the EP A comp are channe ls; the y are fun ctional ly identi c ally to the E P A x _TIM E regi s ters. T h e EP A tri gger ...
8XC196MC, MD, MH USER’S MANUAL C-18 EP Ax_CON EP A x _CON x = 0 –1 ( 8XC196 MH) x = 0 –3 ( 8XC196 MC) x = 0 –5 ( 8XC196 MD) Address: Re set State: Ta b l e C - 4 The EP A control (EP A x _CON) registe rs cont ro l the f unctio ns of th eir a s signed capture /comp are cha n n els. 7 0 x = 0, 2, 4 TB CE M1 M0 RE WGR ROT ON/RT 7 0 x = 1, 3, 5 ...
C-19 REGISTERS EP Ax_CON 3 R E R e- en ab le Re- enab le applie s to the comp are mode on ly . It allows a compa re even t to continue to e xecute each time the e vent-ti me re gist er (EP A x _ TIME) match es the ref ere nce time r rather tha n o nly up on the first time match. 0 = comp are f uncti o n i s disa bled after a si ngle event 1 = com p ...
8XC196MC, MD, MH USER’S MANUAL C-20 EP Ax_CON 0 ON/R T Overwri te New/Reset T imer The ON/RT b it function s as o verwri te n e w in captu re mode a nd reset ti me r i n c o mp are m ode . In Cap ture M ode (ON): An ove rrun error is gen erate d wh e n a n i n put captur e oc c urs whi le th e eve nt-t ime reg iste r (EP A x _TI ME) a nd its b uf ...
C-21 REGISTERS EP Ax_TIME EP A x _T IM E x = 0– 1 (8X C 19 6M H) x = 0– 3 (8X C 19 6M C) x = 0– 5 (8X C 19 6M D) Address: Reset Sta te: T a bl e C -5 T he EP A ti me ( EP A x _TIM E) reg iste r s are th e event-t ime reg ister s f or the EP A chann e ls. In capture mod e, the value o f th e refere nce tim e r is cap tu red i n E P A x _TIM E ...
8XC196MC, MD, MH USER’S MANUAL C-22 FREQ _C NT FREQ_ CNT ( 8XC196 MD) A dd r ess : Re s et S ta te: 1FBAH 00 H Re ad t he fre quenc y ge nerato r cou nt (F REQ_CNT ) regi ster to d etermi ne the cu rrent va lue o f the dow n-cou n t er . 7 0 8X C196M D Co un t Bit Num b e r Functi on 7: 0 Count This re gister con tains t he curr ent down -counter ...
C-23 REGISTERS FREQ _GE N FREQ_ GEN ( 8XC196 MD) A dd r ess : Re s et S ta te: 1 FB8H 00 H The freq u ency (FREQ_GEN) re gister h olds a p rogramme d valu e that spe cifies th e ou tp u t frequen cy . Thi s valu e is rel oade d into the down -cou nte r each t i me the counte r reache s 0. 7 0 8XC1 96M D Output Frequ e ncy Bit Num b e r Functi on 7: ...
8XC196MC, MD, MH USER’S MANUAL C-24 GEN_CON GEN_C ON (8 XC196M H) Address: Reset Sta te: 1F A0H 00H The GEN_CON registe r controls wheth er an i n te rnal reset asserts t he external RESET# signal a n d indi cate s the source of the m ost recen t reset . 7 0 8XC19 6MH RSTS — — — — — — DR 0 Bit Num b e r Bit Mn em on ic Fun ction 7 RST ...
C-25 REGISTERS INT_M ASK INT _ M ASK A d d ress: Reset Sta te: 00 08 H 00 H The interru p t mask (INT_MASK ) registe r e n ables o r disab les (m a s k s) individ ual i n terru pt requ ests. (Th e EI and DI instr uctio ns ena b le a n d disa ble servicin g of a ll maska ble in terrup ts.) INT_M ASK is the low byte o f t he processor status word (PS ...
8XC196MC, MD, MH USER’S MANUAL C-26 INT_M AS K1 INT_M ASK1 Address: Reset Sta te: 00 13 H 00 H The in terrup t mas k 1 (INT_M ASK1) re giste r enab les or d isable s (m asks) i n d i vidual i nterru pt re q uests. (Th e EI a nd DI instructi on s enab le and disabl e ser vicing o f a ll mas kable interr upt s.) INT_MASK 1 can be re a d from or wri ...
C-27 REGISTERS INT _PEN D INT _PEND Address: Reset Sta te: 00 09 H 00 H When h ar d ware det ects an i nt e rrupt req uest, i t sets the correspo nding b it in the inter rupt pen d i ng (INT _PEND or IN T_PEND1) re giste rs . When the vector is t aken, th e h ardwar e cle ars the pen d i n g bit. Softwa re can gene rat e an interr up t by setti ng ...
8XC196MC, MD, MH USER’S MANUAL C-28 INT_P EN D1 INT_PE ND1 Address: Reset Sta te: 00 12 H 00 H When hardwar e det ects a pendin g interru pt, i t set s the corr espo n ding b it in the i nterr u pt pen ding (INT _PEND or IN T_PEND1) re giste rs . When the vector is t aken, th e h ardwar e cle ars the pen d i n g bit. Softwa re can gene rat e an i ...
C-29 REGISTERS ONES _RE G ONES_REG Address: Reset Sta te: 02 H FF FFH The two-b yte ones register (ONE S_RE G) is a l ways eq ual to FFF FH. It is use fu l as a f ixed source of all ones f or co m parison ope ration s. 15 0 One Bit Num b e r Func tio n 15 :0 On e The se bits a re always eq ual t o FFF FH. ...
8XC196MC, MD, MH USER’S MANUAL C-30 Px_DIR P x _DIR x = 2, 5 (8 XC 1 96 MC) x = 2, 5 , 7 (8 XC19 6 MD) x = 1, 2 , 5 (8 XC19 6 MH) Address: Reset Sta te: Ta b l e C - 6 Each pin o f p o rt x can operate in a ny of t he stan dard I/O mo des of o per ation: co mple m e n tary out p u t, open -dra i n ou tput, or hi gh-im p e dan ce in put. T he por ...
C-31 REGISTERS Px_M ODE P x _MODE x = 2, 5 (8XC19 6MC ) x = 2, 5 , 7 (8 XC19 6 MD) x = 1, 2 , 5 (8 XC19 6 MH) Add ress : Rese t State: T a ble C-7 Each bit of th e p ort x mod e (P x _MODE ) regi s ter c ont ro ls whether th e cor respond i ng pin functio ns as a stan da rd I /O port pin or a s a special-f unct io n signa l. 7 0 x = 1 (M H ) — ? ...
8XC196MC, MD, MH USER’S MANUAL C-32 Px_MO DE T able C -8. Special-function Signals for Ports 1, 2, 5, 6 Port 1 (8X C196M H) Port 2 ( 8XC196 MC, M D) Port 2 ( 8XC196 MH) Pi n Sp e cia l-functi on Sig n a l Pin Spec ial-fun ction Sign al Pin Speci al-func tion S ignal P1.0 TXD0 P 2.0 EP A0/PVER P2. 0 E P A0/PVE R P1.1 R XD0 P 2.1 EP A1/ P AL E# P2. ...
C-33 REGISTERS Px_P IN P x _PI N x = 0–5 (8XC19 6MC, MH ) x = 0–5 , 7 (8 XC196M D) Add ress : Rese t State: T a ble C-9 Each b it of t he po rt x pin in put (P x _PI N) registe r refl ects the curren t state of th e corre sp ondi ng p in, reg ard le ss of the p in co nf ig ura tio n. 7 0 x = 1 ( MC) —— — P IN4 PIN3 PIN2 PI N1 P IN0 7 0 x ...
8XC196MC, MD, MH USER’S MANUAL C-34 Px_RE G P x _RE G x = 2–5 (8XC19 6MC) x = 2–5 , 7 (8 XC196M D) x = 1–5 (8XC19 6MH) Add ress : Rese t State: T a b le C -10 For an i nput, set t he correspo nd in g port x da t a ou tp ut ( P x _REG) re gister bit. For an ou tput, wri te th e da t a to be driven ou t by e ach pi n to the correspo nding bit ...
C-35 REGISTERS PI_M ASK PI_ MASK Add ress : Rese t State: 1FBCH AAH The p er iphera l interr upt m ask (PI_M ASK) reg ister e n ables o r disab les ( m as k s) i nterru pt req u e sts as socia ted wi th the peri ph era l interru p t (PI), the seria l port int erru pt (SPI), and the overf low/un derfl ow time r inte rrup t (OV R T M). 7 0 8XC1 9 6 M ...
8XC196MC, MD, MH USER’S MANUAL C-36 PI_M ASK 0 OVRT M1 Ti me r 1 Overfl ow/Und erflow Se tting this bit enab les the tim er 1 o ve rflow/ unde rflo w inte rru pt. The time r 1 an d time r 2 overflo w/underf low inter rupts ar e asso ciate d wit h the overf lo w/u nd erfl ow tim er inte rrup t (OV RTM). Se ttin g INT_ MASK. 0 ena b l es OVRTM. PI_ ...
C-37 REGISTERS PI _P E N D PI_PEND Add re ss: Rese t State: 1FBEH AAH When hard ware dete cts a p end ing p eriph eral or timer inte rrupt, it se ts th e correspo ndin g bi t in t he interr upt pen d i n g (INT _PEND o r INT_PE ND1) r e g ister s a nd t h e p e riphe ral inte rrupt pe n d i n g (PI_ PEND) registe r . Whe n the vecto r is taken , th ...
8XC196MC, MD, MH USER’S MANUAL C-38 PI _P E ND 0 OVRT M1 Ti me r 1 Overfl ow/Und erflow W h en set, this bit ind icates a p endi ng tim er 1 o verfl ow/und erflo w in terrup t. The time r 1 an d time r 2 overflo w/underf low inter rupts ar e asso ciate d wit h the overf lo w/u nd erfl ow tim er inte rrup t (OV RTM). Se ttin g INT_ MASK. 0 ena b l ...
C-39 REGISTERS PPW PPW no d ire ct a cce ss The p rogra m ming pulse width (PPW) regist er is loaded from the e xternal EPROM (locati ons 1 4H an d 15H f or th e 8XC1 96MC a nd M D; lo cations 4 014H and 4 0 15H for the 8XC19 6MH) i n au to pro gra m mi ng m od e. T he P PW_V A LUE de te r mine s th e pr ogr amm i ng pu ls e w idt h. 15 8 P PW15 PP ...
8XC196MC, MD, MH USER’S MANUAL C-40 PS W PSW no direct access The pr o c es sor status wo rd (PSW ) actua lly consists of two b yt e s. Th e high b yt e is th e sta tus word, which i s de scribed h ere; th e low b yte is the I NT_MA SK regi ster . The sta tus word con tains o n e bit (PSW. 1 ) that global ly enable s or d i sa bles servici ng of ...
C-41 REGISTERS PSW 12 V T Over flow-tra p Fl ag T hi s fla g is s e t whe n the overflo w flag is se t, but i t is cle ar ed only by the CLRV T , JVT , a n d JNVT instructi o ns. This a llows te s tin g f or a possib le overfl ow at th e end of a seq uence of rela ted arit hmetic op erati o ns, w hich is gene ral ly more e fficie nt than testi ng t ...
8XC196MC, MD, MH USER’S MANUAL C-42 PT SSE L P TSSEL Ad dress : Re s et S ta te: 00 04H 00 0 0 H The PTS se l ect (P T SSEL) re gist er se lects either a PTS m icroco d e ro utine o r a stan dard inte rrupt se rvice ro utine for e ach in terrup t req uest. Setti n g a bit sel ects a PT S micro code ro utin e; clea ring a bit se lects a sta ndard ...
C-43 REGISTERS PT SSRV PTSSRV Addre ss : Re s et S ta te: 00 06H 00 0 0 H The PTS servi ce (PTS SR V) re gist er is used b y the hard ware to ind icate th a t the final PTS inte rrupt h as bee n s erviced by the PTS routin e. When PTSCOUNT re aches ze ro , h ar d ware clears th e corre - sp ondi ng P T SSEL bit and sets the PTSSRV bit, which req ue ...
8XC196MC, MD, MH USER’S MANUAL C-44 PWM_COUNT PWM_COUNT (rea d onl y) Address: Reset Sta te: 1F B6 H 00 H The PW M count (PW M_COUNT) registe r provid es the curre nt valu e of th e d ecrement e d peri o d cou n t e r . 7 0 PW M Cou nt V a lue Bit Num b e r Func tio n 7:0 P WM Co unt V a l ue Thi s registe r contai ns the current v a lue o f t h ...
C-45 REGISTERS PW M_PE RIOD PW M _ PERIO D Ad d ress: Reset Sta te: 1F B4 H 00 H The P W M pe ri o d ( PW M_ PERIOD) reg ister cont ro ls t h e pe ri o d of th e PWM o u tput s . It con tains a val ue that de te rmi ne s the num b er of state count s ne cess a r y for incre men tin g the PWM cou nter. T he value of PWM_PERI OD is l oade d i nt o t ...
8XC196MC, MD, MH USER’S MANUAL C-46 PWMx _CONTROL PWM x _CONTROL x = 0– 1 Address : Re set State: 1 FB0H, 1 FB2 H 00 H The P WM con tro l (PWM x _CONTROL ) register de term i ne s the d uty cyc l e o f t he P WM x ch an nel. A zero l o a d ed i nto this re gister cau ses the PWM to ou t put a l ow con tinuo usly (0 % duty c ycle). An FFH in thi ...
C-47 REGISTERS SBUF x_RX SBUF x _RX x = 0–1 (8 XC1 96M H) Address : Re set State: 1 F80 H, 1F8 8H 00H Th e se ria l po rt re ce ive buff er x (SBUF x _RX) re gist er cont ains da t a re ceived fr om se rial p ort x . Th e seri a l p ort rece iver is buffer ed and can b egin re ceivin g a se cond d ata byte be f o re the first b yte is re ad. Da t ...
8XC196MC, MD, MH USER’S MANUAL C-48 SBUFx_T X SBUF x _TX x = 0 –1 (8 XC1 96M H) Address: Reset Sta te: 1F8 2H, 1F8AH 00H The se ria l port tr ansm it bu ffer x (SBUF x _TX) registe r con t a i ns dat a t h a t is rea dy for t ransmi ssion. I n mod es 1, 2, a nd 3 , wri ti n g to SBUF x _TX sta rts a transmi ss ion. In m ode 0, writing to SBUF x ...
C-49 REGISTERS SP SP Address: Reset Sta te: 18 H XXXXH The system’ s stack pointer (SP) can point anywhe re in interna l or e xtern al memo ry; it m ust be word alig n ed a nd mu st al ways be i nitiali zed be fore u se. T h e sta ck p o inter i s d ecrem e nted b efore a PUSH and i n crem e n t ed afte r a POP , so t he stack po inter sho uld be ...
8XC196MC, MD, MH USER’S MANUAL C-50 S Px_BAUD SP x _BAUD x = 0– 1 (8X C 19 6M H) Address: R eset Sta te : 1 F84H , 1F 8CH 00 00 H T he s er ial po rt ba ud ra t e x (SP x _BAUD) reg iste r selects the serial port x baud ra t e and c l ock sour c e . The most -sign ifican t bit select s the clock source. The lowe r 1 5 bits repre sent BAUD_ V AL ...
C-51 REGISTERS SPx_CO N SP x _CON x = 0–1 (8XC1 96 MH ) Address: Reset Sta te: 1 F83H, 1F 8BH 00 H The serial port contro l (SP x _CON) registe r selects the commu nicati ons mode and enables or disables the receiver , parity che cking, and nine-b it data transm is sion. 7 0 8XC1 96MH M2 DI R PA R TB 8 REN PEN M1 M0 Bit Num b e r Bit Mn em on ic ...
8XC196MC, MD, MH USER’S MANUAL C-52 SP x_ ST ATUS SP x _ST ATUS x = 0–1 (8XC1 96 MH ) Address : Re set State: 1 F81H, 1F 89 H 00 H The serial po rt statu s (SP x _ST A T US) register co ntai ns bits that indicate t h e st a tus of serial port x . 7 0 8XC1 96MH RPE/RB8 RI TI FE TX E OE — — Bit Numb er Bit Mne moni c Fun ction 7 RPE/RB 8 Re c ...
C-53 REGISTERS T1CONT ROL T1CONTROL Address: Reset Sta te: 1F 78 H 00 H The t i mer 1 con trol (T1CONTROL ) registe r determ ines the clo c k sou rce, coun ti ng dire ction, an d count ra te for tim e r 1 . 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Num b e r Bit Mne moni c F unction 7 CE Cou nt er E nabl e Thi s bit e n ables or disabl es the t imer . From r ...
8XC196MC, MD, MH USER’S MANUAL C-54 T1REL OAD T1RELOAD Address: Reset Sta te: 1F 72 H XXXXH The timer 1 reloa d ( T1R ELOAD) r egiste r contain s a rein itial izat ion value for timer 1. The value of T1REL OAD is loa ded into TI MER1 wh e n ti mer 1 ove rflows or un derfl ows a nd b oth q u adra ture clocking and the r e load function are enabled ...
C-55 REGISTERS T2CONT ROL T2CONTROL Address: Reset Sta te: 1F 7CH 00 H The t i mer 2 con trol (T2CONTROL ) registe r determ ines the clo c k sou rce, coun ti ng dire ction, an d count ra te for tim e r 2 . 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Num b e r Bit Mne moni c F unction 7 CE Cou nt er E nabl e Thi s bit e n ables or disabl es the t imer . From re ...
8XC196MC, MD, MH USER’S MANUAL C-56 TI ME Rx TIM ER x x = 1–2 A dd r ess : Re s et S ta te: 1F 7AH, 1F7 EH 00 00 H Th is regi ster contains the valu e o f t i mer x . Thi s reg ister c an be w ritte n, a llowi ng t imer x to b e in itialize d to a va lu e othe r th an ze ro . 15 0 Tim e r V a lu e Bit Num b e r Func tio n 15 :0 Ti me r V al u e ...
C-57 REGISTERS USF R USFR Address: Re s et S ta te ( MC, M D): R eset Sta te (M H): 1F F6 H 02 H XXH The unera sable PROM (USFR) regi ster contain s two bits that disable exter nal fetche s of data a nd instructi ons a nd a n oth er that detec ts a failed o sc illato r . These bits can be program m e d , but can not be er ased. W ARNING : These bit ...
8XC196MC, MD, MH USER’S MANUAL C-58 W A TCHD OG W A TCHDOG Address: Reset Sta te: 0A H XXH Unless it is cle are d ever y 6 4K state t imes, the watchd og time r resets the d e vice. T o clea r the wat c hdog ti m er , send “1 EH” f o llowe d imm ediatel y by “E1 H” to lo cation 0AH. Cle ari n g this re giste r the fir s t time ena b les t ...
C-59 REGISTERS WG _COMPx WG_COMP x x = 1–3 Ad dress : Re s et S ta te: 1FC2H,1 FC4 H,1FC6 H 00 00 H The pha se compar e (WG_COM P x ) register controls the duty cyc le o f each phase. Wr ite a value to each p hase com pare regist er to specify t he leng t h o f time t hat the associa t ed o u tput s will re main asserted . Changing the W G_REL OA ...
8XC196MC, MD, MH USER’S MANUAL C-60 WG_CONT ROL WG_CONTROL Address: Re s et S ta te ( MC, M D): R eset Sta te (M H): 1FC CH 00 C0 H 800 0 H The wavef orm g enerato r control (WG_CONT ROL) registe r con trol s th e ope ra tin g mode , dea d tim e , and coun t d irectio n, and enab les and disa bl es the counte r . 15 8 — M2 M1 M0 CS EC DT 9 DT8 ...
C-61 REGISTERS WG_COUNT ER WG_COUNTER Address: Re s et S ta te ( MC, M D): R eset Sta te (M H): 1FCA H XXXXH 000 0 H Y ou can read the wavefo rm genera tor counte r (WG_COUNT ER) regist er to d e ter mine t h e current cou n t e r val u e . 15 0 Cou nter V al ue Bit Num b e r Func tio n 15:0 Co unte r V alu e Thi s registe r refle ct s the current ...
8XC196MC, MD, MH USER’S MANUAL C-62 WG_ OUTPUT (Por t 6) WG_OUTPUT (Po rt 6) Address: Reset Sta te: 1FC0 H 000 0 H The po rt 6 o utput con figura t ion (WG_OUT PUT) reg ister co ntro ls po rt 6 f u n ctio ns. If y ou are usin g port 6 for genera l-p urp ose outpu ts, write C0H (for active-h igh outpu ts) or 00H (for active -lo w output s) to the ...
C-63 REGISTERS W G_O UTP UT (W a v eform Generato r) WG_ OUTPUT (Waveform Genera tor) Address: Reset Sta te: 1FC0 H 000 0 H The wavef orm g enerato r output configura tion (WG_OUTPU T) regi ster cont rols t he configur ation of the wavefo rm g enera to r and PWM m o dule pins. Bot h t he wa vefo rm ge nerat or and the PWM modu le sha re pin s with ...
8XC196MC, MD, MH USER’S MANUAL C-64 WG_OUT PUT (Waveform Gener ator) 10 P H3.2 Pha se 3 Functi on S elects eith er the p ort functio n or the wavefo rm gene rat or ou tpu t fun ctio n for p i ns P6 .4/WG3# a nd P6 .5/WG3 . 0 = P6 .4, P6 .5 1 = WG3#, WG3 9 P H2.2 P hase 2 Fu nction S elects eith er the p ort functio n or the wavefo rm gene rat or ...
C-65 REGISTERS W G_O UTP UT (W a v eform Generato r) , T able C -1 1. Output Confi guration PH x .2 P H x .1 PH x .0 Outpu t V a lues Ou tput Pol arities WG x WG x #W G x WG x # 1 0 0 Low Low Always Lo w Always Lo w 1 0 1 Low WG_E VEN# Al ways Low 1 1 0 W G_ODD Low Always Lo w 1 1 1 WG_O DD WG_EVEN NOTE: This tab le assumes active-h ig h outputs (O ...
8XC196MC, MD, MH USER’S MANUAL C-66 WG_PRO T ECT WG_PROTECT Address: Re set State (M C, MD) R eset Sta te (M H): 1FC EH F0 H E0 H The wa vefo rm p rotectio n (WG_ PROTECT) re gist er enab les and d isable s the o utputs an d the prote ct ion circuitry . It a lso selec t s e i ther level -sen si tive or e d ge-tri gg ere d EXTI NT interru pts, and ...
C-67 REGISTERS WG _RELO AD WG_RELOAD Address: Reset Sta te: 1FC8 H 000 0 H The wavef orm genera to r reload (WG_REL OAD) regist er and t he phase compare re g iste rs (WG_COM P x ) con trol th e carrie r p eriod and d uty cyc le. W rite a value to the r e load r e gister t o esta blish the carrier p e riod. Changing the WG_REL OAD valu e chan ges b ...
8XC196MC, MD, MH USER’S MANUAL C-68 WSR WS R A d dress : Re set State: 00 14 H 00 H The wind o w selectio n reg iste r (WSR) map s sectio ns of RAM into the top of th e l owe r regi ster fil e, in 32-, 6 4 -, o r 1 2 8 -byte increm ents. P USHA saves t h is registe r on the stack and POP A restore s it. 7 0 — W6 W5 W4 W3 W2 W1 W0 Bit Num b e r ...
C-69 REGISTERS WSR EP A2 _CO N ( MC, MD ) 1F4 8H 7AH 0 0E8H 3D H 0 0C8 H 1E H 00C 8H EP A3_ C ON † ( MC, M D) 1 F4CH 7AH 0 0ECH 3DH 0 0 CCH 1EH 00C CH EP A4_CON (M D) 1F50H 7AH 00F0H 3DH 00 D0H 1EH 00D0 H EP A5 _CO N (MD ) 1 F54H 7AH 0 0F4H 3 DH 0 0D4 H 1EH 00 D 4H EP A0_ TIME † 1F42H 7AH 00E2 H 3DH 00C2H 1 EH 00C2H EP A1_ TIME † 1F46H 7AH 00 ...
8XC196MC, MD, MH USER’S MANUAL C-70 WSR PWM0_CONT ROL 1FB0 H 7DH 00F0H 3EH 00F 0H 1FH 0 0 B0H PWM1_CONT ROL 1FB2 H 7DH 00F2H 3EH 00F 2H 1FH 0 0 B2H SBUF0_ RX (MH) 1F80 H 7CH 00E0 H 3EH 00C0H 1 FH 0 0 8 0 H SBUF1_ RX (MH) 1F88 H 7CH 00E8 H 3EH 00C8H 1 FH 0 0 8 8 H SBUF0_ TX (MH) 1F82H 7CH 00E2 H 3EH 00C2H 1 FH 0 082H SBUF1_ TX (MH) 1 F8A H 7CH 00E ...
C-71 REGISTERS ZERO_REG ZERO_REG Address: Reset Sta te: 00 H 000 0 H The two-byte zero re g ister (Z ERO_REG) is alwa y s equal t o zero. I t is usefu l as a fixed so urce of the con s tant zero for com pari s ons and calcu l a t ions. 15 0 Zero Bit Num b e r Func tio n 15 :0 Z ero Thi s registe r is a lways e q ual to zero. ...
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Glossary ...
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Gloss ar y - 1 GLOS SARY This glossa ry defines acronyms, abbreviations, and terms that ha ve special m eaning in this m an- ual. (Chapt er 1 discusse s notational conventi ons and general term inolog y .) absolute e rror The ma ximum di f ferenc e between corresponding a ctu a l an d id eal code transiti o ns . Absolute error accounts for a ll dev ...
8XC196MC, MD, MH USER’S MANUAL Gloss ar y - 2 CCBs C h ip configurat ion bytes. The chip c onfiguration registe rs ( CCR s ) are loaded wi th the contents of the CCBs a ft er a de v ice reset, unless the de vice is en t e rin g prog ramm ing modes, in whic h cas e the PC CBs are used. CCRs Chip configurati o n regist ers. Regi st e rs that spec i ...
Gloss ar y - 3 GLOSSARY deasser t The act of maki ng a sig n a l i nactive (dis abled). The polarity (hi gh or low) is defined by the signal name. Active-low signa ls are de signated by a pound symbol (#) suffix; a c tive-high signa ls have no su f fix. T o deassert R D# i s to drive i t high; to de ass ert ALE is to drive it l ow . differential no ...
8XC196MC, MD, MH USER’S MANUAL Gloss ar y - 4 full-scal e er r or The diff erenc e bet ween t he ide a l and a c t u a l in p ut volt age corre sponding t o the final (full-sca le) co de transit ion of a n A /D c onverter . hold latency The t ime i t t akes the m icrocontrol l er t o ass ert HL DA # after an e xte rnal devic e assert s HOL D#. id ...
Gloss ar y - 5 GLOSSARY LS B 1) Leas t-si gnifi cant bi t of a byte o r leas t-sig n i ficant by te o f a word . 2) In an A/D co nv erte r , the referenc e voltage divided by 2 n , where n is t he number of bits to be co nverted. For a 10- bi t co n verte r with a refe rence voltage of 5.12 volts, o ne LSB i s equal t o 5.0 mi llivolts (5.12 ÷ 2 1 ...
8XC196MC, MD, MH USER’S MANUAL Gloss ar y - 6 nonmas kable inter rupts Interrupts that cannot be masked (disabl ed) and can n ot be assigned to the P TS f or proce ssing. The n o n maska ble inte rrup ts are unimplemented opcode, software trap, and NMI . nonvo l atil e m emory R e ad-only mem ory that re tains its c ontents w h e n p owe r i s re ...
Gloss ar y - 7 GLOSSARY pr ogr am memory A partition of m emory where instruct ions can be store d fo r fetchi n g and exec uti on. pr otected instruc tion An instructio n that prevent s an inte r rupt from being ack n o wledged unt i l afte r the next instr uction execute s. T he p rotec t ed i nstructio n s are DI, EI, DP TS, EP TS, POP A, POPF , ...
8XC196MC, MD, MH USER’S MANUAL Gloss ar y - 8 PWM Puls e-width mo dula ted (outputs ). The 8XC1 9 6M x devices have seve ral o p t ions for produ c ing PW M outputs: the generic puls e-width m odulator modules, the wave form generato r , and the EP A wi th or wit hout the PTS . The 8XC196M D also has a fr e quency generator t hat produces PWM out ...
Gloss ar y - 9 GLOSSARY sample ti m e The peri od of time that the sample window is open . (That i s, the length o f time tha t the input c hannel is actua lly connec ted to the s ample capaci tor .) sample ti me uncer tainty The vari ation in t he sample time . sample wi ndow The period of ti me that begins when the sample capacitor is atta ched t ...
8XC196MC, MD, MH USER’S MANUAL Gloss ar y -10 special i nterru pt A ny of the three nonmaskable interr upts ( uni mple- mente d opcode, softwa re tra p, or NM I ). speci al-purpose me m ory A pa rtit i on of memory use d for s toring t he int errupt ve ct ors , PTS vectors , chip configuration byte s, and several reserved locat ions. standard int ...
Glossa r y-11 GLOSSARY transfer functi on errors Errors inherent in an ana log-to-digital conversion proc ess: quan ti zing er r o r , z er o-offset err or , ful l-scale error , di f f erential n onl ine a r i t y , and n o nl inearit y . Errors that ar e hardware - de pendent, rather than being inherent in the process i t se lf, include feedt hr o ...
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Index ...
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Index -1 #, de fined, 1-3, A-1 16- bi t da ta b us r ead cy c les, 15-1 4 timing dia g ram , 15- 1 5 w r it e cyc l es, 15 -1 4 8-bit dat a bus r ead cy c les, 15-1 6 timing dia g ram , 15- 1 7 w r it e cyc l es, 15 -1 6 A A/D comman d register, 12-8, C- 6 A/D conv erter, 2-11, 12-1–12 -18 actua l char a cter is ti c, 12-16 and port 0 r ea ds, 1 ...
8XC 1 96 MC, MD, MH USER ’ S MANU AL Ind ex-2 AND i n str uction, A -2, A-8, A- 41, A- 4 2, A-48, A-53 ANDB i n str u c tio n , A-2, A- 8, A-9, A- 42, A-43, A-48, A-5 3 ANGND, 1 2-5, 13-1, B-14 Ap BUI LDER s o ftwa r e , down loading, 1-10 Applic a ti on notes, order ing, 1 -6 Ar ithme tic instr uctions, A-47, A-48, A-52, A-53 As se rt , define d ...
Index -3 INDEX Clock exte rnal, 13- 7 gener ator, 2-7, 1 3 - 7, 13-8 inte rna l, and i dle mo de, 14-4, 14-5 p has es, in te rn al, 2- 8 CLR ins t r uct ion , A-2, A- 1 0 , A-41, A-47, A-52 CLRB ins truction, A-2, A- 11, A-41, A-47 , A-5 2 CLRC ins truction, A-3, A- 11, A-46, A-51 , A-5 7 CLRVT ins truc t ion, A- 3, A- 1 1, A-46, A- 51, A- 5 7 CMP ...
8XC1 96MC, MD , MH USER ’ S MANUA L Index -4 re-enabli n g the compa re event, 11-20, 11-22 reloa ding the wave form gene rator, 11-20, 11-23, C-16 resetting the timer in com p are m ode, 11- 21 resetting the time r s , 1 1 - 21, 1 1 - 23 selecting the c apture/compa r e e vent, 11-19 selecting t he compar e event, 1 1-22 selec ting the t ime ba ...
Index -5 INDEX Hype rt ext ma nua ls and data she et s, down loading, 1- 10 I Idle mode , 2-1 1 , 13-13, 14-4–14- 5 ente rin g , 14 -5 pin s tatus, B-2 3, B-25 timeout control , 11-7 IDLPD instruction, A-2, A-16, A-46, A-51, A-57 IDLPD #1, 1 4 - 5 IDLPD #2, 1 4 - 6 illegal operand, 13-9, 1 3 - 1 2 Imme diate a d d ressi ng, 3-6 INC inst ruc tion, ...
8XC1 96MC, MD , MH USER ’ S MANUA L Index -6 JVT instr uct ion, A-3, A- 5, A-23, A-4 5, A-50, A-5 6 L Lat ency‚ See bus- ho l d protocol ‚ interrupt s LCAL L inst ruction, A- 3, A-23, A-45, A-5 0 , A-56 LD ins t r uction, A- 2, A-23, A-44, A-49, A-55 LDB ins t ruction, A- 2, A-23, A-44, A-49, A- 55 LDBS E instruc tion, A-3, A-24, A-44, A- 49, ...
Index -7 INDEX ORB ins t ructio n , A-2, A- 28, A- 4 3, A-48, A- 53 Osc illa tor and powerdown mode, 14-5 exte rna l cryst al , 13-6 on-chip, 13-5 OTP ROM control l ing ac c e ss to inte rnal memory, 16 -3–16-6 control l ing f etches from e xternal memory, 16 -6–16-7 memor y map, 16-2 program ming, 16-1–1 6 - 33 S ee a lso progra mming modes ...
8XC1 96MC, MD , MH USER ’ S MANUA L Index -8 SFRs, 6-6, 14-3 P ort 3, B -18 address ing, 6-14 idle , powe rdown, reset status, B-23, B-2 5 op er a t i o n, 6-15–6 -1 6 ove rvie w, 6-1 pin c o nfi guration, 6 -14 struc ture, 6-15 P ort 4, B -18 address ing, 6-14 idle , powe rdown, reset status, B-23, B-2 5 op er a t i o n, 6-15–6 -1 6 ove rvie ...
Index -9 INDEX instruc tions, A-51, A- 57 inte r ru p t lat ency, 5 -11 inte r r u p t proces s in g flow, 5 -2 routine, defined, 5-1 serial I/O m odes, 5-37– 5 - 58 single transf er mode, 5 - 2 7 synchron o us s e rial I/O receive m ode, 5-47 –5-50 synchron ou s se ri al I/ O transmit mode, 5-43 –5-46 vectors , memor y locat io ns, 4-3 S ee ...
8XC1 96MC, MD , MH USER ’ S MANUA L Index -10 FREQ_CNT, 8-4, C-22 FREQ_GEN, 8-3, C-23 GEN_ CON, 13-9, C-24 grouped b y mo dule s, C-1 INT_MASK, 5-15, C-25 INT_MASK1, 5-16 , 7-2, C-26 INT_PEND, 5 - 2 1, 7-3, C-27 INT_PEND1 , 5-22, 7-3, C-28 naming c onventions, 1-4 ONES_ REG, C-29 P0_PIN, 6- 3 , 6-4 P1_MOD E consider ations, 6-12 P1_PIN, 6- 3 , 6- ...
Index-11 INDEX RST inst ructi o n, 3-11, 13-9, 13-12, A-3, A-31, A-46, A-5 1 , A-57 Run -time p rogramming , 1 6-32–1 6-33 code exa mple , 16- 33 RXD, B-20 and SIO port mo de 0, 7-5, 7-7 and SIO port mo de s 1, 2, and 3, 7-7 S Sampled input, B- 13 SBUF x _RX, C-70 SBUF x _TX, C-70 SCAL L i nst ruct io n, A-3, A- 3 1, A-41, A-47, A-50, A-55, A-56 ...
8XC1 96MC, MD , MH USER ’ S MANUA L Index -12 SJMP instruc tion, A-2, A-36, A-41 , A-47, A-49, A-55 SKIP i n st ructio n , A-2, A -36, A-41, A-51, A-57 Slave progra mmi n g mode, 1 6 - 1 5– 16-24 address /comma nd decoder routine, 1 6-19, 16- 20 a lg o ri th m, 16-19 –1 6-24 circ uit, 16-16 dump-word routine, 1 6 - 19, 16-23 ente rin g , 16 - ...
Index-13 INDEX Timi ng d i agra ms 16-bit data bus, 15-15 8-bit dat a bus, 1 5- 17 BUSWIDTH, 15-12 READY, 1 5 - 1 9 sys t e m bus t imin g , 15-3 2 Timing r equirem ents BUSWIDTH, 15-13 READY, 1 5 - 1 8 TRAP ins truc t ion, 5-6, A-2, A-39, A- 46, A- 50, A-55, A-56 TRAP interr upt, 5-4 TXD, B-21 and SIO port mo de 0, 7-5 U UART, 2-9, 7- 1 Unera sabl ...
8XC1 96MC, MD , MH USER ’ S MANUA L Index -14 WSR values an d direct ad d r esses, 4- 15 WORD, defined, 3-2 Worl d Wi de Web, 1-11 WR#, B-22 idle , powe rdown, reset status, B-23, B-2 5 WRH#, B-22 Wr ite cy cl es 16-bit data bus, 15-14 8-bit dat a bus, 1 5- 16 W ri te strob e mo de exa mple s ystem, 15-26 s ign al s, 15 -2 5 WRL#, B-22 WSR, 4-13, ...
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