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Access PCI-DIO-24D(H) - page 1
10623 Roselle Street, San Diego, CA 92 121 • (858) 550-9559 • FAX (858) 550-7322 contactus@accesi o.com • www.accesio.com MODEL PCI-DIO-24D(H) USER MANUAL FILE: MPCI-DIO-24DH.G1o ...
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Notice The information in this document is provided for reference only. ACCES does n ot assume any liability arising out of the application or use of the informat ion or products d escribed herein. This docu ment may contain or reference information and p roducts protec ted by copyrig hts or patents and does not convey any license under the patent ...
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Warranty Prior to shipment, ACCES equipment is thoroughly insp ected and tested to applicable sp ecifications. However, should equipment failure occu r, ACCES assu res its customers that prompt service a nd support will be available. All equipment originally manufactu red by ACCES which is found to be defective will be repaired or replaced subjec t ...
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Table of Contents Chapter 1: Introduction ................................................................................................. 5 Specifications ............................................................................................................ 7 Figure 1-1: Card D or H Block Diagram ............................................ ...
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Chapter 1: Introduction Features • 24 Bits of Digital Input/Output. • All 24 I/O Lines Buffered on the Card. • I/O Buffers Can Be Tri-st ated under Program Control. • Four and Eight Bit Ports Independently Selectabl e for I/O. • Pull-Ups on I /O Lines. Pull Do wn resistor s may be installed at the factory (**per p ort 8 bit**) • Resetta ...
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output use according to direction assignment from a control register in the PPI. Further, if a jumper i s properly placed on the card, the tristate buffers may be enabled/di sabled under program control. (See the Option Selection section to follow.) I/O wiring connections for t he H card are via a 50- pin conne ctor on the back plate of the card. F ...
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Specifications Digital Inputs (TTL Compatible) • Logic High: 2.0 to 5.0 VDC • Logic Low: -0.5 to +0.8 VDC • Load: ±20 μ A Digital Outputs • Logic High: 2.0 VDC min., source 32 ma • Logic Low: 0.55 VDC max., sink 64 ma Optional Counter/Timers • Type: 82C54 programmable in terval counters (up to three) • Output drive: Source 2.5 mA, s ...
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Figure 1-1: Card D or H Block Diagra m Manual PCI-DIO-24DH 8 ...
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Optional Counter/Timers These cards have options to includ e one, two, or th ree 82C54 counter(s) that each inclu de three 16-bit counter/timers factory configured in an optimal m odule for use as ev ent counters, frequency output, pulse width, and frequency measurem ent. See the Block Diagr am which show s one 82C54 counter. If your card has one o ...
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Access PCI-DIO-24D(H) - page 10
Chapter 2: Installation A printed Quick-Start Guide (QSG) is pa cked with the card for your convenience. If you’ve already performed the steps from the QSG, you may find this chapter to be redundant and may skip forward to begin developing your application. The software provided with this card is on CD and mu st be installed onto your hard disk p ...
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Access PCI-DIO-24D(H) - page 11
Hardware Installation 1. Make sure to set switches and jump ers from eith er the Option Selection section of this manual or from the suggestions of SETUP.EXE. 2. Do not install card into the computer until the software has been fully installed. 3. Turn OFF computer power AND unplug AC power from the system. 4. Remove the computer cover. 5. Carefull ...
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Access PCI-DIO-24D(H) - page 12
Chapter 3: Option Selection Refer to the setup programs on the CD provided with the card. Also, refer to the Block Diagram and the Option Selection Map when reading this section of the manual. Buffer Mode Jumper A means of enabling or disabling (t ristating) the 74ABT245B input/output buffers under program control is provided at the jumper position ...
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3.9" 4. 8" IR Q D I NT EXT IR Q T IN T E N IN T S E L 0 TST BEN Figure 3-1 : Option Selection Map version D Figure 3-2: Option Selection Map version H Manual PCI-DIO-24DH 13 ...
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Chapter 4: Address Selection These cards use one ad dress space and occupy sixteen I/O locations. The S03 (whi ch has 3 counters) version takes up 32 I/O locations. PCI architecture is Plug-and-Play. This mean s t hat the BIOS or Operating System determines the resources assigned to PCI card s rather than the user se lecting those resou rces with s ...
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Access PCI-DIO-24D(H) - page 15
Chapter 5: Software There are sample program s provided with the card in C, Pascal, QuickBASIC, and several Windows languages. DOS samples are located in the DOS directory and Win dows samples are located in the WIN32 directory. The follo wing paragraphs descri be the setup program and the 16- and 32-bit utility drivers. SETUP.EXE This program is s ...
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Access PCI-DIO-24D(H) - page 16
Chapter 6: Programming These cards are I/O-m apped devices that are easily configure d from any language and any language can easily perform digital I/O through the card's port s. This is especially true if the form of the data is byte or word wide. All references to the I/O por ts would be in absolute port addressin g. Developing Your Applica ...
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Access PCI-DIO-24D(H) - page 17
These cards use an 825 5-5 PPI to provide a total of 24 bits input/output capability. The card is de signed to use the PPI in Mode 0 wherein: a. There are two 8-bit groups (A and B) and two 4-bit group s (C Hi and C Lo). b. Any port can be configured as an input or an output. c. Outputs are latched. d. Inputs are not latched. The PPI contains a Con ...
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c. Now, if any of the ports are to be set as output s, you may set the values to that port with the outputs still in the tristate condition. (If all ports are to be set as inputs, this step is not necessary.) d. If data bit D7 is low when the control byte is written, ONLY the associated buffer controller is addressed. If, for example, a control byt ...
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Programming Example (C) The following program fra gment in C language illustrates the fore going: const BASE_ADDRESS 0x300; outportb(BASE_ADDRESS +3, 0x89); /* This instruction sets the m ode to Mode 0, ports A and B as output, and port C as input. Since bit D7 is high, the output buffers are set to tristate condition. See item b. above.*/ outportb ...
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Enabling/Disabling I/O Buffers When using the tristate mode (Jumper in the TST posit ion), the method to disable the I/O buffers involved writing a control word to th e Control Register at Ba se Address +3. This control word wa s required to have bit D7 (the most significant bit) set. That meant that the PPI translated it as an "active mode se ...
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Access PCI-DIO-24D(H) - page 21
Chapter 7: 8254 Counter/Timer These cards have the opti on of one, two, or three 82C54 cou nter(s) that each include three 16-bit counter/timers factory configured in an optimal m odule for use as ev ent counters, frequency output, pulse width, and frequency measurem ent (See Block Diagram). Each counter can be prog rammed to any count as low as 1 ...
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Counter/Timer Registers Base + 10 Write/Read: Counter#A0 When writing, th is registe r is used to load a count value into the counter. The transfer is eit her a single or double byte transfer, depending on the control byte written to the counter control register at BASE ADDRESS +13. If a double byte transfer is used, then the least- significant byt ...
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Programming the 8254 The counters are prog rammed by writing a control byte into the counter control regi ster. Refer to the previous register map for the base addresse s of the counters and the co unter control register. The control byte specifies the counter to be programmed, the co unter mode, the type of read/write operati on, and the modulus. ...
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Reading and Loading the Counters If you attempt to read the counters on the fly when there is a high input frequen cy, you will most likely get erroneous data. This is partly cause d by carries rippling through the counte r during the read operation. Also, the low and high bytes are read se quentially rather than simultaneously and, thus, it is pos ...
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1st Read: Status byte 2nd Read: Low byte of latched data 3rd Read: High byte of latched data After any latching operation on a counter, the conten ts of its hold registe r must be read before any subsequent latches of that counter will have any effect. If a status latch command is issued be fore the hold register is read, then the first read will r ...
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Pulse Width The Pulse Width function will measure the width of an applie d event from its rise to its fall (effectively one half the period). The Base Address of the card is required as input to the function . The signal should be applied to the CLOCK IN pin of the card. Software latency will be affected by the operating system and will set a limit ...
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Access PCI-DIO-24D(H) - page 27
Chapter 8: Connector Pin Assignments The H card has a 50-pin conne ctor provided on the ba ck plate of these cards for I/O connections. The mating connector is an AMP type 1-746 285-0 or equiva lent. Connector pin assignment s are listed below. Assignment Pin Assignment Pin PC7 1 Counter A0 Freq In 2 PC6 3 Ctr A1 P.W.I. (Gate) 4 PC5 5 Counter A2 Fr ...
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The D card has a 37-pin D-su b connector provided on the back plate of these cards for I/O conne ctions. If all three counters are present, pin 20 is counter C2 ' s frequency output. Otherwise, pin 20 is fused +5V power. Assignment Pin Assignment Pin Ground 1 Digital IRQ Disable 2 C2 Freq Out / Fused +5V 20 Port C 7 Hi 3 Ground 21 Port C 6 Hi ...
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Access PCI-DIO-24D(H) - page 29
Customer Comments If you experience any problems with this manual or ju st want to give us some feedback, please email us at: manuals@accesio.com. Please detail any errors you find and in clude your mailing address so that we can send you any manual updates. 10623 Roselle Street, San Dieg o CA 92121 Tel. (858)550-9559 FAX (8 58)550-7322 www.accesio ...
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