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Cypress CY7C1320BV18の取扱説明書

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  • Cypress CY7C1320BV18 - page 1

    18-Mbit DDR-II SRAM 2-W ord Burst Architecture CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05621 Rev . *D Revised June 2, 2008 Features ■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz clock for h ...

  • Cypress CY7C1320BV18 - page 2

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 2 of 31 Logic Block Diagram (CY7C1316BV18) Logic Block Diagram (CY7C1916BV18) Wri te Reg Wri te Reg CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 8 16 8 NWS [1:0] V REF Write Add. Decod ...

  • Cypress CY7C1320BV18 - page 3

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 3 of 31 Logic Block Diagram (CY7C1318BV18) Logic Block Diagram (CY7C1320BV18) Wri te Reg Write Reg CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 18 36 18 BWS [1:0] V REF Write Add. Deco ...

  • Cypress CY7C1320BV18 - page 4

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 4 of 31 Pin Configuration The pin configuration for CY7C1316BV18, CY7C1916 BV18, CY7C1318BV18, and CY7 C1320BV18 follow . [1] 165-Ball FBGA (13 x 15 x 1 .4 mm) Pinout CY7C1316BV18 (2M x 8) 123456789 10 11 A CQ NC/72M A R/W NWS 1 K NC/144M LD A NC/36M CQ B ...

  • Cypress CY7C1320BV18 - page 5

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 5 of 31 CY7C1318BV18 (1M x 18) 123456789 10 11 A CQ NC/72M A R/W BWS 1 K NC/14 4M LD A NC/36M CQ B NC DQ9 NC A NC/288M K BWS 0 AN C N C D Q 8 C NC NC NC V SS AA 0A V SS NC DQ7 NC D NC NC DQ10 V SS V SS V SS V SS V SS NC NC NC E NC NC DQ1 1 V DDQ V SS V SS ...

  • Cypress CY7C1320BV18 - page 6

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 6 of 31 Pin Definitions Pin Name IO Pin Descripti on DQ [x:0] Input Output- Synchronous Dat a Input Output S ignals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins dri ve out t he requested data during a ...

  • Cypress CY7C1320BV18 - page 7

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 7 of 31 CQ Output Clock CQ Referenced with Respect to C . This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II. In single clock mo de, CQ is generated with resp ect to K. The timing for the echo clocks is sh ...

  • Cypress CY7C1320BV18 - page 8

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 8 of 31 Functional Overview The CY7C1316BV18, CY7C1916BV18, CY7C1318 BV18, and CY7C1320BV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface. Accesses are initiated on the ri sing edge of the positive input clock (K). All synchronous inp ...

  • Cypress CY7C1320BV18 - page 9

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 9 of 31 Programmable Impedan ce An external resistor , RQ, must be connected between the ZQ pin on the SRAM and V SS to enabl e the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of th e intended line impedance d riven by ...

  • Cypress CY7C1320BV18 - page 10

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 10 of 31 T ruth T able The truth table for the CY7C1316BV18, CY7C1 916BV1 8, CY7C1318BV18, and CY7C1320BV18 follows . [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ DQ Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edge ...

  • Cypress CY7C1320BV18 - page 11

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 1 1 of 31 Write Cycle Descriptions The write cycle description tabl e for CY7C1916BV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the data portion of a write sequence, th e single byte (D [8:0] ) is written into the device. L – L–H During th ...

  • Cypress CY7C1320BV18 - page 12

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 12 of 31 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.1 -1900. The T AP operates using JEDEC standard 1.8V I ...

  • Cypress CY7C1320BV18 - page 13

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 13 of 31 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It a lso places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the ...

  • Cypress CY7C1320BV18 - page 14

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 14 of 31 T AP Controller St ate Diag ram The state diagram for the T AP controller follows. [9] TEST -LOGIC RESET TEST -LOGIC / IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 ...

  • Cypress CY7C1320BV18 - page 15

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 15 of 31 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 ? ...

  • Cypress CY7C1320BV18 - page 16

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 16 of 31 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Setu ...

  • Cypress CY7C1320BV18 - page 17

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 17 of 31 Identification R egi ster Definitions Instruction Field Va l u e De scription CY7C1316BV18 CY7C1916BV18 CY7 C1318BV18 CY7C1320BV18 Revision Numb er (31:29) 000 000 000 000 V ersion numbe r . Cypress Device ID (28:12) 1 10 10100010000101 1 10101000 ...

  • Cypress CY7C1320BV18 - page 18

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 18 of 31 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 27 1 1H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26 N 2 9 9 G 5 6 6 A 8 3 1 J 3 7P 30 1 1F 57 5B 84 2J 4 7N 31 1 1G 58 5A 85 3K 57 R 3 2 9 F 5 9 4 A 8 6 3 J 6 8R 33 10F 6 ...

  • Cypress CY7C1320BV18 - page 19

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 19 of 31 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW). ...

  • Cypress CY7C1320BV18 - page 20

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 20 of 31 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ..................... ............ –65°C to +150°C Ambient T empe r at ur e with Power Appl i ed ...

  • Cypress CY7C1320BV18 - page 21

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 21 of 31 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 575 mA (x9) 580 (x18) 600 (x36) 635 167 MHz (x8) 490 mA (x9) 490 (x18) 510 (x36) 540 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V ...

  • Cypress CY7C1320BV18 - page 22

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 22 of 31 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V , V DDQ = 1.5V 5 pF C CLK Clock I ...

  • Cypress CY7C1320BV18 - page 23

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 23 of 31 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parameter Description 300 MHz 278 MHz 250 MHz 20 0 MH z 167 MHz Unit Min Max Min Max Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [22] ...

  • Cypress CY7C1320BV18 - page 24

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 24 of 31 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.45 – – 0.45 – –0.45 ? ...

  • Cypress CY7C1320BV18 - page 25

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 25 of 31 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 6, 27, 28 ] READ READ READ NOP NOP WRITE WRITE NOP 1 23 4 56 7 8 9 1 0 Q40 t KHCH t CO t t HC t t HA t SD t HD t KHCH t SD t HD DON’ T CARE UNDEFINED t CLZ t DOH t CHZ SC t KH t KHKH ...

  • Cypress CY7C1320BV18 - page 26

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 26 of 31 Ordering Information Not all of the speed, package, and temper ature ranges are available. Please cont act your local sale s representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Package T ...

  • Cypress CY7C1320BV18 - page 27

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 27 of 31 250 CY7C131 6BV18-250BZC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1916BV18-250BZC CY7C1318BV18-250BZC CY7C1320BV18-250BZC CY7C1316BV18-250BZXC 51-85180 165-Ball F ine Pitch Ball Grid Array (13 x 15 x 1.4 mm) ...

  • Cypress CY7C1320BV18 - page 28

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 28 of 31 167 CY7C131 6BV18-167BZC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1916BV18-167BZC CY7C1318BV18-167BZC CY7C1320BV18-167BZC CY7C1316BV18-167BZXC 51-85180 165-Ball F ine Pitch Ball Grid Array (13 x 15 x 1.4 mm) ...

  • Cypress CY7C1320BV18 - page 29

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 29 of 31 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BO ...

  • Cypress CY7C1320BV18 - page 30

    CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev . *D Page 30 of 31 Document History Page Document Title: CY7C1316BV18/CY7C1916BV18/CY7C1318BV1 8/CY7C132 0BV18 , 18-Mbit DDR-II SRAM 2-Word Burst Ar- chitecture Document Number: 38-05621 Rev . ECN No. Submission Date Orig, o f Change Description of Chan ge ** 252474 ...

  • Cypress CY7C1320BV18 - page 31

    Document Number: 38-05621 Rev . *D Revised June 2, 2008 Page 31 of 31 DDR RAMs and QDR RAMs comprise a new fam ily of products develope d by Cypress, Hitachi, IDT , Micron, NEC, a nd Samsung. All p rodu ct and company names mentione d in this document are the trademarks of the ir respective holders. CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320 ...

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