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Cypress CY7C1381FV25 - page 1
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05547 Rev . *E Revised Feburary 14, 2007 Features • Supports 133 MHz bus operations • 512K x 36/1M x 18 co mmon IO • 2.5V ...
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Cypress CY7C1381FV25 - page 2
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 2 of 28 Logic Block Diagram – CY7C1381DV25 /CY7C1381FV25 [3 ] (512K x 36) Logic Block Diagram – CY7C1383DV25 /CY7C1383FV25 [3 ] (1M x 18) ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARR ...
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Cypress CY7C1381FV25 - page 3
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 3 of 28 Pin Configurations A A A A A 1 A 0 NC NC V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SSQ DQ ...
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Cypress CY7C1381FV25 - page 4
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 4 of 28 Pin Configurations (continued) 234 5 6 7 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ AA DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS V ...
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Cypress CY7C1381FV25 - page 5
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 5 of 28 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1381DV25 (512 K x 36) 234 567 1 A B C D E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D ...
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Cypress CY7C1381FV25 - page 6
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 6 of 28 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one of the address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 [2] are sampled active. A ...
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Cypress CY7C1381FV25 - page 7
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 7 of 28 Functional Overview All synchronous inpu ts pass through input registers controlled by the rising edge of the clock. Maximum a ccess delay from the clock rise (t CDV ) is 6.5 ns (133 MHz device). The CY7C1381DV25/CY7C 1383DV25/CY7C13 81FV25/ CY7C1383FV2 ...
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Cypress CY7C1381FV25 - page 8
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 8 of 28 and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precauti on, the data lines are tri-stated once a write cycle is detected, regardless of the st ate of OE . Single Write Accesses Initiated by ADSC This write access is ...
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Cypress CY7C1381FV25 - page 9
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 9 of 28 T ruth T able [4, 5, 6, 7, 8] Cycle Description Address Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X L X L X X X L-H T ri-S tate Deselected Cycle, Power Down None L L X L L X X X X L-H T ri-S tate Deselect ...
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Cypress CY7C1381FV25 - page 10
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 10 of 28 T ruth T able for Read/Write [4, 9] Function (CY7C1381DV25 /CY7C1381FV25) GW BWE BW D BW C BW B BW A Read H H X X X X Read H L H H H H Write Byte A (DQ A , DQP A )H L H H H L Write Byte B (DQ B , DQP B )H L H H L H Write Bytes A, B (DQ A , DQ B , DQP A ...
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Cypress CY7C1381FV25 - page 11
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 1 1 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1381DV25/C Y7C1383DV25 incorporate s a serial boundary scan test access port (T AP). This part is fully compliant with 1 14 9.1. T he T AP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. Th ...
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Cypress CY7C1381FV25 - page 12
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 12 of 28 When the T AP controller is in the Capture -IR state, the two least significant bits are loaded with a binary ‘01’ pattern to allow for fault isolati on of the board level serial test data path. Byp ass Register T o save time wh en serially shiftin ...
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Cypress CY7C1381FV25 - page 13
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 13 of 28 the T AP co ntroller , it will direct ly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will en able the output buffers to drive the output bus. When LOW , this bit will place the outp ...
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Cypress CY7C1381FV25 - page 14
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 14 of 28 2.5V T AP AC T est Conditions Input pulse levels ........................ .............. ...........V SS to 2.5V Input rise and fall time .............. ............ ........... ................ 1 ns Input timing reference levels ...................... ...
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Cypress CY7C1381FV25 - page 15
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 15 of 28 Identification Codes Instruction Code Description EXTEST 0 00 Captures IO ring contents. Places th e boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 0 01 Loads the ID register with the vendor ID code and plac ...
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Cypress CY7C1381FV25 - page 16
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 16 of 28 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N 7 3 2 C 1 1 6 2 D 2 3 N10 33 A1 1 63 E2 4P 1 1 3 4 B 1 1 6 4 F 2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7R 9 3 7 A 9 6 7 H 3 8P 9 3 8 B 9 6 8 J 1 9P 1 ...
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Cypress CY7C1381FV25 - page 17
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 17 of 28 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guideline s, not tested. S torage T emperature .............. ................. .. –65°C to +150°C Ambient T emperature wit h Power Applied ........... ...
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Cypress CY7C1381FV25 - page 18
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 18 of 28 Cap acit ance [18] Parameter Description T est Conditio ns 100 TQFP Package 1 19 BGA Package 165 FBGA Package Unit C IN Input Capa citance T A = 25°C, f = 1 MHz, V DD /V DDQ = 2.5V 58 9 p F C CLK Clock In put Cap acit ance 5 8 9 pF C IO Input/Output C ...
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Cypress CY7C1381FV25 - page 19
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 19 of 28 Switching Characteristics Over the Operating Range [19, 20] Parameter Descriptio n 133 MHz 100 MHz Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the first Access [21] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 2.1 2.5 ns t CL ...
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Cypress CY7C1381FV25 - page 20
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 20 of 28 Ti ming Diagrams Read Cycle Timing [25] t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH t CDV t OEHZ t CDV Single READ BURST READ t OEV t OELZ t CHZ Burst wraps around to its initial state t ADVH t ADVS ...
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Cypress CY7C1381FV25 - page 21
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 21 of 28 Write Cycle T iming [25, 26] Ti ming Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3) A2 A3 Extended BURST WRITE D(A2 ...
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Cypress CY7C1381FV25 - page 22
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 22 of 28 Read/Write Cycle Timing [25, 27, 28] Ti ming Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WRITE D(A3) A3 A4 BURST READ Back-to-Back READs High-Z Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) t WEH t WES t OEHZ t DH ...
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Cypress CY7C1381FV25 - page 23
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 23 of 28 ZZ Mode T iming [29, 30] Ti ming Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 29. Device must be deselected when entering ZZ sleep mode. See Cy ...
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Cypress CY7C1381FV25 - page 24
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 24 of 28 Ordering Information Not all of the speed, package, and temperature rang es are availabl e. Please contact your local sales representa tive or visit www .cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part and Packag ...
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Cypress CY7C1381FV25 - page 25
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 25 of 28 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm ...
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Cypress CY7C1381FV25 - page 26
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 26 of 28 Figure 2. 1 19-Ball BGA ( 14 x 22 x 2.4 mm) (51-851 15) Package Diagrams (continued) 51-851 15-*B [+] Feedback ...
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Cypress CY7C1381FV25 - page 27
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 27 of 28 © Cypress Semicon ductor Corpor ation, 2006- 2007. The inform ation cont ained herein is subject to change wi thout notic e. Cypress Semiconductor Corporation assumes no respon sibility for the use of any circuitr y other than circuitr y embodied in a ...
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Cypress CY7C1381FV25 - page 28
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev . *E Page 28 of 28 Document History Page Document Title: CY7C1381DV25/CY7C1383DV25/CY7C13 81FV25/CY7C1 383FV25, 18-Mb it (512K x 36/1M x 18) Flow-Through SRAM Document Number: 38-05547 REV . ECN NO. Issue Date Orig . of Change Description of Change ** 254518 See ECN RKF ...
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