日本語 dropdown-ico

Cypress CY7C1410AV18の取扱説明書

29ページ 0.65 mb
ダウンロード

ページに移動 of 29

Summary
  • Cypress CY7C1410AV18 - page 1

    36-Mbit QDR™-II SRAM 2-W ord Burst Architecture CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05615 Rev . *E Revised June 13, 2 008 Features ■ Separate independent read and write data ports ❐ Supports concurrent t ...

  • Cypress CY7C1410AV18 - page 2

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 2 of 29 Logic Block Diagram (CY7C1410A V18) Logic Block Diagram (CY7C1425A V18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 8 21 16 8 NWS [1: ...

  • Cypress CY7C1410AV18 - page 3

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 3 of 29 Logic Block Diagram (CY7C1412A V18) Logic Block Diagram (CY7C1414A V18) 1M x 18 Array CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 18 20 36 18 BWS ...

  • Cypress CY7C1410AV18 - page 4

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 4 of 29 Pin Configuration The pin configuration for CY7C1410A V18, CY7C1425 A V18, CY7C141 2A V18, and CY7C1414A V18 fo llow . [1] 165-Ball FBGA (15 x 17 x 1 .4 mm) Pinout CY7C1410A V18 (4M x 8) 123456789 10 11 A CQ NC/72M A WPS NWS 1 K NC/144M RPS AA C Q B ...

  • Cypress CY7C1410AV18 - page 5

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 5 of 29 CY7C1412A V18 (2M x 18) 123456789 10 11 A CQ NC/144M A WPS BWS 1 K NC/288M RPS A NC/72M CQ B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AAA V SS NC Q7 D8 D NC D1 1 Q10 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V SS V SS V DD ...

  • Cypress CY7C1410AV18 - page 6

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 6 of 29 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during val id write opera tions. CY7C1410A V18 - D [7:0] CY7C1425A V18 - D [8:0] CY7C1412A V18 - D [17:0] CY7C141 ...

  • Cypress CY7C1410AV18 - page 7

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 7 of 29 CQ Echo Clock CQ Referenced with Respect to C . This is a free - running clock and is synchronized to the Input clock for output data (C) of the QDR-II. In the single clock mode , CQ is generate d with respect to K. The timings for the echo clocks i ...

  • Cypress CY7C1410AV18 - page 8

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 8 of 29 Functional Overview The CY7C1410A V18, CY7C1425A V18, CY7C1412A V18, an d CY7C1414A V18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to rea d operations and the write port is dedicated to write ...

  • Cypress CY7C1410AV18 - page 9

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 9 of 29 Programmable Impedan ce An external resistor , RQ, must be connected between the ZQ pin on the SRAM and V SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of th e intended line impedance d riven by the ...

  • Cypress CY7C1410AV18 - page 10

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 10 of 29 T ruth T able The truth table for CY7C1410A V18, CY7C1425A V18 , CY7C1412A V18, and CY7C1 414A V18 follows. [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising ed ge of K ; input write data on K and K rising edges. ...

  • Cypress CY7C1410AV18 - page 11

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 1 1 of 29 Write Cycle Descriptions The write cycle description tabl e for CY7C1425A V18 follows. [2, 8] BWS 0 K K Comments L L–H – During the Data portion of a write sequence, the single byte (D [8:0] ) is writ te n in to the device. L – L–H Du ring ...

  • Cypress CY7C1410AV18 - page 12

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 12 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.1-1900. The T AP operates usin g JEDEC standard 1.8V IO ...

  • Cypress CY7C1410AV18 - page 13

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 13 of 29 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the Sh ...

  • Cypress CY7C1410AV18 - page 14

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 14 of 29 T AP Controller St ate Diagram The state diagram for the T AP controller follows. [9] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 ...

  • Cypress CY7C1410AV18 - page 15

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 15 of 29 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 μ ...

  • Cypress CY7C1410AV18 - page 16

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 16 of 29 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Setup ...

  • Cypress CY7C1410AV18 - page 17

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 17 of 29 Identification R egi ster Definitions Instruction Field Va l u e Descrip tion CY7C1410A V18 CY7C1425A V18 CY7C1412 A V18 CY7C1414A V18 Revision Numb er (31:29) 000 000 000 000 V ersion number . Cypress Device ID (28:12) 1 10100 1 10100001 1 1 1 101 ...

  • Cypress CY7C1410AV18 - page 18

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 18 of 29 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 87 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61 4B 89 1K 6 8R 34 1 1E 62 3A ...

  • Cypress CY7C1410AV18 - page 19

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 19 of 29 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operation s. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (All other inputs can be HIGH or LOW). ? ...

  • Cypress CY7C1410AV18 - page 20

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 20 of 29 Maximum Ratings Exceeding maximum ratings may im pair the useful life of the device. These user guidelines are not tested. S torage T emperature ......................... ... ... .. . –65°C to +150°C Ambient T emperature with Powe r App lied .. ...

  • Cypress CY7C1410AV18 - page 21

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 21 of 29 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs S tatic 250MHz (x8) 400 mA (x9) 400 (x18) 420 (x36) 475 200MHz (x8) 350 mA (x9) 350 (x18) 370 (x36) 420 167MHz (x8) 330 ...

  • Cypress CY7C1410AV18 - page 22

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 22 of 29 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Condition s Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V , V DDQ = 1.5V 5 pF C CLK Clock I ...

  • Cypress CY7C1410AV18 - page 23

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 23 of 29 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [22] 111 m s t CYC t KHKH K Clock and C ...

  • Cypress CY7C1410AV18 - page 24

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 24 of 29 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 6, 27, 28 ] K 1 2 34 5 8 10 6 7 K RPS WPS A D READ READ WRITE WRITE WRITE NOP READ WRITE NOP 9 A0 t KH t KHKH t KL t CY C tt HC t SA t HA t SD t HD SC t t SA t HA t SD t HD A6 A5 A3 A4 ...

  • Cypress CY7C1410AV18 - page 25

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 25 of 29 Ordering Information Not all of the speed, package and temperature range s are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Pack age Diagram Package T y ...

  • Cypress CY7C1410AV18 - page 26

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 26 of 29 167 CY7C1410A V18-167BZC 5 1-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1425A V18-167BZC CY7C1412A V18-167BZC CY7C1414A V18-167BZC CY7C1410A V18-167BZXC 51-851 95 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 ...

  • Cypress CY7C1410AV18 - page 27

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 27 of 29 Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85195 A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TO ...

  • Cypress CY7C1410AV18 - page 28

    CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 28 of 29 Document History Page Document Title: CY7C1410A V18/CY7C1425A V18/CY7C1412A V1 8/CY7C1414A V18, 36-Mbit QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05615 REV . ECN NO. SUBMISSION DA TE ORIG . OF CHANGE DESCRIPTION OF CHANGE ** 2473 ...

  • Cypress CY7C1410AV18 - page 29

    Document #: 38-05615 Rev . *E Revised June 13, 2008 Page 29 of 29 QDR RAMs and Qua d Data Ra te RA Ms comprise a ne w fam i ly of pr od uct s developed by Cypress, Hit a chi, IDT , NEC, and Samsung. A l l p r oduct and company names mentioned in this d ocume nt a re the tradem arks of their respective holders. CY7C1410A V18, CY7C1425A V18 CY7C1412A ...

メーカー Cypress カテゴリー Computer Hardware

Cypress CY7C1410AV18のメーカーから受け取ることができるドキュメントは、いくつかのグループに分けられます。その一部は次の通りです:
- #BRANDの図面#
- CY7C1410AV18の取扱説明書
- Cypressの製品カード
- パンフレット
- またはCypress CY7C1410AV18の消費電力シール
それらは全部重要ですが、デバイス使用の観点から最も重要な情報は、Cypress CY7C1410AV18の取扱説明書に含まれています。

取扱説明書と呼ばれる文書のグループは、Cypress CY7C1410AV18の取り付け説明書、サービスマニュアル、簡易説明書、またはCypress CY7C1410AV18のユーザーマニュアル等、より具体的なカテゴリーに分類されます。ご必要に応じてドキュメントを検索しましょう。私たちのウェブサイトでは、Cypress CY7C1410AV18の製品を使用するにあたって最も人気のある説明書を閲覧できます。

関連する取扱説明書

Cypress CY7C1410AV18デバイスの取扱説明書はどのようなものですか？
取扱説明書は、ユーザーマニュアル又は単に「マニュアル」とも呼ばれ、ユーザーがCypress CY7C1410AV18を使用するのを助ける技術的文書のことです。説明書は通常、全てのCypress CY7C1410AV18ユーザーが容易に理解できる文章にて書かれており、その作成者はその分野の専門家です。

Cypressの取扱説明書には、基本的な要素が記載されているはずです。その一部は、カバー/タイトルページ、著作権ページ等、比較的重要度の低いものです。ですが、その他の部分には、ユーザーにとって重要な情報が記載されているはずです。

1. Cypress CY7C1410AV18の説明書の概要と使用方法。説明書にはまず、その閲覧方法に関する手引きが書かれているはずです。そこにははCypress CY7C1410AV18の目次に関する情報やよくある質問、最も一般的な問題に関する情報を見つけられるはずです。つまり、それらはユーザーが取扱説明書に最も期待する情報なのです。
2. 目次。Cypress CY7C1410AV18に関してこのドキュメントで見つけることができる全てのヒントの目次
3. Cypress CY7C1410AV18デバイスの基本機能を使うにあたってのヒント。 Cypress CY7C1410AV18のユーザーが使い始めるのを助けてくれるはずです。
4. トラブルシューティング。Cypress CY7C1410AV18に関する最も重要な問題を診断し、解決するために役立つ体系化された手続き
5. FAQ。よくある質問
6. 連絡先。一人では問題を解決できない場合に、その国におけるCypress CY7C1410AV18のメーカー/サービスへの連絡先に関する情報。

Cypress CY7C1410AV18についてご質問がありますか？

次のフォームを使用してください

見つけた説明書を読んでもCypress CY7C1410AV18の問題を解決できない場合、下記のフォームを使用して質問をしましょう。ユーザーのどなたかがCypress CY7C1410AV18で同様の問題を抱えていた場合、その解決方法を共有したいと考えるかもしれません。

画像のテキストを入力してください

Captcha
新しい画像

コメント (0)