-
Cypress CY7C1470V33 - page 1
72-Mbit (2M x 36/4M x 18/1M x 72) Pi p elined SRAM with NoBL™ Architecture CY7C1470V33 CY7C1472V33 CY7C1474V33 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05289 Rev . *I Revised June 20, 2006 Features • Pin-comp atible and functionally equiv a le nt to ZBT™ • Supp ...
-
Cypress CY7C1470V33 - page 2
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 2 of 29 A0, A1, A C MODE CE1 CE2 CE3 OE READ LOGIC DQ s DQ P a DQ P b DQ P c DQ P d DQ P e DQ P f DQ P g DQ P h D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 BURST LOGIC A0 ...
-
Cypress CY7C1470V33 - page 3
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 3 of 29 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A CE 1 CE 2 BW a CE 3 V DD V SS C ...
-
Cypress CY7C1470V33 - page 4
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 4 of 29 Pin Configurations (continued) 234 56 7 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d A V DDQ BW d BW a CLK WE V SS V SS V SS V SS V DDQ V SS V DD V SS V SS V SS ...
-
Cypress CY7C1470V33 - page 5
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 5 of 29 Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 12 34 5 6 7 89 1 1 10 DQg DQg DQg DQg DQg DQg DQg DQg DQc DQc DQc DQc NC DQPg DQh DQh DQh DQh DQd DQd DQd DQd DQPd DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd DQb DQb DQb DQb DQb DQb DQ ...
-
Cypress CY7C1470V33 - page 6
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 6 of 29 Pin Definitions Pin Name I/O T ype Pin Description A0 A1 A Input- Synchronous Address In p uts used to select one of the add re ss locations . Sampled at the rising edge of the CLK. BW a BW b BW c BW d BW e BW f BW g BW h Input- Synchronous Byte Write Select Inputs, acti ...
-
Cypress CY7C1470V33 - page 7
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 7 of 29 Functional Overview The CY7C1470V33, CY7 C1472V33, and CY7C1474V33 are synchronous-pipel ined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions. All synchronous inp uts pass through input registers controlled by the rising ed ...
-
Cypress CY7C1470V33 - page 8
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 8 of 29 On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d, e,f,g,h /D QP a,b,c,d,e,f,g,h for CY7C1474V33, DQ a,b,c,d /DQP a,b, c,d for CY7C1470V33 & DQ a,b /DQP a,b for CY7C1472V33) (or a subset for b yte write operations, see Write Cycle Description table ...
-
Cypress CY7C1470V33 - page 9
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 9 of 29 Notes: 1. X = “Don't Care”, H = Lo gic HIGH, L = Logic L OW , CE stands fo r ALL Chip Ena bles active. BWx = 0 signifies at least one Byte W rite Select is active, BW x = V alid signifies that the desired byte writ e selects are as se rted, see Write Cycle Descr ...
-
Cypress CY7C1470V33 - page 10
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 10 of 29 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1470 V3 3) WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Wri te Byte a – (D Q a and DQP a ) L HHH L Wri te Byte b – (D Q b and DQP b )L H H L H Write Bytes b, a L H H L L Write B ...
-
Cypress CY7C1470V33 - page 11
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 1 1 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1470V33, CY7C1 472V33, and CY7C1474V33 incorporates a serial bounda ry scan test access port (T AP). This port operates in accordance with IEEE S tandard 1 149.1-19 90 but does not have the set of functions requ ired fo ...
-
Cypress CY7C1470V33 - page 12
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 12 of 29 Instruction Register Three-bit instructions can be serially loaded into the instruction register . This register is loa ded when it is placed betwe en the TDI and TDO ba lls as show n in the T ap Contro ller Block Diagram. Upon power-up, the instruction register is load ...
-
Cypress CY7C1470V33 - page 13
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 13 of 29 possible to capture all other signals an d simply ignore the value of the CLK captured in the bounda ry scan reg ister . Once the data is captured, it is possible to shift out the data by putting the T AP into the Shift-DR state. This places the boundary scan register b ...
-
Cypress CY7C1470V33 - page 14
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 14 of 29 3.3V T AP AC T est Conditions Input pulse levels ............... .............. .............. ..... V SS to 3.3V Input rise and fall times ......... ........ ... ... ........... ... ........... ... 1 ns Input timing referenc e levels .................... .............. ...
-
Cypress CY7C1470V33 - page 15
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 15 of 29 Identification Register Definitions Instruction Field CY7C1470V33 (2M x 36) CY7C1472V33 (4M x 18) CY7C1474V33 (1M x 72) Description Revision Number (31:29) 000 000 000 Describes the versi on number Device De pth (28:24 ) [12] 0101 1 0101 1 0101 1 Reserved for internal u ...
-
Cypress CY7C1470V33 - page 16
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 16 of 29 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165 -Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1C 1 2 1 R 3 4 1 J 1 1 6 1 B 7 2 D1 22 P2 42 K10 62 B6 3E 1 2 3 R 4 4 3 J 1 0 6 3 A 6 4D 2 2 4 P 6 4 4H 1 1 6 4 B 5 5E 2 2 5 R 6 4 5 G 1 1 6 5 A 5 6F 1 2 6 R 8 4 ...
-
Cypress CY7C1470V33 - page 17
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 17 of 29 Boundary Scan Exit Order (1M x 72) Bit # 2 09-Ball ID Bit # 209-Ball ID Bit # 209 -Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 U10 85 B1 1 2A 2 3 0 T 2 5 8 T 1 1 8 6 B 1 0 3B 1 3 1 U 1 5 9 T 1 0 8 7 A 1 1 4B 2 3 2 U 2 6 0 R 1 1 8 8 A 1 0 5 C 1 33 V1 61 R10 89 A7 6C 2 3 4 V ...
-
Cypress CY7C1470V33 - page 18
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 18 of 29 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65 °C to +150°C Ambient T emp erature with Power Applied ........... ............................ ...... –5 ...
-
Cypress CY7C1470V33 - page 19
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 19 of 29 Cap acit ance [15] Parameter Description T est Co nd itions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C ADDRESS Address Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 6 6 6 pF C DA T A Da ta Input Capacit ance 5 5 5 pF C CTRL Control In put Ca ...
-
Cypress CY7C1470V33 - page 20
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 20 of 29 Switching Characteristics Over the Operating Range [16, 17] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [18] V CC (typical) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cycle T ime 4.0 5.0 6.0 ns F MAX Maximum Op ...
-
Cypress CY7C1470V33 - page 21
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 21 of 29 Switching W aveforms Read/Write/T iming [22, 2 3, 24] Notes: 22. For this waveform ZZ is tied LOW. 23. When CE is LOW , CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is H IGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 24. Order of the Burst sequence is determi ...
-
Cypress CY7C1470V33 - page 22
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 22 of 29 NOP , ST ALL and DESELECT Cycles [2 2, 23 , 25 ] ZZ Mode T iming [26, 27] Notes: 25. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a pause. A W r ite is not performed during this cycle. 26. Device must be deselected when entering Z ...
-
Cypress CY7C1470V33 - page 23
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 23 of 29 Ordering Information Not all of the speed, package and temperature ranges are av ailable. Please contact your local sales representative or visit www .cyp ress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Part and Package T ype Operating R ...
-
Cypress CY7C1470V33 - page 24
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 24 of 29 250 CY7C1470V33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1472V33-250AXC CY7C1470V33-250BZC 51-85165 165-ball Fine-Pitc h Ball Grid Array (15 x 17 x 1.4 mm) CY7C1472V33-250BZC CY7C1470V33-250BZXC 51-85165 165-ball Fine-Pi tc ...
-
Cypress CY7C1470V33 - page 25
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 25 of 29 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLU ...
-
Cypress CY7C1470V33 - page 26
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 26 of 29 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10.00 14.00 B C D E F G H ...
-
Cypress CY7C1470V33 - page 27
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 27 of 29 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n ...
-
Cypress CY7C1470V33 - page 28
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 28 of 29 Document History Page Document Title: CY7C1470 V33/CY7C1472V33/CY 7C14 74V3 3 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 REV . ECN No. Issue Date Orig. of Change Description of Ch ange ** 1 14676 08/06/02 PKS New ...
-
Cypress CY7C1470V33 - page 29
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 29 of 29 *H 416221 See ECN RXU Converted from Prelimin ary to Final Changed address of Cypress Semico nductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed Three-state to Tri-state Changed the description of I X from Input Loa d Cu ...
Cypress CY7C1470V33についてご質問がありますか？
次のフォームを使用してください
見つけた説明書を読んでもCypress CY7C1470V33の問題を解決できない場合、下記のフォームを使用して質問をしましょう。ユーザーのどなたかがCypress CY7C1470V33で同様の問題を抱えていた場合、その解決方法を共有したいと考えるかもしれません。