日本語 dropdown-ico

Cypress CY7C1317CV18の取扱説明書

31ページ 0.7 mb
ダウンロード

ページに移動 of 31

Summary
  • Cypress CY7C1317CV18 - page 1

    18-Mbit DDR-II SRAM 4-W ord Burst Architecture CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-07161 Rev . *D Revised June 18, 2008 Features ■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz clock for ...

  • Cypress CY7C1317CV18 - page 2

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 2 of 31 Logic Block Diagram (CY7C1317CV18) Logic Block Diagram (CY7C1917CV18) Writ e Reg CLK A (18:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W DQ [7:0] Output Logic Reg. Reg. Reg. 16 8 32 8 NWS [1:0] V REF Write Add. Dec ...

  • Cypress CY7C1317CV18 - page 3

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 3 of 31 Logic Block Diagram (CY7C1319CV18) Logic Block Diagram (CY7C1321CV18) Writ e Reg CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 36 72 18 BWS [1:0] V REF Write Add. Decode 36 20 ...

  • Cypress CY7C1317CV18 - page 4

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 4 of 31 Pin Configuration The pin configuration for CY7C1317CV18, CY7C191 7CV18, CY7C1319CV18, and CY7C1321CV18 follo w . [1] 165-Ball FBGA (13 x 15 x 1 .4 mm) Pinout CY7C1317CV18 (2M x 8) 123456789 10 11 A CQ NC/72M A R/W NWS 1 K NC/144M LD A NC/36M CQ B ...

  • Cypress CY7C1317CV18 - page 5

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 5 of 31 CY7C1319CV18 (1M x 18) 123456789 10 11 A CQ NC/72M A R/W BWS 1 K NC/14 4M LD A NC/36M CQ B NC DQ9 NC A NC/288M K BWS 0 AN C N C D Q 8 C NC NC NC V SS AA 0 A 1 V SS NC DQ7 NC D NC NC DQ10 V SS V SS V SS V SS V SS NC NC NC E NC NC DQ1 1 V DDQ V SS V ...

  • Cypress CY7C1317CV18 - page 6

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 6 of 31 Pin Definitions Pin Name IO Pin Descripti on DQ [x:0] Input Output- Synchronous Dat a Input Output S ignals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins dri ve out t he requested data during a ...

  • Cypress CY7C1317CV18 - page 7

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 7 of 31 CQ Output Clock CQ Referenced with Respect to C . This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II. In single clock mo de, CQ is generated with resp ect to K. The timing for the echo clocks is s ...

  • Cypress CY7C1317CV18 - page 8

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 8 of 31 Functional Overview The CY7C1317CV18, CY7C1917CV18, CY7C1 319CV18, and CY7C1321CV18 are synchronous pi pelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DO ...

  • Cypress CY7C1317CV18 - page 9

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 9 of 31 after the read(s), the st ored data from the ear lier write i s writte n into the SRAM array . This is called a posted write. If a read is performed o n the same address on which a write is performed in the previous cycle, the SRAM reads out the m ...

  • Cypress CY7C1317CV18 - page 10

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 10 of 31 Application Example Figure 1 shows two DDR-II used in an applicatio n. Figure 1. Application Example T ruth T able The truth table for the CY7C1317CV18, CY7C1917 CV18, CY7C13 19CV18, and CY7C1321CV18 fo llows. [2, 3, 4, 5, 6, 7] Operation K LD R/ ...

  • Cypress CY7C1317CV18 - page 11

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 1 1 of 31 Burst Address T able (CY7C1319CV18, CY7C1321CV18) First Address ( External) Second Addres s (Internal) Third Address (I nternal) Four th Address (Intern al) X..X00 X..X01 X..X10 X..X1 1 X..X01 X..X10 X..X1 1 X..X00 X..X10 X..X1 1 X..X00 X..X01 X ...

  • Cypress CY7C1317CV18 - page 12

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 12 of 31 Write Cycle Descriptions The write cycle description t able for CY7C1 321CV18 follows. [2, 8] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments LLLL L – H – D u r i n g t h e d a t a p o r t i o n o f a w r i t e s e quence, all fou r bytes (D [35:0] ) ar ...

  • Cypress CY7C1317CV18 - page 13

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 13 of 31 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.1 -2001. The T AP operates using JEDEC standard 1.8V ...

  • Cypress CY7C1317CV18 - page 14

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 14 of 31 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It a lso places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the ...

  • Cypress CY7C1317CV18 - page 15

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 15 of 31 T AP Controller St ate Diag ram The state diagram for the T AP controller follows. [9] TEST -LOGIC RESET TEST -LOGIC / IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 ...

  • Cypress CY7C1317CV18 - page 16

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 16 of 31 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 ...

  • Cypress CY7C1317CV18 - page 17

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 17 of 31 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Set ...

  • Cypress CY7C1317CV18 - page 18

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 18 of 31 Identification R egi ster Definitions Instruction Field Va l u e De scription CY7C1317CV18 CY7C1917CV18 CY7 C1319CV18 CY7C1321CV18 Revision Numb er (31:29) 000 000 000 000 V ersion numbe r . Cypress Device ID (28:12) 1 101010001 1000101 1 1010100 ...

  • Cypress CY7C1317CV18 - page 19

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 19 of 31 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 84 2J 1 6 P2 9 9 G 5 7 5 B8 5 3 K 2 6N 30 1 1F 58 5A 86 3J 3 7P 31 1 1G 59 4A 87 2K 4 7 N3 2 9 F 6 0 5 C8 8 1 K 5 7R 33 10F 61 4B 89 2 L 6 8R 34 1 1E 6 ...

  • Cypress CY7C1317CV18 - page 20

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 20 of 31 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW). ...

  • Cypress CY7C1317CV18 - page 21

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 21 of 31 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ..................... ............ –65°C to +150°C Ambient T emperature wit h Pow e r App l i e ...

  • Cypress CY7C1317CV18 - page 22

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 22 of 31 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 580 mA (x9) 580 (x18) 600 (x36) 655 167 MHz (x8) 515 mA (x9) 515 (x18) 540 (x36) 600 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V ...

  • Cypress CY7C1317CV18 - page 23

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 23 of 31 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V , V DDQ = 1.5V 5 pF C CLK Clock ...

  • Cypress CY7C1317CV18 - page 24

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 24 of 31 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parameter Description 300 MHz 278 MHz 250 MHz 20 0 MH z 167 MHz Unit Min Max Min Max Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [22 ...

  • Cypress CY7C1317CV18 - page 25

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 25 of 31 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.45 – – 0.45 – –0.45 ? ...

  • Cypress CY7C1317CV18 - page 26

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 26 of 31 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29 ] K 1 2 3 4 5 6 7 8 9 10 11 12 13 A DQ C READ (burst of 4) READ (burst of 4) READ (burst of 4) NOP NOP WRITE (burst of 4) WRITE (burst of 4) NOP DON’ T CARE UNDEFINED CQ K ...

  • Cypress CY7C1317CV18 - page 27

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 27 of 31 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Package T y ...

  • Cypress CY7C1317CV18 - page 28

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 28 of 31 250 CY7C1317CV18-2 50BZC 51-85180 1 65-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1917CV18-250BZC CY7C1319CV18-250BZC CY7C1321CV18-250BZC CY7C1317CV18-250BZXC 5 1-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) ...

  • Cypress CY7C1317CV18 - page 29

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 29 of 31 167 CY7C1317CV18-1 67BZC 51-85180 1 65-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1917CV18-167BZC CY7C1319CV18-167BZC CY7C1321CV18-167BZC CY7C1317CV18-167BZXC 5 1-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) ...

  • Cypress CY7C1317CV18 - page 30

    CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 30 of 31 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW B ...

  • Cypress CY7C1317CV18 - page 31

    Document Number: 001-07161 Rev . *D Revised June 18, 2008 Page 31 of 31 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. All pr oduct and co mpany nam es mentioned i n this documen t are the tr ad emarks of their respe ctive hold ers. CY7C1317CV18, CY7C1917CV18 CY7C1319CV1 ...

メーカー Cypress カテゴリー Computer Hardware

Cypress CY7C1317CV18のメーカーから受け取ることができるドキュメントは、いくつかのグループに分けられます。その一部は次の通りです:
- #BRANDの図面#
- CY7C1317CV18の取扱説明書
- Cypressの製品カード
- パンフレット
- またはCypress CY7C1317CV18の消費電力シール
それらは全部重要ですが、デバイス使用の観点から最も重要な情報は、Cypress CY7C1317CV18の取扱説明書に含まれています。

取扱説明書と呼ばれる文書のグループは、Cypress CY7C1317CV18の取り付け説明書、サービスマニュアル、簡易説明書、またはCypress CY7C1317CV18のユーザーマニュアル等、より具体的なカテゴリーに分類されます。ご必要に応じてドキュメントを検索しましょう。私たちのウェブサイトでは、Cypress CY7C1317CV18の製品を使用するにあたって最も人気のある説明書を閲覧できます。

関連する取扱説明書

Cypress CY7C1317CV18デバイスの取扱説明書はどのようなものですか？
取扱説明書は、ユーザーマニュアル又は単に「マニュアル」とも呼ばれ、ユーザーがCypress CY7C1317CV18を使用するのを助ける技術的文書のことです。説明書は通常、全てのCypress CY7C1317CV18ユーザーが容易に理解できる文章にて書かれており、その作成者はその分野の専門家です。

Cypressの取扱説明書には、基本的な要素が記載されているはずです。その一部は、カバー/タイトルページ、著作権ページ等、比較的重要度の低いものです。ですが、その他の部分には、ユーザーにとって重要な情報が記載されているはずです。

1. Cypress CY7C1317CV18の説明書の概要と使用方法。説明書にはまず、その閲覧方法に関する手引きが書かれているはずです。そこにははCypress CY7C1317CV18の目次に関する情報やよくある質問、最も一般的な問題に関する情報を見つけられるはずです。つまり、それらはユーザーが取扱説明書に最も期待する情報なのです。
2. 目次。Cypress CY7C1317CV18に関してこのドキュメントで見つけることができる全てのヒントの目次
3. Cypress CY7C1317CV18デバイスの基本機能を使うにあたってのヒント。 Cypress CY7C1317CV18のユーザーが使い始めるのを助けてくれるはずです。
4. トラブルシューティング。Cypress CY7C1317CV18に関する最も重要な問題を診断し、解決するために役立つ体系化された手続き
5. FAQ。よくある質問
6. 連絡先。一人では問題を解決できない場合に、その国におけるCypress CY7C1317CV18のメーカー/サービスへの連絡先に関する情報。

Cypress CY7C1317CV18についてご質問がありますか？

次のフォームを使用してください

見つけた説明書を読んでもCypress CY7C1317CV18の問題を解決できない場合、下記のフォームを使用して質問をしましょう。ユーザーのどなたかがCypress CY7C1317CV18で同様の問題を抱えていた場合、その解決方法を共有したいと考えるかもしれません。

画像のテキストを入力してください

Captcha
新しい画像

コメント (0)