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Cypress CY7C1345G - page 1
CY7C1345G 4-Mbit (128K x 36) Flow Through Sync SRAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1 709 • 408-943-2600 Document Number: 38-05517 Rev . *E Revised July 15, 2007 Features ■ 128K x 36 common IO ■ 3.3V core power supply (V DD ) ■ 2.5V or 3.3V IO supply (V DDQ ) ■ Fast clock-to -out put times ...
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Cypress CY7C1345G - page 2
CY7C1345G Document Number: 38-05517 Rev . *E Page 2 of 20 Logic Block Diagram ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQ s DQP A DQP B DQP C DQP D A 0, A1, A ADV CLK ADSP ADSC BW D BW C BW B BW A BWE CE1 CE2 CE3 OE GW SLEEP CONTROL DQ A , DQP A BYTE WR ...
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Cypress CY7C1345G - page 3
CY7C1345G Document Number: 38-05517 Rev . *E Page 3 of 20 Pin Configurations 100-Pin TQFP Pi nout A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/9M A A A A A A DQP B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SSQ DQ C DQ C DQ C DQ ...
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Cypress CY7C1345G - page 4
CY7C1345G Document Number: 38-05517 Rev . *E Page 4 of 20 1 19-Ball BGA Pinout Pin Configurations (continued) 2 34 5 6 7 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ CE 2 A DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS V SS NC/576M NC ...
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Cypress CY7C1345G - page 5
CY7C1345G Document Number: 38-05517 Rev . *E Page 5 of 20 Pin Definitions Name IO Description A0, A1, A Input Synchronous Address Inpu ts Used to Select One of the 128K Address L ocations . Sampled a t the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A [1:0] feed the two-bit counter . BW A, B ...
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Cypress CY7C1345G - page 6
CY7C1345G Document Number: 38-05517 Rev . *E Page 6 of 20 Functional Overview All synchronous inputs pass through input re gisters controlled by the rising edge of the clock. Maximum access delay from th e clock rise (t CO ) is 6.5 ns (133 MHz de vice). The CY7C1345G supports secondary cache in systems using either a linear or interleaved burst seq ...
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Cypress CY7C1345G - page 7
CY7C1345G Document Number: 38-05517 Rev . *E Page 7 of 20 Burst Sequences The CY7C1345G provides an on-chip two-bit wrap around burst counter inside th e SRAM. The burst counter is fed by A [1:0] and follows either a linear or interle aved burst order . The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear bur ...
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Cypress CY7C1345G - page 8
CY7C1345G Document Number: 38-05517 Rev . *E Page 8 of 20 T ruth T able The truth table for CY7C1345G follows. [1, 2, 3, 4, 5] Cycle Descriptio n Address Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power down None H X X L X L X X X L-H T ri-St ate Deselected Cycle, Power down N o n e L L X L L XXXX L - H T r i - S t a t e ...
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Cypress CY7C1345G - page 9
CY7C1345G Document Number: 38-05517 Rev . *E Page 9 of 20 T ruth T able for Read or Write The partial truth t able for read or write follows. [1, 6] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX Read H L H H H H Write Byte (A, DQP A )H L H H H L Write Byte (B, DQP B )H L H H L H Write Bytes (B, A, DQP A , DQP B )H L H H L L Write Byte (C, DQP ...
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Cypress CY7C1345G - page 10
CY7C1345G Document Number: 38-05517 Rev . *E Page 10 of 20 Maximum Ratings Exceeding the maximum ratin gs may shorten the battery life of the device. These user guidelines are not te sted. S torage T emperature ........................ ......... –65°C to +150°C Ambient T emperat ure wit h Power Applied .......... .............. ................ ...
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Cypress CY7C1345G - page 11
CY7C1345G Document Number: 38-05517 Rev . *E Page 1 1 of 20 Cap acit ance T ested initia lly and after any design or process change that may affect these parameters. Parameter Description T est Cond itions 100 TQFP Max 11 9 B G A Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V . V DDQ = 3.3V 55 p F C CLK Clock Input Capacit an ...
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Cypress CY7C1345G - page 12
CY7C1345G Document Number: 38-05517 Rev . *E Page 12 of 20 Switching Characteristics Over the Operating Range [9, 10] Parameter Description –133 –100 Unit Min Max Min Max t POWER V DD (T ypical) to the first Access [1 1] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 2.5 4 .0 ns t CL Clock LOW 2.5 4.0 ns Output T imes t CDV Data ...
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Cypress CY7C1345G - page 13
CY7C1345G Document Number: 38-05517 Rev . *E Page 13 of 20 Timing Diagrams Figure 1 shows the read cycle timing. [15] Figure 1. Read Cy cle T iming t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH t CDV t OEHZ t CDV Single READ BURST READ t OEV t OELZ t CHZ Burst wraps around to its initial state t AD ...
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Cypress CY7C1345G - page 14
CY7C1345G Document Number: 38-05517 Rev . *E Page 14 of 20 Figure 2 shows the write cycle timing. [15, 16] Figure 2. Write Cycle T iming Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3) A2 A3 Extended BURST W ...
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Cypress CY7C1345G - page 15
CY7C1345G Document Number: 38-05517 Rev . *E Page 15 of 20 Figure 3 shows the read and write timing. [16, 17, 18] Figure 3. Read/W rite Timing Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WRITE D(A3) A3 A4 BURST READ Back-to-Back READs High-Z Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) t WEH t WES t OE ...
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Cypress CY7C1345G - page 16
CY7C1345G Document Number: 38-05517 Rev . *E Page 16 of 20 Figure 4 shows the ZZ mode timing. [19, 20] Figure 4. ZZ Mode Timing Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes: 19. Device must be deselected when entering ZZ mode. See “ ...
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Cypress CY7C1345G - page 17
CY7C1345G Document Number: 38-05517 Rev . *E Page 17 of 20 Ordering Information Not all of the speed, package and temperature range s are availabl e. Please contact your local sales representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Part and Package T ype Operating Range 133 CY7C1345G-13 ...
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Cypress CY7C1345G - page 18
CY7C1345G Document Number: 38-05517 Rev . *E Page 18 of 20 Package Diagrams Figure 5. 10 0-Pin Thi n Plastic Qu ad Flatpack (14 x 20 x 1 .4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETE ...
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Cypress CY7C1345G - page 19
CY7C1345G Document Number: 38-05517 Rev . *E Page 19 of 20 Figure 6. 1 19-Ball BGA (14 x 22 x 2.4 mm), 51-85 1 15 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.00(3X) REF. 7.62 22.00±0.20 14.00±0.20 1.27 60? ...
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Cypress CY7C1345G - page 20
Document Number: 38-05517 Rev . *E Revised July 15, 2007 Page 20 of 20 Intel and Penti um are register ed trademarks and i486 is a trademar k of Intel Corpo ration. All produ ct and compan y names mention ed in this document may be the trad emarks of their respective ho lders . CY7C1345G © Cypress Sem iconductor Corp oration, 200 4-2007. The infor ...
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