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Cypress CY14B108L - page 1
PRELIMINARY CY14B108L, CY14B108N 8 Mbit (1024K x 8/512K x 16) nvSRAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-45523 Rev . *B Revised Marc h 19, 2009 Features ■ 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 102 4K x 8 (CY14B108L) or 512K x 16 (CY14B10 ...
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Cypress CY14B108L - page 2
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 2 of 24 Pinout s Figure 1. Pin Diagram - 48 FBG A Figure 2. Pin Diag ram - 44/54-Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC A 17 A 2 A 1 NC V CC DQ 4 NC DQ 5 DQ 6 NC DQ 7 NC A 15 A 14 A 13 A 12 HSB 3 2 6 ...
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Cypress CY14B108L - page 3
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 3 of 24 T able 1. Pin Definitions Pin Name I/O T yp e Description A 0 – A 19 Input Address Inputs Used to Sele ct one of the 1, 048,576 bytes of the nvSRAM fo r x8 Configuration . A 0 – A 18 Address Inputs Used to Select one of the 524,288 words of the n vSRAM for x16 Configur ...
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Cypress CY14B108L - page 4
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 4 of 24 Device Operation The CY14B108L/CY1 4B108N nvSRAM is made up of two functional components paired in the same physical cell. They are a SRAM memory cell and a n onvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is tran ...
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Cypress CY14B108L - page 5
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 5 of 24 STORE operation is complet ed, the CY14B108L/CY14B108N remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power Up) During power up or after any low power condition (V CC <V SWITCH ), an internal RECALL re ques ...
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Cypress CY14B108L - page 6
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 6 of 24 T able 2. Mod e Selection CE WE OE, BHE , BLE [3] A 15 - A 0 [5] Mode IO Power H X X X Not Selected Output High Z S tandby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRA ...
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Cypress CY14B108L - page 7
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 7 of 24 Preventing AutoStore The AutoS t ore function is disabled by initiating an AutoS tore disable sequence. A sequence of read ope rations is performed in a manner si milar to the Software STORE initiation. T o initiate the AutoS tore disa ble sequence, the followi ng sequence ...
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Cypress CY14B108L - page 8
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 8 of 24 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These us er guidelines are not teste d. S torage T emperature ............. .............. ....... –65 ° C to +150 ° C Maximum Accumulated S torage Time At 150 ° C Ambient T emperature ...
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Cypress CY14B108L - page 9
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 9 of 24 AC T est Conditions Input Pulse Levels ...... ............... .............. ........... ...... 0V to 3V Input Rise and Fall T imes (10% - 90%) ................. ....... < 3 ns Input and Output T iming Reference Levels ........ ............ 1.5V Dat a Retention and Endu ...
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Cypress CY14B108L - page 10
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 10 of 24 AC Switching Characteristics Parameters Descriptio n 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Min Ma x SRAM Read Cy cle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [1 1] t RC Read Cycle T ime 2 0 25 45 ns t AA [12] t AA Address Acc ...
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Cypress CY14B108L - page 11
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 1 1 of 24 Figure 6. SRAM Read Cycl e #2: CE and OE Controlled [3, 1 1, 15] Figure 7. SRAM Write Cycle #1: WE Controlled [3, 14, 15, 16] Ad dress V alid Ad dre ss Data Output Ou tput Data Vali d Stand by Active High Impedance CE OE BHE, BLE I CC t HZCE t RC t ACE t AA t LZC E t DO ...
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Cypress CY14B108L - page 12
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 12 of 24 Figure 8. SRAM W rite Cycle #2: CE Controll ed [3, 14, 15, 16] Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled [3, 14, 15, 16] D ata Ou tput Da ta Inpu t In put D ata Valid High Impedance Addr ess Val id Ad dre ss t WC t SD t HD BHE , BLE WE CE t SA t SCE t HA t BW ...
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Cypress CY14B108L - page 13
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 13 of 24 AutoStore/Power Up RECALL Parameters Descrip tion 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [17] Power Up RECALL Duration 20 20 20 ms t STORE [18] ST ORE Cycle Duration 8 8 8 ms t DELA Y [19] T ime Allowed to Complete SR AM Cycle 20 25 25 ns V SWITCH Low V ...
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Cypress CY14B108L - page 14
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 14 of 24 Sof tware Controlled STORE/RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [22, 23] Parameters Descrip tion 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC STORE/RECALL Initiation Cycle T ime 20 25 45 ns t SA ...
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Cypress CY14B108L - page 15
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 15 of 24 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB T o Output Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Wid th 15 15 15 ns t SS [24, 25] Soft Sequence Processing T ime 100 100 100 μ s S ...
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Cypress CY14B108L - page 16
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 16 of 24 T ruth T able For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Inputs/Outputs [2 ] Mode Power H X X High Z Deselect/Power down S tandby L H L Data Out (DQ 0 –DQ 7 ); Read Active L H H High Z Output Disabled Active L L X Data ...
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Cypress CY14B108L - page 17
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 17 of 24 Ordering Information Speed (ns) Ordering Code Package Diagram Package T ype Operating Range 20 CY14B108L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B108L-ZS20XC 51-850 87 44-pin TSOP II CY14B108L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B108L-ZS20XI 51-85087 44- ...
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Cypress CY14B108L - page 18
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 18 of 24 45 CY14B108L-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B108L-ZS45XC 51-850 87 44-pin TSOP II CY14B108L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B108L-ZS45XI 51-85087 44-p in TSOP II CY14B108L-BA45XCT 51-85128 48-ball FBGA Commercial CY14B108L-BA45XC 51-85128 48 ...
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Cypress CY14B108L - page 19
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 19 of 24 Part Numbering Nomenclature Option: T - T ape & Reel Blank - S td. S peed: 20 - 20 ns 25 - 25 ns Data Bus: L - x8 N - x16 Density: 108 - 8 Mb V oltage: B - 3.0V Cypress CY 14 B 108L-ZS P 20 X C T NVSRAM 14 - Auto Store + Software STORE + Hardware STORE T emperature: C ...
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Cypress CY14B108L - page 20
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 20 of 24 Package Diagrams Figure 15. 44-Pin TSOP II (51-85087) MAX MIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016) 0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 ( ...
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Cypress CY14B108L - page 21
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 21 of 24 Figure 16. 48 -Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-8512 8) Package Diagrams (continued) A 1 A1 CORNER 0.75 0.75 Ø0.30±0.05(48X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.21±0.05 1.20 MAX C SEATING PLANE 0.53±0.05 0.25 C 0.15 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3.7 ...
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Cypress CY14B108L - page 22
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 22 of 24 Figure 17. 54-Pin TSOP II (51-85160) Package Diagrams (continued) 51-85160 -** [+] Feedback ...
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Cypress CY14B108L - page 23
PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev . *B Page 23 of 24 Document History Page Document Title: CY14B108L/CY14B108N 8 Mbit (1024K x 8/512K x 16) nvSRAM Document Number: 001-45523 Rev . ECN No. Orig. of Change Submission Date Descriptio n of Change ** 2428826 GVCH See ECN New Data Sheet *A 2520023 GVCH/PYRS 06/23/08 Updated I CC1 ...
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Cypress CY14B108L - page 24
Document #: 001-45523 Rev . *B Revised March 19, 2009 Page 24 of 24 AutoS tore and QuantumT rap are registered trademar ks of Cypress Semicondu ctor Corporation . All product s and company na mes mentio ned in this document are the trademark s of their respe ctive holders. PRELIMINARY CY14B108L, CY14B108N © Cypress Semicondu ctor Corporati on, 200 ...
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