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Manual SBE HighWire HW400c/2

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  • SBE HighWire HW400c/2 - page 1

    HighWire HW400c/2 User Reference Guide Rev 1.0 ___________________HighWire HW400c/2 User Reference Guide M8275, Rev 1.0 October 10, 2006 Copyright 2006, SBE, Inc. Page i ...

  • SBE HighWire HW400c/2 - page 2

    HighWire HW400c/2 User Reference Guide Rev 1.0 Copyright ©2006 by SBE, Inc. All rights reserved. No part of this manual may be repro duced by any means without written permission from SBE, Inc., except that the purchaser may copy necessary portions for internal use only. While every effort has been made to ensu re the accuracy of this manual, SBE ...

  • SBE HighWire HW400c/2 - page 3

    HighWire HW400c/2 User Reference Guide Rev 1.0 Revision History Revision Date Changes 1.0 October 10, 2006 Initial Release October 10, 2006 Copyright 2006, SBE, Inc. Page iii ...

  • SBE HighWire HW400c/2 - page 4

    HighWire HW400c/2 User Reference Guide Rev 1.0 THIS PAGE IS INTENTIONALLY LEFT BLANK October 10, 2006 Copyright 2006, SBE, Inc. Page iv ...

  • SBE HighWire HW400c/2 - page 5

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table of Contents Revision History ............................................................................................................................ iii Table of Contents ......................................................................................................................... ...

  • SBE HighWire HW400c/2 - page 6

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.2 MV64462 System Controller .............................................................................................. 17 3.2.1 System Bus ................................................................................................................ 17 3.2.2 Dual Data Rate (DDR) SDRAM ......... ...

  • SBE HighWire HW400c/2 - page 7

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.6.7 IPMI System Power Supply ...................................................................................... 42 3.6.8 IPMI Firmware EEPROMs ....................................................................................... 42 3.6.9 Zircon PM Reset ......................................... ...

  • SBE HighWire HW400c/2 - page 8

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.4.3 Reading BCM5388 Register ...................................................................................... 65 4.4.4 Writing a BCM5388 Register .................................................................................... 65 5 Linux on the HW400c/2 and Host system ..................... ...

  • SBE HighWire HW400c/2 - page 9

    HighWire HW400c/2 User Reference Guide Rev 1.0 List of Figures Figure 1. HW400c/2 Block Diagram ........................................................................................................... 3 Figure 2. The HW400c/2 PTMC Processing Platform ................................................................................ 8 Figure 3. HW4 ...

  • SBE HighWire HW400c/2 - page 10

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 14. Layer 2 Switch Port Assignments .............................................................................................. 27 Table 15. Compact PCI connector J3 pin out ............................................................................................. 30 Table 16. Mezzanine Car ...

  • SBE HighWire HW400c/2 - page 11

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 48. Warm Reset Register (WRR) Offset address 0x17 ..................................................................... 58 Table 49. SPI Page Register (SPR) Offset Address 0x1A ......................................................................... 58 Table 50. SPI Address Register (SAR) Offset ...

  • SBE HighWire HW400c/2 - page 12

    HighWire HW400c/2 User Reference Guide Rev 1.0 Conventions The following conventions are used in this docum ent: A # following a signal name, e.g., INTA #, represents an active low signal. A / preceding a signal name, e.g., /INTA represents an active low signal. 0x preceding a number represents a Hexadecimal value. A number in “ ” preceded by H ...

  • SBE HighWire HW400c/2 - page 13

    HighWire HW400c/2 User Reference Guide Rev 1.0 1 ABOUT THIS MANUAL This manual is technical reference fo r the HighWire HW400c/2 Gigabit Switched PTMC Processing Platform for CompactPCI. This manual is intended for those who are installing the HW400c/2 into a system. The HighWire HW400c/2 User Reference Manual includes the following: • Introducti ...

  • SBE HighWire HW400c/2 - page 14

    HighWire HW400c/2 User Reference Guide Rev 1.0 2 INTRODUCTION The HW400c/2 is a flexible high-performan ce core processing platform for building powerful processor enabled CompactPCI (C PCI) telephony and data communications I/O solutions. Advanced features on the HW400c/2 include two PCI Telecom Mezzanine Card (PTMC) sites for CT Bus enabled I/O i ...

  • SBE HighWire HW400c/2 - page 15

    HighWire HW400c/2 User Reference Guide Rev 1.0 I2C Co nfi g. ROM Micr ow ire Se r i a l EE PRO M SRA M Bo o t RO M Dis k o n Ch ip Tem p Se n s o rs Flas h Mem or Sys te m C o nt ro lle r Di s c ov ery I II J1 PCI J2 PCI- 64 IPMI C ontro lle r Tem p S ens or s Flas h Mem or y J3 PSB J4 H .110 J5 Rea r I/ O La ye r 2 Et he r net Swi tc h H.110 L Con ...

  • SBE HighWire HW400c/2 - page 16

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.3 Handling Procedures The HW400c/2 board uses CMOS components that can be easily damaged by static electrical discharge. To avoid damage, familiarize yourself with electrostatic discharge (ESD) procedures, whic h include the following precautions: • The board should be handled only b y tr ained ser ...

  • SBE HighWire HW400c/2 - page 17

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.5 Returns/Service Before returning any equipment for service, you must obtain a Return Material Authorization (RMA) number from SBE: TEL: 800-925-2666 (Toll free, USA) TEL: +925-355-2000 (Outside of USA) FAX: +925-355-2020 Ship all returns to SBE’s USA service center: SBE, Inc. 4000 Executive Parkw ...

  • SBE HighWire HW400c/2 - page 18

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.7 Mean Time Between Failures (MTBF) The Mean Time Between Failure (MTBF) of SBE, Inc’s HW400c/2 was calculated per Telcordia Technical Reference TR-332 Issue 6 , December 1997. The following specific parameters were used: Prediction method: Method I (Parts count procedure) Application conditions: C ...

  • SBE HighWire HW400c/2 - page 19

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.8 Regulatory Agency Certifications The HW400c/2 complies with the requirements listed below. 2.8.1 Safety • IEC60950 International product safety pending • IEC60950 pending • UL60950 pending • Certified Body (CB) Report pending 2.8.2 US and Canadian Emissions • FCC Part 15 Class B pending ? ...

  • SBE HighWire HW400c/2 - page 20

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.10 Physical Properties The Highwire 400c/2 is compliant with the mechanical specifications of PCMIG 2.0. Table 2 lists the physical dimensions of the HW400c/2 product. Figure 2 shows the physical profile of the HW400c/2 board. Table 2. HW400c/2 Physical Dimensions Length: 9.2 inches (233.68 mm) Width ...

  • SBE HighWire HW400c/2 - page 21

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.1 HW400c/2 Front Panel The HW400c/2 CompactPCI front panel has custom cut outs with the appropriat e thickness to accommodate two PTMC bezels (with EMC gaskets), two RJ-45 connectors, blue Hot Swap LED, green power LED, and status LEDs. Figure 3 below shows an illustration of the front panel. Figu ...

  • SBE HighWire HW400c/2 - page 22

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.2 Part number and serial number oards are marked with the manufacturing part number and assembly revision. This is marked on a label and affixed to the top of the board. d to e secondary side of the board. .10.3 Bus Keying TMC. I 2.10.3.2 PTMC Site f key posts installed on e HW400c/2. The key post ...

  • SBE HighWire HW400c/2 - page 23

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.4 Power Requirements The power requirements of the HW400c/2 are defined for two environments: • CompactPCI VIO of 5.0v (see Table 3) • CompactPCI VIO set 3.3v (see Table 4). 1. All voltages are required. 2. The CompactPCI VIO has no effect on the local PC I bus VIO (PTMC sites), which is fix e ...

  • SBE HighWire HW400c/2 - page 24

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.5 Switches The HW400c/2 contains single switch that is necessary for normal operation. The switch is an integral part of the lower ej ector handle inside the front panel, and is used along with the blue LED (see Figure 3) and the Linear Systems LTC1644, for hot swap. The switch is connected to the ...

  • SBE HighWire HW400c/2 - page 25

    HighWire HW400c/2 User Reference Guide Rev 1.0 3 FUNCTIONAL BLOCKS The HW400c/2 has six major functional blocks – the PowerPC processor, system controller, CT Bus interface, Ethernet sw itch, PTMC expansion sites, and the IPMI controller. The following sections describe these functional blocks in greater detail. Additional features such as the co ...

  • SBE HighWire HW400c/2 - page 26

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.1.2 Console port The front panel console port is connected through the MV64462 via a Linear Systems LTC1386 EIA-562 (low voltage EIA-232) tran sceiver. The console port is an RJ45 modular connector mounted on the front panel using t hree wire (Tx, Rx, GND) EIA- 232 at 9600 baud, 8N1 (8 bits, No parit ...

  • SBE HighWire HW400c/2 - page 27

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 7 describes the pin out of J8 and J9. So me of the pins listed are for Factory use only. Table 7. J8 and J9 pin out Header Pin Label Usage 1 O N/C. The “o” indicates pin one 2 SCL TWSI IPMB SCL, for Factory use only 3 none N/C. Just below the “J8” header title. 4 SDA TWSI IPMB SDA, for Fa ...

  • SBE HighWire HW400c/2 - page 28

    HighWire HW400c/2 User Reference Guide Rev 1.0 Figure 7. Optional Reset/NMI switch 3.1.4 COP/JTAG Port s. The J6 header can also e used to access the JTAG chain for the entire board. The COP/JTAG port uses 3.3V signaling. A 16-pin header (J6, see Figure 2, and Figure 8) and a 6-pin header (JX6) are provided on the HW400c/2 board for conn ecting to ...

  • SBE HighWire HW400c/2 - page 29

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table functions .1 Jumper 8. J7 pin 3.1.5 Pins Label Usage 1-2 PWR Forces board “late power” to switch “ON” at power- up 3-4 IGNP Forces board to operate as if no Host PCI bus is present 5-6 FAC a) Sets “FACT” bit in BSR register for use by so b) Enables writes to Microwire EEPROM lower ftw ...

  • SBE HighWire HW400c/2 - page 30

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.3 Host PCI B or and CompactPCI host, as well as between the PTMC ites and the CompactPCI host. The MV64462 device acts as a PCI-to-PCI bridge he HW400c/2 supports a 64-bit-wide bus operating at 33 or 66 MH z. PCI-X d; however 100/133 MHz operation is not su pported. 3.2.3.1 Operation s nt on the ba ...

  • SBE HighWire HW400c/2 - page 31

    HighWire HW400c/2 User Reference Guide Rev 1.0 If a PCI-X 133 card is installed in S ite B, it may be forced to 100 MHz, by installing the LPCI jumper at (see Section 3 .1.5). o st PCI bus, that is, the two uses can operate at different speeds and bus widths. from being installed by a voltage key residing at each site (see Section .10.3). 3.2.5 Ser ...

  • SBE HighWire HW400c/2 - page 32

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 9. Microwire EEPROM Contents, Factory Area Word Address Bits 15-8 (MSB) Typical Value Bits 7-0 (LSB) Typical Value 0x00 Payload Length (word s) 0x20 Format 0x03 0x01 CRC32 Byte 2 0xCC CRC3 2 for address 0x00 and 0x02-0x0F 0xCC 0x02 CRC32 Byte 4 0xCC CRC32 Byte 3 0xCC 0x03 Subsystem Vendor ID 0x76 ...

  • SBE HighWire HW400c/2 - page 33

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 10. Microwire EEPROM Contents, Uboot Area Word Address Bits 15-8 (MSB) Typical Value Bits 7-0 (LSB) Typical Value 0x10 Board IP Address byte 1 0xA8 Board IP Address byte 0 0xC0 0x11 Board IP Address byte 3 0x0A Board IP Address byte 2 0x01 0x12 Gateway IP Address byte 1 0xA8 Gateway IP Addres s b ...

  • SBE HighWire HW400c/2 - page 34

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.6 MV64462 Ethernet Interface The MV64462 contains an Ethernet MAC, which provides a MAC-to-MAC connection to port 7 of the on-board Broadcom BMC5388 layer 2 Ethernet switch (see Table 14). The connection is made via the RGMII ports on each device. The operating speed of the RGMII port is 125 MHz. 3 ...

  • SBE HighWire HW400c/2 - page 35

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.7.4 CT Bus Controller The Agere T8110L CT bus controller on the HW400c/2 board is accessed and programmed via the device bus. It also has a data bus width of 16 bits. Burst reads/writes are not supported by the T8110L. See Section 3.3 for details about the CT Bus Controller functions. 3.2.7.5 CPLD ...

  • SBE HighWire HW400c/2 - page 36

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.10 Multi-Purpose Port (MPP) Usage The MV64462 Discovery III includes a 32-bit Multi-Purpose Port (MPP) that can be used for a variety of possible functions. The HW400c/2 board uses the MPP for the serial Console Port signals (front-panel RJ-45), REQ and GNT signals for the local PCI bus, I2C EEPROM ...

  • SBE HighWire HW400c/2 - page 37

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.3 Computer Telephony Bus Controller The HW400c/2 includes the Agere T8110L CT Bus Controller to control TDM bus switching between the backplane (CompactPCI J4 connector) and the local bus, which is connected to the JN3 conn ector on each of the two PTMC sites. 3.3.1 H.110 Interface (T8110L) The Agere ...

  • SBE HighWire HW400c/2 - page 38

    HighWire HW400c/2 User Reference Guide Rev 1.0 Figure 10. Local CT Bus Clocking Block Diagram Control for the local “A” and “B” bus drivers is provided by bits 4, 5, 6, and 7 in the Clock Select Register (CSR). Refer to Section 4.2.1 for further details. Figure 11 shows the implementation. Figure 11. Local CT Bus Clock Generation October 10 ...

  • SBE HighWire HW400c/2 - page 39

    HighWire HW400c/2 User Reference Guide Rev 1.0 The T8110L can be programmed such that its local frame reference (LREF [3:2]) puts are used to generate all of the TDM bus clocks and syncs. The T8110L Local ble 13. LREF [3:2] Assignments in Clock Reference Inputs have been assigned to the PTMC JN3 H.110 clock pins as shown in Table 13. Ta LREF input ...

  • SBE HighWire HW400c/2 - page 40

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.4.1 Switch Re 3.4.2 MV64462 S s the HW400c/2 can be accessed via the 000 Mbps and is a rced from the Ethernet switch. The the receiver signals on the stem controller, and vice-versa for a direct MAC-to-MAC connection. 3.4.3 Front Panel (RJ-45) Ethernet Interface he HW400c/2 board ld ed RJ-45 (with in ...

  • SBE HighWire HW400c/2 - page 41

    HighWire HW400c/2 User Reference Guide Rev 1.0 3 ernet Ports .4.4 PT5MC Eth Each of the two PT5MC sites on the HW400c/2 have two 10/100/ 1000 Mbps ports connected to the Ethernet switch. The signals conform to PICMG ECN 2.15-1. 0- 001, using the first 24 pins of the respective JN4 conn ectors. pactPCI J3 connector using a FET switch specially desig ...

  • SBE HighWire HW400c/2 - page 42

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 1 t PC or J3 t A B C D E 5. Compac I connect pin ou 1 +5.0v +5.0v N/C N/C N/C 2 +5.0v +12v N/C N/C N/C 3 N/C N/C N/C N/C N/C 4 LED Clock N/C N/C N/C N/C 5 N/C N/C N/C N/C N/C 6 LED Data N/C N/C N/C GND 7 N/C N/C N/C N/C N/C 8 +3.3v N/C GND GND N/C 9 +3.3v N/C N/C N/C GND 10 +3.3v N/C N/C N/C N/C ...

  • SBE HighWire HW400c/2 - page 43

    HighWire HW400c/2 User Reference Guide Rev 1.0 The Link/Activity/Speed LED indication is as follows: n when the network link is up • blinking at 3 Hz for 10 Mb/s Tx or Rx; or 1000 Mb/s Tx or Rx. An optional front panel 2-high LED is provided as a status indicator for the Ethe rnet re shown as LEDs C and D in Figure 3, and by default are not prese ...

  • SBE HighWire HW400c/2 - page 44

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5 Mezzanine Card Sites The HW400c/2 board supports I/O expansi on using either one or tw o industry- standard PTMC and/or PMC modules. This section provides technical details for these expansion sites. 3.5.1 PT5MC Type Mezzanine Cards The PT5M n to the local PCI bus (32-bit, 33-133 MHz PCI or PCI-X), ...

  • SBE HighWire HW400c/2 - page 45

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.4 Mezzanine Card Power Each of the two mezzanine card sites on the HW400c/2 is allotted a portion of the total power budget for the board. For th e standard version, the mezzanine power budget is 16.2 Watts for each slot, while th e optional high-power version allows 26.4 atts for each slot. The po ...

  • SBE HighWire HW400c/2 - page 46

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.6 PTMC Jn1 and Jn2 PCI Connectors d IEEE P1386.1. Pn1 32-Bit PCI Pn2 32-Bit PCI Communication using the local PCI bus is done across two PTMC/PMC connectors, JN1 and JN2. Table 18 shows the 32-bit PCI connector pin assignment for JN1 an JN2 on the HW400c/2 as defined by the PMC specification Table ...

  • SBE HighWire HW400c/2 - page 47

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.7 PTMC Jn3 CT Bus Connector Table 19 shows the PTMC Pn3 CT Bus connector pin assignment for the HW400c/2 PTMC Configuration #2/#5 Pn3 Connector Pin Assignment for both Configuration #2 ( PT2MC) and C onfiguration #5 (PT5MC). The signal definitions for Pn3 are per the PICMG 2.15 specification. Table ...

  • SBE HighWire HW400c/2 - page 48

    HighWire HW400c/2 User Reference Guide Rev 1.0 .5.8 PTMC Jn4 LAN/User I/O Connector Table 20 (Site A) and Table 21 (Site B) show the PTMC Pn4 LAN and/or User I/O connector pin assignment for the HW400c/2 for both Configuration #2 (PT2MC User onfiguration #5 (PT5MC LAN and 3.5.8.1 M 4 s tab e co ections from TM Jn4, t pact PCI nect or P MC, the sig ...

  • SBE HighWire HW400c/2 - page 49

    HighWire HW400c/2 User Reference Guide Rev 1.0 Tabl Pn4 PT2MC Pn4 PT5MC e 20. PTMC Site A Configuration #2/#5 Pn4 Connector Pin Assignment Pin # Signal Pin Pin Pin Name Signal Name # # Signal Name Signal Name # 1 cP CI J5 E22 cPCI J5 D22 2 1 LPa DA + LPa DC + 2 3 cPCI J5 2 C2 cPCI J5 B22 4 3 LPa DA - LPa DC - 4 5 cPCI J5 A22 cPCI J5 E21 6 5 Ground ...

  • SBE HighWire HW400c/2 - page 50

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.8.2 PTMC Site B Pn4 This table shows the connections from PTMC Site B Jn4 to the Compact PCI onnector J5 and, for PT5MC, the signals for the Ethernet ports, Link Ports A and B. ble 14. ed or Table 21. PTMC Site B Configuration #2/#5 Pn4 Connector Pin Assignment Pn4 PT2MC Pn4 PT5MC c LPa (Link Port ...

  • SBE HighWire HW400c/2 - page 51

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.9 PTMC Site Voltage Keying Voltage key po n accordance with IEEE 1386. See ection 2.10.3. he HW400c/2 local PCI bus I/O voltage is 3.3 volts only . Therefore, PTMC and MC modules with 5 volt only I/O signals cannot be used on the HW400c/2 board, and residing at each site. 3.6 IPMI System Management ...

  • SBE HighWire HW400c/2 - page 52

    HighWire HW400c/2 User Reference Guide Rev 1.0 Figure 13 ram Table 22. GPIO Port Assignments for IPMI GPIO Port I/O Desc ription . IPMI Block Diag GPIO_00 Input /PWRON monitor (active low) GPIO_01 Input HEALTHY monitor (active high) GPIO_07 Output Blue LED control (low = on, high = off) GPIO_12 Input Watchdog Timer Expired (active low) GPIO_13 Outp ...

  • SBE HighWire HW400c/2 - page 53

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 23. Voltage Monitor A/ D Port Assignments for IPMI Supply Voltage Monitor A/D Port 5-Volt A2D1 3.3-Volt A2D2 1.1-Volt (CPU core) A2D3 1.5-Volt (System controller core) A2D4 2.5-Volt (SDRAM) A2D5 Table 24. HW400c/2 Temperature Sensor Locations Location I 2 C Port 1 Address Device TS0 (U84) Control ...

  • SBE HighWire HW400c/2 - page 54

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.6.6 Board Reset via IPMI ble 22) is connected to the CPLD and OR’ed with the /P_RST set signal from the Host CompactPCI bus. A standard IPMI command is issued to initiate the board reset. IPMI commands are issued through an IPMI Shelf Manager 3.6.7 IPMI System Power Supply IPMI Zircon PM, together ...

  • SBE HighWire HW400c/2 - page 55

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.6.9 Zircon PM -up, the Zircon PM is held in r eset state until the 3.3V supply voltage is within tolerance. 3.6.10 IMPI Get The response to the IPMI command “GetDeviceID” from the Shelf Manager is of the See Appendix A for the complete response format to GetDeviceID.” Unique Product ID numbers ...

  • SBE HighWire HW400c/2 - page 56

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.7 Hot Swap Support The HW400c/2 complies with the PICMG 2.1 specification for full hot swap in CompactPCI systems as de fined by the PI CMG 2.1 R2.0 specification. Hot swap functions, such as power FET control, are provided by a Linear Technologies LTC1664 Hot Swap Controller. 3.7.1 Hot Swap o All si ...

  • SBE HighWire HW400c/2 - page 57

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.7.5 Hot Swap Sequence sequence is a coordination be tween the operator, the hardware on the W400c/2 board, and the host system board that is capable of basic, full, or high- availability hot swap. Table 27 outlays the Hot Swap insertion and extraction Hot Swap Insertion/Extraction Sequenc es Type Seq ...

  • SBE HighWire HW400c/2 - page 58

    HighWire HW400c/2 User Reference Guide Rev 1.0 4 PROGRAMMING INFORMATION mmable register information is provided in is section. .1 HW400c/2 M Table 28 shows the m 2 board. Table 28. HW400c/2 Memory Ma Address Start (Hex) re d (H Device No. Device Size y Size The HW400c/2 memory map and progra th 4 emory Map emory map for the HW400c/ p Add ss En ex) ...

  • SBE HighWire HW400c/2 - page 59

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2 CPLD Registers ogrammable Logic Device) registers are 8-bit registers that are accessible by the system controller. Nam De Offset ess ) c All CPLD (Complex Pr 1: All reserved l ocations and bits ar e set to zero a fter a reset to the CPLD. : Check indivi dual register descriptions for default regis ...

  • SBE HighWire HW400c/2 - page 60

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.1 Clock Select Register (CSR) The Clock Select Register (CSR) is a Read/Write register. This register selects whether or not the H.110 Controller (T8110L) drives the H.110 an d local CT bus sync and clock. The register bit definitions are shown in Table 30. Table 30. Clock Select Regist er (CSR) Of ...

  • SBE HighWire HW400c/2 - page 61

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.2 Board Status Register (BSR) The Board Status Register (BSR) is a Read/Write register. This register reflects the presence of the CT bus (H.110, see Section 3.3.3), the state of the FACT (Factory) mper in J7 (see Figure 9), and can control and report the state of two of the status EDS on the front ...

  • SBE HighWire HW400c/2 - page 62

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.4 Memory Option Register (M OR) T The Memory Option Register (MOR) is a Read-Only register. This register reports the presence and size of the M-Systems Disk on Chip device. able 33. Memory Option Register (MOR) Offset Address 0x07 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DOC3 DOC2 DOC1 DO C ...

  • SBE HighWire HW400c/2 - page 63

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.6 PTMC Reset Register (PRR) PTMC Reset Register (PRR) is a Read/Write register that asserts and de-asserts reset to the individual PTMC sites. The Reset pulse applied to the PTMC m odules must conform to the PCI standard, that is, it must be at least 10 PCI clock cycles long. Table 35. PTMC Reset R ...

  • SBE HighWire HW400c/2 - page 64

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.8 Board Option Register (BOR) for the W400c/2 board. Table 37. Board Option Register (BOR) Offset Address 0x0D The Board Option Register (BOR) is a Read Only register. This register indicates the configuration and product type. Bit 5, bi t 2, bit 1 and bit 0 are always “1” H Bit 7 Bit 6 Bit 5 B ...

  • SBE HighWire HW400c/2 - page 65

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.10 PCI Status Register (PSR) The PCI Status Register (PSR) is a Read-Only register and indicates the status of host and local PCI buses. The bits of this register are defined as follo the ws. Table 39. PCI Status Register (PSR) Offse t Address 0x0F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R ...

  • SBE HighWire HW400c/2 - page 66

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.12 Hardware Revision Register (HRR) The Hardware Revision Register (HRR) is a Read-Only register. It contains the current major and minor (optional) hardware revision for the board. Table 41. Hardware Revision Register (HRR) Offset Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HRR7 HRR6 H ...

  • SBE HighWire HW400c/2 - page 67

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.14 PLL Configuration Register B (PLLB) ter long with PLLA) can help software determine the CPU operating frequency, as well a Table 43. PLL Configuration Regist er B (PLLB) Addr 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The PLL Configuration Register B (PLLB) is a Read-Only register. It con ...

  • SBE HighWire HW400c/2 - page 68

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.15 LED Register B (LEDB) The LED Register B (LEDB) is a Read/Write register. It contains controls for the eight on-board surface-mount LEDs as well as the optional LAN status LEDs. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Table 44. LED Register B (LEDB) Offset Address 0x14 STLEDD S 1 LEDB0 T ...

  • SBE HighWire HW400c/2 - page 69

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.16 Device Control Register (DCR) U 15 B B B B B B The Device Control Register (DCR) is a Read/Write register, which controls the CP timer enable and three resets. The Reset pulse applied to any d evice must conform to the specifications of that particular device. Please refer to the applicabl e dev ...

  • SBE HighWire HW400c/2 - page 70

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.18 Warm Reset Register (WRR) The Warm Reset Register is a Read/Write Register. Writing a value of 0x77 to the Warm Reset Register initializes a Warm Reset. The actual reset si gnal is driven by the CPLD 1-2 milliseconds after writing 0x77 to the WRR. The CPU, System Controller, CPLD registers, T811 ...

  • SBE HighWire HW400c/2 - page 71

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.21 SPI Read Byte Offset Register (SOR) g ding from e BCM5388 Ethernet Switch SPI port. In the case where the entire register is not Tab x1C The SPI Byte Offset Select Register is a Read/Write register. It is used for selec tin the desired byte offset (within the regist er selected by the SAR) when ...

  • SBE HighWire HW400c/2 - page 72

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.23 Write Byte Count Register (WBC) The Write Byte Count Register is a Read/Write register. It is used for setting the number of bytes to be written when writing to the BCM5388 SPI port. All bytes in a given register must be written; for example, if the register to be written itten, contains 3 bytes ...

  • SBE HighWire HW400c/2 - page 73

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.25 SPI Error and Status Register (SESR) The SPI Error Register is a Read Only register. SBSY clears when the previous operation is completed, and the SPIFER, RACKER, and BYTER error flags clear when the next operation is started. PIFER, RACKER and BYTER are valid afte r SBSY=0 (Interface Ready), bu ...

  • SBE HighWire HW400c/2 - page 74

    HighWire HW400c/2 User Reference Guide Rev 1.0 R) king the programming tatus after a write operation. to write EEPROM word addresses 0x00-0x0F without the FAC jumper stalled results in a write error, setting WERR bit. These addresses are reserved for Ta 9 Bit 7 Bit 5 Bit 3 Bit 2 1 Bit 0 4.2.27 EEPROM Operation/Status Register (EOS The EEPROM Operat ...

  • SBE HighWire HW400c/2 - page 75

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.28 EEPROM Data Registers (EDR0 – EDR1) The y are used for holding bac ading EDR0-1. They are written to the EE PROM during a write operation. ope sign Ta R i EEPROM Data Registers are Read/Write registers. The data bytes to be read from or written to the serial EEPROM. Values written to EDR0-1 ar ...

  • SBE HighWire HW400c/2 - page 76

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.3.2 Writing an ation/Status Register (EOSR, see p. B. Write a “0x01” to the EOSR. This starts the Write Enable operation (EWEN). . Set the EEPROM Address Register (EAR, see Section 4.2.25) to the desired word address. the EEPROM Data Registers EDR0 (LSB) and EDR1 (MSB). F. Write a “0x02” to t ...

  • SBE HighWire HW400c/2 - page 77

    HighWire HW400c/2 User Reference Guide Rev 1.0 RBC to a size that exceeds the actual register size will result in an incorrect read e. valu er size values re in strict accordance with the BCM5388 data sheet. 4.4.3 Reading BCM . Check the SBSY flag in the SPI Erro r and Status Register, bit 0 (SESR, see Section 4.2.24). If set to “0”, proceed to ...

  • SBE HighWire HW400c/2 - page 78

    HighWire HW400c/2 User Reference Guide Rev 1.0 D. Write the bytes to be written into the SPI Data Reg 4.2.24), beginning with LSB in SDR0. isters (SDR0-7, see Section E. Set the Write Byte Count Register (WBC, see Section 4.2.23) to the count of bytes to write. This step initiates writing to the Ethernet switch. The register will not be written if ...

  • SBE HighWire HW400c/2 - page 79

    HighWire HW400c/2 User Reference Guide Rev 1.0 5 LINUX ON THE H The HW400c/2 uses an off the shelf 2.6.9 PPC Linux kernel distribution from Gentoo W400C/2 AND HOST SYSTEM ( www.gentoo.org ) with some additional files added specific to the HW400c/2, and with the GenericHDLC WAN stack enabled. The Gentoo Linux kernel may be m. e 14. The root f ile sy ...

  • SBE HighWire HW400c/2 - page 80

    HighWire HW400c/2 User Reference Guide Rev 1.0 • Recent distribution of Linux installed. Because Gentoo Linux is based on the 2.6 series Linux kernel, it is best to use Gentoo Linux in conjunction with a host that has a Linux distribution based on the 2.6 kernel. 5.2 Network and System Configuration Booting Linux on the HW400c/2 requires services ...

  • SBE HighWire HW400c/2 - page 81

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.4 Configuring c/2. 5.4.1 Modifying nce all software is compiled natively on th e HW400c/2, there is no need to modify the host’s path. 5.4.2 Configurin y age for your nal product, having access to a complete Linux distribution and tool set for your the /etc/exports file on your host machine, adding ...

  • SBE HighWire HW400c/2 - page 82

    HighWire HW400c/2 User Reference Guide Rev 1.0 The parenthesized access privilege values s hown in the previous example should be sufficient. These access privileges specify that the target system at the specified IP dress will have read/write access to the exported file system, and that the user ID ID) of the root user on the target system will no ...

  • SBE HighWire HW400c/2 - page 83

    HighWire HW400c/2 User Reference Guide Rev 1.0 text editor to remove the hash mark on each line that contains the string tftp . Active , he xinetd is the e two mechanisms, and is generally viewed as being more secure an the older inetd . (process status) command, as in the following ample: ps alxww | grep inet .. . stem is using the xinetd server t ...

  • SBE HighWire HW400c/2 - page 84

    HighWire HW400c/2 User Reference Guide Rev 1.0 # 140 0 578 1 0 0 1152 356 do_select S ? 0:00 inetd ps alxww | grep inet 18 0 1360 508 pipe_read S ? 0:00 grep -i inet The alxww options to ps cause the command to display all system processes in an e or arguments contain the string inet . Of these, the first is the actual inetd process, and the third ...

  • SBE HighWire HW400c/2 - page 85

    HighWire HW400c/2 User Reference Guide Rev 1.0 d 5.4.5 Configuring tftp with xinet The servers that can be managed by the xinetd are each listed in a server-spe c ific description: The tftp server serves files using the Trivial File Transfer P o # w s # and to start the installation process for some operating systems. service tftp { no socket_typ ...

  • SBE HighWire HW400c/2 - page 86

    HighWire HW400c/2 User Reference Guide Rev 1.0 he final step in configuring the TFTP server on your Linux system is to copy the o tha • If the /tftpboot directory does not already exist, create it (as root) on your system mkdir command: t ctory structure that was created when you /opt/gentoo/usr/src/linux/arch/ppc/boot/images/uIma o oceed to Sect ...

  • SBE HighWire HW400c/2 - page 87

    HighWire HW400c/2 User Reference Guide Rev 1.0 If you don’t already have one, the easiest way to create a bootp server is to have it reside on the same LAN subnet as the HW400c/2. Creating bootp relay agents for LAN segments is beyond the scope of this document. o set up a server with BOOTP with TFTP ability in a standard Linux box, uncomment (or ...

  • SBE HighWire HW400c/2 - page 88

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.1 U-boot, Universal Bootloader The HW400c/2 uses a boot ROM based on Das U-boot . U-boot (Universal Bootloader) is an off-the-shelf freewar e package found on Sourceforge.net. Ma commands and environment variables are ava ilable in U-boot to facilitate the ny loading f the Linux kernel from various ...

  • SBE HighWire HW400c/2 - page 89

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.1.2 U-boot environment variables riables and commands. While most can be used with the HW400c/2, only a few are necessary for the boot process. A complete list of U-boot environment variables can be found in Appendix B . Lis s eed only be separated by a space (see Section for the Linux kernel. Cons ...

  • SBE HighWire HW400c/2 - page 90

    HighWire HW400c/2 User Reference Guide Rev 1.0 keystroke will stop the countdown and drop into the U-boot debug shell. baudrate Baud rate of the HW400c/2 console (debug) port unit’s MAC address. he MAC address is assigned by SBE at the time of manufacture, stored in non-volatile memory, and ress will be ignored. n dot notation. If not used, ing b ...

  • SBE HighWire HW400c/2 - page 91

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.1.3 Power up call trace For reference purposes, this is a summary of the power up calls after U-boot runs and early_init (…/arch/ppc/kernel/setup.c) rnel/head.S) machine_init (…/arch/ppc/kernel/setup.c) k.c) gigateak_setup_ethernet gigateak_enable_ipmi 1. “ 00c/2 platform. 2. U rt. Normally _ ...

  • SBE HighWire HW400c/2 - page 92

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.2 Booting with tftp m. If a static IP dress is not assigned to the HW400c/2 th rough the boot console, a boot p server may also be necessary. The bootp server, tf tp server, and the NFS server functions 5.5.2.1 U-boot pa The following example shows U-boot parame ters necessary for a tftp download a ...

  • SBE HighWire HW400c/2 - page 93

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.2.2 U-boot pa tftp download and ith a static IP address assigned using the U-boot command: ay IP address ( gatewayip ), the tftp server IP address boot file name ( bootfile ) must also be erver IP address ded to the bootargs line. When all variables are configured, volatile memory. n8 ip=$(ipaddr): ...

  • SBE HighWire HW400c/2 - page 94

    HighWire HW400c/2 User Reference Guide Rev 1.0 TFTP from server 10.0.0.5; our IP address is 10.0.0.10 ######### ############### Bytes transferred = 1551015 (17aaa7 hex) Entry K address 00000000) ... gigateak_setup_peripherals: enter gateak_intr_setup: exit gateak_setup_arch: exit c version 3.4.4 (Gentoo 3.4.4- r1, V-643xx 10/100/1000 Ethernet Drive ...

  • SBE HighWire HW400c/2 - page 95

    HighWire HW400c/2 User Reference Guide Rev 1.0 HDLC support module revision 1.17 Cronyx Ltd, Synchronous PPP and CISCO HDLC (c) 1994 Building Number Three Ltd & Jan "Yenya" Kasprzak. RAID: Version 2.4 Build 5go ip_conntrack version 2.1 (2048 buckets, 16384 max) - 336 bytes per conntrack ip_tables: (C) 2000-2002 Netfilter core team ipt ...

  • SBE HighWire HW400c/2 - page 96

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.3 Booting with Disk on Chip A Disk-on-Chip (DoC) flash file system device is used on the HW400c/2 for data storage. DoC is a high-density flash device manufactured by M-Syste ms Incorporated, and has a data bus width of 16 bits. The 128 MB device is standard on e HW400c/2, with the option of popula ...

  • SBE HighWire HW400c/2 - page 97

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.3.2 Creating a uRamdisk Image uRamdisk is a tiny kernel image needed to boot uImage from the Disk on Chip. ng # /sbin/m mkdir -p / mount -o loop ramdisk.image /mnt/ramdisk Copy everything that is need th mdis disk. Then... # umount /mnt/ramdisk # gzip ramdi Ramdisk can be written t with the docshel ...

  • SBE HighWire HW400c/2 - page 98

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.6 Compiling the Kernel ( uImage ) y 1. As root, change to the kernel source directory DD = 2 digit day HH = 2 digit hour mm = 2 digit m inutes # date 031310002006 # make mrproper 4. Create a new .config file by copying the config-save file to .config # cp config-save .config # make uImage Unlike othe ...

  • SBE HighWire HW400c/2 - page 99

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.6.1 Gentoo Application Packages Management ple, e inetd is not automatically installed and activated under Gentoo as under some Linux distributions etwork access. o e command: # rc-status --all or more information about Portage see the man page portage(5) , and “Portage” is the name of Gentoo&apo ...

  • SBE HighWire HW400c/2 - page 100

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.6.1.2 Enable remo up an file at /etc/ssh/sshd_config . One les g to log in, an attacker first must login as a reg pa im e HW400c/2 console as root: If daemon on every start up: default 5.6.1.3 Starting netw rk services; xinetd A lot of services depend on having the xinetd service running. Unlike sshd ...

  • SBE HighWire HW400c/2 - page 101

    HighWire HW400c/2 User Reference Guide Rev 1.0 # rc-update add vsftpd default /etc/vsftpd/vsftpd.conf can be: dirmessage_enable=YES an sf pd.b nner # edit banner first xferlog_enable=YES idle_session_timeout=600 data_connection_timeout=120 cii d_enable=NO ascii e= chroot_list_enable=YES backg liste ls_recurse_enable=NO More inform g You may also wa ...

  • SBE HighWire HW400c/2 - page 102

    HighWire HW400c/2 User Reference Guide Rev 1.0 Appendix A Response message data to IPMI GetDeviceID request. Values in bold are changes from default Zircon firmware response message. Byte offset Description IPMI Definition SBE value Comments IPMI GetDeviceID 1 Completion code (returned in me ssage, N not part of data) /A 2 D ed 0 Impleme nts standa ...

  • SBE HighWire HW400c/2 - page 103

    HighWire HW400c/2 User Reference Guide Rev 1.0 Appendix B U-Boot Environment variables n source boot and debug firmware. A U-boo .de/wiki/bin/view/DULG/Manual Das U-boot was created by Wolfgang Denk as an ope complete t manual can be found at http://www.denx . ndix i s accessed by entering the help Note: ands m d' ootd - boot default, i.e., ru ...

  • SBE HighWire HW400c/2 - page 104

    HighWire HW400c/2 User Reference Guide Rev 1.0 October 10, 2006 Copyright 2006, SBE, Inc. Page 92 mtest - simple RAM test mw - memory write (fill) nfs - boot image via network using NFS protocol nm - memory modify (constant address) pci - list and access PCI Configuraton Space ping - send ICMP ECHO_REQUEST to network host printenv - print environme ...

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