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Manual Xilinx UG154

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  • Xilinx UG154 - page 1

    R LogiCORE™ IP SPI-4.2 Core v8.5 Getting Star ted Guide UG154 Mar ch 24, 2008 ...

  • Xilinx UG154 - page 2

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com UG154 March 24, 2008 "Xilinx" and the Xilinx logo sho wn abov e are registered trademar ks of Xilinx, Inc. Any rights not expressly g ranted herein are reser v ed. CoolRunner , Roc k etChips, Roc ket IP , Spar tan, StateBENCH, Stat eCAD , Vir te x, XA CT , XC2064 , XC3090, XC4005, and XC ...

  • Xilinx UG154 - page 3

    w ww .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Revision History The following table shows the revision history for this document. Date V ersion Revision 09/30/04 1.0 Initial Xilinx release. 1 1/1 1/04 1.1 Document u pdated to support SPI-4.2 cor e v7.1. 04/28/05 1. 2 Document update d to support SPI-4. 2 core v7.2 and Xil ...

  • Xilinx UG154 - page 4

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com UG154 March 24, 2008 ...

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    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com UG154 March 24, 2008 Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ...

  • Xilinx UG154 - page 6

    w ww .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 R <project directory>/<component name> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 <component name>/doc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 <component name> ...

  • Xilinx UG154 - page 7

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com UG154 March 24, 2008 Chapter 3: Quick Start Example Design Figure 3-1: Core Customization GUI Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chapter 4: Detailed Example Design Figure 4-1: Example Design Confi guration . . . . . . . . . . . . . . . . . . . . . . . . . ...

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    w ww .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 R ...

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    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com UG154 March 24, 2008 Chapter 4: Detailed Example Design Table 4-1: Project Di rectory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4-2: Component Name Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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    w ww .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 R ...

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    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 11 UG154 March 24, 2008 R Pr eface About This Guide This guide provides information about generating the Xilinx LogiCORE™ IP SPI-4 .2 cor e, customizing and simulating the core using th e provided example design, and running the design files through implementation using the Xilinx tools. Content ...

  • Xilinx UG154 - page 12

    12 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Preface: About This Guide R T ypogr aphical The following typographical conventions are used in this document: Online Document The following conventions ar e used in this document: Con vention Meaning or Use Example Courier font Messages, prompts, and program files that the ...

  • Xilinx UG154 - page 13

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 13 UG154 March 24, 2008 R Chapter 1 Intr oduction The LogiCORE IP SPI-4.2 (PL4) co re is a fully verifi ed design solution that supports V erilog and VHDL. The example design in this guide is provided in both V erilog and VHDL. This chapter introduces the SPI-4.2 core and provides r e l ated infor ...

  • Xilinx UG154 - page 14

    14 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 1: Introd uction R Contact your local Xilinx re presentative for a closer r eview and estimate of the effort requir ed to meet your specific des ign requir ements. Additional Core Resour ces For detailed information and updates about th e SPI-4.2 core, see the follow ...

  • Xilinx UG154 - page 15

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 15 UG154 March 24, 2008 R Chapter 2 Licensing the Cor e This chapter provides instructions for obtaining a license for the core so that you can use the core in a design. The SPI-4.2 cor e is provided under the terms of the Xilinx LogiCORE Site License Agr eement . This license agr eement conforms ...

  • Xilinx UG154 - page 16

    16 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 2: Licensing the Core R be tested in the tar get device for a limited time before timing out . The core can be reactivated by re configuring the device after a t ime out. Y ou can obtain the Full System Evaluation License in one of the following ways, dependi ng on t ...

  • Xilinx UG154 - page 17

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 17 UG154 March 24, 2008 Installing Y our License File R Follow the instructions in the lounge to fill out the license r equest form; then click Submit to automatically generate the li cense. An email containing the license and installation instructions will be se nt to you immediately . Installing ...

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    18 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 2: Licensing the Core R ...

  • Xilinx UG154 - page 19

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 19 UG154 March 24, 2008 R Chapter 3 Quick Start Example Design The quick start steps pr ovide information to quickly gener ate a SPI-4.2 core, r un the design through implementation with the Xilinx tools, and simulate the example design using the provided demonstration test bench. For mor e detail ...

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    20 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 3: Quick Star t Example Design R 5. After creating the project, locate the di r ectory containing the SPI-4.2 core in the taxonomy tree; it appears under Communications & Networking > T elecommunications > SPI-4.2. 6. Double-click the cor e to bring up the ...

  • Xilinx UG154 - page 21

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 21 UG154 March 24, 2008 Implementing th e Example Design R Implementing the Example Design A f t e r g e n e r a t i n g a c o r e w i t h a F u l l S y s t e m H a r d w a r e E v a l u a t i o n o r F u l l l i c e n s e , t h e n e t l i s t s and the example design can be pr ocessed by the Xil ...

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    22 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 3: Quick Star t Example Design R T o run a VHDL or V erilog functional simulation of the example design using NCSIM: 1. Set the current dir ectory to: <quickstart> /simulation/functional/ 2. Execute the simulation script: % simulate_ncsim.sh ms-dos> simulate ...

  • Xilinx UG154 - page 23

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 23 UG154 March 24, 2008 Running the Sim ulation R The simulation script compiles the timing simulation model and the demonstration test bench, adds re levant signals to the wave window , and runs the simulation. T o observe the operation of the cor e, inspect the simu lation transcript and the wav ...

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    24 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 3: Quick Star t Example Design R ...

  • Xilinx UG154 - page 25

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 25 UG154 March 24, 2008 R Chapter 4 Detailed Example Design This chapter provides detailed information about the example design, including a description of files and the di r e ctory structur e generated by the Xilinx CORE Generator , the purpose and contents of the pr ovided scripts, the contents ...

  • Xilinx UG154 - page 26

    26 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R Directory and File Contents The SPI-4.2 core dir e ctories and their assoc iated files are defined in the following sections. <project director y> The project dir ectory contains all the CORE Generator project files. See the SP I-4 ...

  • Xilinx UG154 - page 27

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 27 UG154 March 24, 2008 Directory and File Contents R <component name>/e xample design The example design dir ectory contains the ex ample design files pr ovided with the cor e. spi4_2_ug153.pdf SPI-4.2 User Guide Back to T op T able 4-3: Doc Directory (Cont inued) Name Description T able 4- ...

  • Xilinx UG154 - page 28

    28 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R <component name>/implement The implement directory contains the cor e implementation script files. T able 4-5: Implement Directory Name Description <project_dir>/<component_name>/implement implement.{sh|bat} W indows (. ...

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    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 29 UG154 March 24, 2008 Directory and File Contents R implement/results The results dir ectory is created by the implem ent script, after which the implement script resul ts are placed in the r esults dir ectory . <component name>/simulation The simulation directory contains the necessar y f ...

  • Xilinx UG154 - page 30

    30 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R simulation/functional The functional directory contains functional simulation scripts pr ovided with the core. T able 4-8: Functional Director y Name Description <project_dir>/<component_name>/simulation/functional simulate_m ...

  • Xilinx UG154 - page 31

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 31 UG154 March 24, 2008 Implementation and Sim ulation Scripts R simulation/timing The timing directory contains timing simulation scripts provided with the core. Implementation and Sim ulation Scripts The implementation script is either a shell sc ript or a batch file that runs the example design ...

  • Xilinx UG154 - page 32

    32 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R If the core was generated with the Full System Har dware Evaluation or the Full license, the implementation script is pr esent and performs the following steps: 1. Synthesizes the example design using the se lected synthesis tool (XST or ...

  • Xilinx UG154 - page 33

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 33 UG154 March 24, 2008 Example Design Configurat ion R connects to a SPI-4.2 PHY layer device or network processor . Figure 4-1 shows the example design modules architectur e and interfaces to the SPI-4.2 core. Loopbac k Module The Loopback Module connects to the user inte rface of the SPI-4. 2 S ...

  • Xilinx UG154 - page 34

    34 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R Demonstration T est Bench The demonstration test bench emulates a PHY device by generating and receiving packet data across the SPI-4.2 interface. The interf ace between the demonstration test bench and the SPI-4.2 core is illustrated in ...

  • Xilinx UG154 - page 35

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 35 UG154 March 24, 2008 Demonstratio n T est Bench R • Status Monitor • Te s t c a s e Cloc k Generator The Clock Generator cr eates all of the clocks that are used in the Design Example, including SysClk , RDClk2x , UserClk , TSClk , and SnkIdelayRefClk . These clocks are described in mor e d ...

  • Xilinx UG154 - page 36

    36 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R Star tup Module The Startup Module contains th ree functions: DCM setup, calendar loading, an d Dynamic Phase Alignment (DP A) Initialization. These functions are described in detai l in the following secti ons. DCM Star tup The DCM Star ...

  • Xilinx UG154 - page 37

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 37 UG154 March 24, 2008 Demonstratio n T est Bench R • RDCLK_RST Holds DCMReset_RDClk for 8 cycles then r eleases it • RDCLK_LCK Wa i t s f o r t h e Locked_RDClk signal. • TSCLK_RST Holds DCMReset_TSClk for 12 cycles then r eleases it. • TSCLK_LCK Wa i t s f o r t h e Locked_TSClk signal. ...

  • Xilinx UG154 - page 38

    38 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R Procedures Module The procedur es module is a package of functions instantiated in the testcase module to simplify sending d ata and status to the stimulus module. Usi ng these functions, you can create any desired s equence of data or s ...

  • Xilinx UG154 - page 39

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 39 UG154 March 24, 2008 Demonstratio n T est Bench R Lastly , the signal SnkInFrame is cr eated in the status monitor by inverting Snk Oof . This signal is used by the stimulus module to send traini ng. See Appendix C, “Data and Status Monitor W arnings.” Customizing the Demonstrat ion T est B ...

  • Xilinx UG154 - page 40

    40 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R MERGE_P A YLOAD Integer 0 <0 or 1> Before da ta is sent on RDat, the demonstration test bench can either mer ge an EOP and SOP control wor d into one payload control word, or i t can leave them as two separate contr ol words. 1 : M ...

  • Xilinx UG154 - page 41

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 41 UG154 March 24, 2008 Demonstratio n T est Bench R T estcase Module The testcase module generates data and sends it to the stimulu s module, which in turn transmits data to the Sink core and status to the Source core. The following data is cr eated in the testcase module: • Static configuratio ...

  • Xilinx UG154 - page 42

    42 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R Ta b l e 4 - 1 1 contains a list of common useful test case signals and descriptions. There ar e five request signals that can be asse rted in the testcase module. The first four signals interface to the stimulus module (s ee Figure 4-2, ...

  • Xilinx UG154 - page 43

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 43 UG154 March 24, 2008 Demonstratio n T est Bench R and the status for that channel. This sends the status and the channel to the stimulus module for transmission to the core. The stimulus mo d u le e n su r es t h at t h e st a t us i s se n t in the correct location of the calendar sequence. Ca ...

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    44 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Exa mple Design R ...

  • Xilinx UG154 - page 45

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 45 UG154 March 24, 2008 R Appendix A VHDL Details Pr ocedures Module The procedur es module is a package of functions instantiated in the testcase module to simplify the sending of data and status to th e Stimulus module. By using these functions, the user can create any desir ed sequence of data ...

  • Xilinx UG154 - page 46

    46 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Appendix A: VHDL Details R automatically calcul ated from the number of bytes sent. ERR has a higher priority than EOP; if EOP and ERR ar e both ‘1’, the EO Ps for the burst is an EOP abort = ‘01’. The send_idles procedur e is used to send idle contr ol words . The s ...

  • Xilinx UG154 - page 47

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 47 UG154 March 24, 2008 Proce dures Module R The send_status pr ocedure is used to change the status for a particular channel. The get_status pr ocedure is called to check s tatus of a specific channe l. It will cause the status value of that channel to be returned to the testcase. ADDR2 0 to 255 ...

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    48 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Appendix A: VHDL Details R ...

  • Xilinx UG154 - page 49

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 49 UG154 March 24, 2008 R Appendix B V erilog Details Pr ocedures Module The procedur es module is a package of functi ons ins tantiated in the T estcase module to simplify sending data and status to the Stimul us module. Use thes e functions to cr eate any desir ed sequence of data or status. All ...

  • Xilinx UG154 - page 50

    50 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Appendix B: V e r ilog Details R The send_user_data pr ocedure is used to transmit a burst of data. The presence of a SOP contr ol word (befor e the burst of data) and an EOP contr ol word (following the data burst), can be specified. The EOPS (bits 14:13 of the control word ...

  • Xilinx UG154 - page 51

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 51 UG154 March 24, 2008 Random T estcase Sample Code R The send_status pr ocedure is used to change the status for a particular channel. The get_status procedure is called to check status of a specific channel. It will cause the status value of that channel to be returned to the T estca se. Random ...

  • Xilinx UG154 - page 52

    52 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Appendix B: V e r ilog Details R RandIdleRequest = {$random(` RANDOM_SEED + $random(`RANDOM_SEED + $time))} % 100; RandTrainingRequest = {$rand om(`RANDOM_SEED + $time)} % 100; RandDIP4Request = {$random(` RANDOM_SEED + $time + $random(`RANDOM_SEED))} % 10 0; RandDIP2Request ...

  • Xilinx UG154 - page 53

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 53 UG154 March 24, 2008 Random T estcase Sample Code R begin if (DIP4RequestCnt > 0) begin DIP4RequestCnt <= DIP4Reques tCnt - 1'b1; TCDIP4Request <= 1'b1; end else begin DIP4RequestCnt <= 'b0; TCDIP4Request <= 1'b0; end end else begin TCDIP4Request <= 1' ...

  • Xilinx UG154 - page 54

    54 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Appendix B: V e r ilog Details R begin TCSnkDip2ErrRequest <= 1'b1; SnkDip2ErrRequestCnt <= {$ra ndom(`RANDOM_SEED + $time)} % 9; end end //Sends a random sized packe t to a random channel if (RandTask == 0) begin tasks.send_packet({$random(` RANDOM_SEED + $time)} ...

  • Xilinx UG154 - page 55

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 55 UG154 March 24, 2008 R Appendix C Data and Status Monitor W arnings The Data and Status monitors continuously check data sent to and r eceived fr om the demonstration test bench. Ther e are several common warnings that occur when the T estcase module is modified. The warnings ar e listed and de ...

  • Xilinx UG154 - page 56

    56 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Appendix C: Dat a and Status Monitor W arnings R ...

  • Xilinx UG154 - page 57

    SPI-4.2 v8.5 Getti ng Started Guide www .xilinx.com 57 UG154 March 24, 2008 R Appendix D T iming Simulation W arning and Err or Messages There ar e several common simulation warnings and err or messages when timing simulation is run on the example design. These warnings and mes sages are descr ibed in this appendix. "# TDat Error: Data Mismatc ...

  • Xilinx UG154 - page 58

    58 www .xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Appendix D: Timing Simulation W arning and Error Mess ages R ...

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