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Cypress CY7C1150V18 - page 1
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 18-Mbit DDR-II+ SRAM 2-W ord Burst Architecture (2.0 Cycle Read Latency) Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-06621 Rev . *D Revised March 06, 2008 Features ■ 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K ...
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Cypress CY7C1150V18 - page 2
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 2 of 27 Logic Block Diagram (CY7C1 146V18) Logic Block Diagram (CY7C1 157V18) CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W DQ [7:0] Output Logic Reg. Reg. Reg. 8 8 16 8 NWS [1:0] V REF Write Add. Decode 8 8 LD C ...
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Cypress CY7C1150V18 - page 3
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 3 of 27 Logic Block Diagram (CY7C1 148V18) Logic Block Diagram (CY7C1 150V18) CLK A (18:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W DQ [17:0] Output Logic Reg. Reg. Reg. 18 18 36 18 BWS [1:0] V REF Write Add. Decode 18 1 ...
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Cypress CY7C1150V18 - page 4
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 4 of 27 Pin Configurations CY7C1 146V18 (2M x 8) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 23 4 567 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS 1 K R/W NC/144M NC NC NC NC NC TDO NC NC NC NC NC NC TCK NC NC A NC/288M K NWS 0 V SS A ...
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Cypress CY7C1150V18 - page 5
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 5 of 27 Pin Configurations (continued) CY7C1 148V18 (1M x 18) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 23 4 567 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A BWS 1 K R/W NC/144M DQ9 NC NC NC NC TDO NC NC NC NC NC NC TCK NC NC A NC/288M ...
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Cypress CY7C1150V18 - page 6
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 6 of 27 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input Output- Synchronous Data Input Output Signal s . Inputs are sampled on the rising edge of K an d K clocks when write operations are val id. These pins drive out the req uested data when a ...
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Cypress CY7C1150V18 - page 7
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 7 of 27 DOFF Input DLL T urn Off − Active LOW . Connecting this pin to g round turns off the DLL inside the device. The timings in the DLL turned off operation are different from those listed in this data sheet. For normal operation, connect this pin to ...
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Cypress CY7C1150V18 - page 8
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 8 of 27 Functional Overview The CY7C1 146V18, CY7C1 1 57V18, CY7C1 148V18, and CY7C1 150V18 are syn chronous pipelined Burst SRAMs equipped with a DDR inte rface. Accesses are initiate d on the rising edge o f the positive inp ut clock (K). All synchronou ...
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Cypress CY7C1150V18 - page 9
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 9 of 27 echo clock and follows the ti ming of any data pin. This signal i s asserted half a cycle befo re valid data arrives. DLL These chips utilize a Delay Lock Loop (DLL) th at is desig ned to function between 120 MHz and the speci fied maximum clock f ...
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Cypress CY7C1150V18 - page 10
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 10 of 27 Write Cycle Descriptions The write cycle descriptions of CY7C1 146V18 and CY7C1 148V18 follows. [3, 9] BWS 0 / NWS 0 BWS 1 / NWS 1 K K Comments L L L – H – When the Data portion of a write sequence is active : CY7C1 146V18 − both nibbles (D ...
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Cypress CY7C1150V18 - page 11
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 1 1 of 27 The write cycle descriptions of CY7C1 148 V18 follows, [3, 9] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments LLLL L – H – W h e n t h e D a t a p o r t i o n o f a w r i t e s e quence is active , all four bytes (D [35:0] ) are written into the device ...
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Cypress CY7C1150V18 - page 12
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 12 of 27 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan test access port (T AP) in the FBGA package. This part is fully comp liant with IEEE S tandard 1 14 9.1-2001. The T AP op erates using JEDEC standard 1.8V IO ...
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Cypress CY7C1150V18 - page 13
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 13 of 27 IDCODE The IDCODE instruction causes a vendor-speci fic, 32-bit code to be loaded into the instruction re gister . It also places the instruction register b etween th e TDI an d TDO p ins an d enable s the IDCODE to be shifted out of the device w ...
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Cypress CY7C1150V18 - page 14
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 14 of 27 T AP Controller St ate Diagram Figure 2 shows the tap controller state diagram. [10] Figure 2. T ap Co ntroller St ate Diagram TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR SELECT I ...
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Cypress CY7C1150V18 - page 15
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 15 of 27 T AP Controller Blo ck Diagram Figure 3. T a p Controller Block Diagram T AP Electrical Characteristics The T ap Electrical Characteristics ta ble over the operati ng rang e follows. [1 1, 12, 13] Parameter Descriptio n T est Conditions Min Max U ...
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Cypress CY7C1150V18 - page 16
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 16 of 27 T AP AC Switchi ng Characteristics The T ap AC Switching Characteristics ta ble over the operati ng rang e follows. [14, 15] Parameter Descriptio n Min Max Unit t TCYC TCK Clock Cycle T ime 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIG ...
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Cypress CY7C1150V18 - page 17
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 17 of 27 Identification Regi ster Definitions Instruction Field Va l u e Description CY7C1 146V18 CY7C1 157V18 CY7C1 148V18 CY7C 1 150V18 Revision Number (31:29) 000 000 000 000 V ersion number . Cypress Device ID (28:12) 1 10101 1 1 100000101 1 10101 1 1 ...
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Cypress CY7C1150V18 - page 18
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 18 of 27 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 1 1H 54 7B 81 3G 1 6 P 28 10G 55 6B 82 2G 26 N 2 9 9 G 5 6 6 A 8 3 1 J 3 7 P 30 1 1F 57 5B 84 2J 4 7N 31 1 1G 58 5A 85 3K 57 R 3 2 9 F 5 9 4 A 8 6 3 J 6 8R 33 10F ...
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Cypress CY7C1150V18 - page 19
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 19 of 27 Power Up Sequence in DDR-II+ SRAM During Power Up, when the DOFF is tied HIG H, the DLL gets locked after 2048 cycles of st able clock. DDR-II+ SRAMs must be powered up and initialized in a predefin ed manner to prevent undefined operations. Powe ...
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Cypress CY7C1150V18 - page 20
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 20 of 27 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. These user guid elines are not tested. S torage T emperature ............. .............. ..... –65°C to + 150°C Ambient T emperature with Powe r Applied ? ...
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Cypress CY7C1150V18 - page 21
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 21 of 27 Cap acit ance T ested initially and after any design or proc ess change that may affect these parameters . Parameter Descriptio n T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V V DDQ = 1.5V 5p F C CLK Clock ...
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Cypress CY7C1150V18 - page 22
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 22 of 27 Switching Characteristics Over the operating range [21, 22] Cypress Parameter Consortium Parameter Description 375 MH z 333 MHz 300 MHz Unit Min Max Min Max Min Max t POWER V DD (T ypical) to the first Access [23] 1–1–1– m s t CYC t KHKH K ...
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Cypress CY7C1150V18 - page 23
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 23 of 27 Switching W aveforms Read/Write /Deselect Sequence Figure 7. W aveform for 2.0 Cycle Read L aten cy [29, 30, 31] DON’ T CARE UNDEFINED 1 2 3 4 5 6 7 8 9 10 READ READ READ NOP WRITE WRITE t NOP 11 K K LD R/W A t KH t KL t CYC t HC t SA t HA SC A ...
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Cypress CY7C1150V18 - page 24
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 24 of 27 Ordering Information Not all of the speed, package and tem perature ranges are availabl e. Contac t your local sales representative or visit www .cypress.com for actual products offered. Speed (MHz) Ordering Co de Package Diagram Package T y pe O ...
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Cypress CY7C1150V18 - page 25
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 25 of 27 300 CY7C1 146V18-300BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1 157V18-300BZC CY7C1 148V18-300BZC CY7C1 150V18-300BZC CY7C1 146V18-300BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb ...
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Cypress CY7C1150V18 - page 26
CY7C1 146V18, CY7C1 157V18 CY7C1 148V18, CY7C1 150V18 Document Number: 001-06621 Rev . *D Page 26 of 27 Package Diagram Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-8 5180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW ...
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Cypress CY7C1150V18 - page 27
Document Number: 001-06621 Rev . *D Revised March 06, 2008 Page 27 of 27 QDR™ is a trademark of Cypress Semicond uctor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of prod ucts developed by Cypress, IDT , NEC, Renesas, and Samsung. All product an d c ompany names me ntioned in t his document ar e the trade marks of th eir respecti ...
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