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Manual Intel SE7520JR2

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  • Intel SE7520JR2 - page 1

    Intel ® Server Board SE7520JR2 T echnical Product Specification Revision 1.0 October 2004 Enterprise Platforms and Services Marketing ...

  • Intel SE7520JR2 - page 2

    Revision History Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 ii Revision History Date Revis ion Number Modifications December 2003 0.5 Preliminary Release June 2004 0.9 Memory Sub-system rew rite, BIOS Chapter Updated, Management Chapter re-write, Error Handling chapter re-w rite, several changes made to better reflect final design Octob ...

  • Intel SE7520JR2 - page 3

    Intel® Server Board SE7520JR2 Disclaimers Revision 1.0 C78844-002 iii Disclaimers Information in this document is provided in connection with Intel ® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale f ...

  • Intel SE7520JR2 - page 4

    Table of Contents Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 iv Table of Contents 1. Introduction ................................................................................................................... ..... 19 1.1 Chapter Outline ............................................................................................... ...

  • Intel SE7520JR2 - page 5

    Intel® Server Board SE7520JR2 Table of Contents Revision 1.0 C78844-002 v 3.2.2 PCI-X Hub (PXH) ................................................................................................... 33 3.2.2.1 Full-height Riser Slot .......................................................................................... 33 3.2.2.2 Low Profile Riser ...

  • Intel SE7520JR2 - page 6

    Table of Contents Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 vi 3.4.3 Interrupt Routing .................................................................................................... 52 3.4.3.1 Legacy Interrupt Routing .................................................................................... 52 3.4.3.2 APIC Interrupt Ro ...

  • Intel SE7520JR2 - page 7

    Intel® Server Board SE7520JR2 Table of Contents Revision 1.0 C78844-002 vii 4.3 BIOS Power On Self Test (POST) ......................................................................... 81 4.3.1 User Interface ........................................................................................................ 81 4.3.1.1 System Activity Window . ...

  • Intel SE7520JR2 - page 8

    Table of Contents Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 viii 5.1 Platform Management Architecture Overview ..................................................... 115 5.1.1 5V Standby .......................................................................................................... 116 5.1.2 IPMI Messaging, Commands, and Abst ...

  • Intel SE7520JR2 - page 9

    Intel® Server Board SE7520JR2 Table of Contents Revision 1.0 C78844-002 ix 5.3.17.2 User Model ..................................................................................................... 134 5.3.17.3 Request/Response Protocol .......................................................................... 134 5.3.17.4 Host to mBMC Communicatio ...

  • Intel SE7520JR2 - page 10

    Table of Contents Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 x 6.4.2 Diagnostic LEDs .................................................................................................. 167 6.4.3 POST Code Checkpoints ..................................................................................... 168 6.4.4 Bootblock Initialization C ...

  • Intel SE7520JR2 - page 11

    Intel® Server Board SE7520JR2 Table of Contents Revision 1.0 C78844-002 xi 8. Design and Environmental Specifications ..................................................................... 202 8.1 Server Board SE7520JR2 Design Specification .................................................. 202 8.2 Power Supply Requirements ........................ ...

  • Intel SE7520JR2 - page 12

    Table of Contents Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 xii Appendix A: Integration and Usage Tips .............................................................................. 221 Glossary ....................................................................................................................... ............ 222 Refer ...

  • Intel SE7520JR2 - page 13

    Intel® Server Board SE7520JR2 List of Figures Revision 1.0 C78844-002 xiii List of Figures Figure 1. SE7520JR2 Board Layout ........................................................................................... 23 Figure 2. Server Board Dimensions ............................................................................................ 25 ...

  • Intel SE7520JR2 - page 14

    List of Tables Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 xiv List of Tables Table 1: Baseboard Layout Reference ....................................................................................... 24 Table 2: Processor Support Matrix ............................................................................................. 2 8 Ta ...

  • Intel SE7520JR2 - page 15

    Intel® Server Board SE7520JR2 List of Tables Revision 1.0 C78844-002 xv Table 33: BIOS Setup, Boot Device Priority Sub-menu Selections ........................................... 97 Table 34: BIOS Setup, Hard Disk Drive Sub-Menu Selections .................................................. 97 Table 35: BIOS Setup, Removable Drives Sub-menu Selecti ...

  • Intel SE7520JR2 - page 16

    List of Tables Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 xvi Table 68: Error Codes and Messages ...................................................................................... 162 Table 69: Error Codes Sent to the Management Module ......................................................... 164 Table 70: BIOS Generated Beep Codes ...

  • Intel SE7520JR2 - page 17

    Intel® Server Board SE7520JR2 List of Tables Revision 1.0 C78844-002 xvii Table 103: External USB Connector Pin-out ............................................................................ 197 Table 104: Internal 1x10 USB Connector Pin-out (J1F1) ......................................................... 198 Table 105: Internal 2x5 USB Connecto ...

  • Intel SE7520JR2 - page 18

    List of Tables Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 xviii < This page intentionally left blank. > ...

  • Intel SE7520JR2 - page 19

    Intel® Server Board SE7520JR2 Introduction Revision 1.0 C78844-002 19 1. Introduction This Technical Product Specification (TPS) provides detail to the architecture and feature set of the Intel ® Server Board SE7520JR2. The target audience for this document is anyone wishing to obtain more in depth detail of the server board than what is generall ...

  • Intel SE7520JR2 - page 20

    Introduction Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 20 1.2 Server Board Use Disclaimer Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used t ...

  • Intel SE7520JR2 - page 21

    Intel® Server Board SE7520JR2 Server Board Overv iew Revision 1.0 C78844-002 21 2. Server Board Overview The Intel ® Server Board SE7520JR2 is a monolithic printed circuit board with features that were designed to support the high density 1U and 2U server markets. 2.1 Server Board SE7520JR2 SKU Availability In this document, the name SE7520JR2 is ...

  • Intel SE7520JR2 - page 22

    Server Board Overv iew Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 22 o RJ45 Serial B Port o Two RJ45 NIC connectors o 15-pin video connector o Two USB 2.0 ports o U320 High density SCSI connector (Channel B) (SCSI SKU only) • Internal IO Connectors / Headers o Two onboard USB port headers. Each header is capable of supporting two USB ...

  • Intel SE7520JR2 - page 23

    Intel® Server Board SE7520JR2 Server Board Overv iew Revision 1.0 C78844-002 23 Figure 1. SE7520JR2 Board Layout 3 18 17 14 13 11 15 10 9 8 7 6 5 4 19 25 26 27 12 16 32 33 29 28 21 24 20 39 37 34 31 35 22 36 40 38 23 1 2 30 ...

  • Intel SE7520JR2 - page 24

    Server Board Overv iew Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 24 Table 1: Baseboard Layout Reference Ref # Description Ref # Description 1 (J1A1) 2-Pin Chassis Intrusion Header (J1A2) 2-Pin Hard Drive Act LED Header (J1A4) Rolling BIOS Jumper 22 CPU #2 Fan Header 2 10-Pin DH10 Serial A Header 23 CPU #1 Fan Header 3 Ext SCSI Channel ...

  • Intel SE7520JR2 - page 25

    Intel® Server Board SE7520JR2 Server Board Overv iew Revision 1.0 C78844-002 25 The following mechanical drawing shows the physical dimensions of the baseboard. Figure 2. Server Board Dimensions ...

  • Intel SE7520JR2 - page 26

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 26 3. Functional Architecture This chapter provides a high-level description of the functionality associated with the architectural blocks that make up the Intel Server Board SE7520JR2. Note : This document describes the features and functionality of the Server Board SE7 ...

  • Intel SE7520JR2 - page 27

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 27 3.1 Processor Sub-system The support circuitry for the processor sub-system consists of the following: • Dual 604-pin zero insertion force (ZIF) processor sockets • Processor host bus AGTL+ support circuitry • Reset configuration logic • Processor module prese ...

  • Intel SE7520JR2 - page 28

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 28 3.1.5 Common Enabling Kit (CEK) Design Support The baseboard has been designed to comply with Intel’s Common Enabling Kit (CEK) processor mounting and heat sink retention solution. The baseboard will ship with a CEK spring snapped onto the bottom side of the board b ...

  • Intel SE7520JR2 - page 29

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 29 Processor Family FSB Frequency Frequency Support Intel® Xeon™ 800 MHz 3.2 GHz Yes Intel® Xeon™ 800 MHz 3.4 GHz Yes Intel® Xeon™ 800 MHz 3.6 GHz Yes 3.1.6.1 Processor Mis-population Detection The processors must be populated in the correct order for the proces ...

  • Intel SE7520JR2 - page 30

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 30 High and Low Ratio is determined and programmed to all processors. If there is no value that works for all installed processors, all processors not capable of speeds supported by the BSP are disabled and an error is displayed. 3.1.6.7 Microcode IA-32 processors have t ...

  • Intel SE7520JR2 - page 31

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 31 BSP and starts executing from the reset vector (F000:FFF0h). A processor that does not perform the role of BSP is referred to as an application processor (AP). The BSP is responsible for executing the BIOS power-on self-test (POST) and preparing the machine to boot th ...

  • Intel SE7520JR2 - page 32

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 32 • Memory Controller Hub (MCH) • I/O Controller Hub (ICH5-R) • PCI-X Hub (PXH) The following sub-sections provide an overview of the primary functions and supported features of each chipset component as they are used on the Server Board SE7520JR2. Later sections ...

  • Intel SE7520JR2 - page 33

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 33 GB/s. One x8 interface is used as the interconnect between the MCH and PXH, while the other is configured as two separate x4 interfaces to the full height riser slot. The E7520 MCH is a root class component as defined in the PCI Express Interface Specification, Rev 1. ...

  • Intel SE7520JR2 - page 34

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 34 3.2.2.3 I/OxAPIC Controller The PXH contains two I/OxAPIC controllers, both of which reside on the primary bus. The intended use of these controllers is to have the interrupts from PCI bus A connected to the interrupt controller on device 0, function 1 and have the in ...

  • Intel SE7520JR2 - page 35

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 35 IDE channels of the ICH5R. One channel is accessed through the 40-pin connector on the baseboard. The signals of the second channel are routed to the 100-pin backplane connector for use in either the Intel Server Chassis SR1400 or SR2400 when integrated with a backpla ...

  • Intel SE7520JR2 - page 36

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 36 3.2.3.6 Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA-compatible PIC described in the previous section, the ICH5-R incorporates the Advanced Programmable Interrupt Controller (APIC). 3.2.3.7 Universal Serial Bus (USB) Controller The ...

  • Intel SE7520JR2 - page 37

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 37 The ICH5-R supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface: Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read By te/Word, Process Call, Block Read/Write, a ...

  • Intel SE7520JR2 - page 38

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 38 X8, double row 256MB 512MB 1GB 2GB X4, single row 256MB 512MB 1GB 2GB X4, Stacked, double row 512MB 1GB 2GB 4GB DIMMs on channel ‘A’ are paired with DIMMs on channel ‘B’ to configure 2-way interleaving. Each DIMM pair is referred to as a bank. The bank can be ...

  • Intel SE7520JR2 - page 39

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 39 Using the following algorithm, BIOS configures the memory controller of the MCH to run in either dual channel mode or single channel mode: (1) If 1 or more fully populated DIMM banks are detected, the memory controller is set to dual channel mode. Otherwise, go to ste ...

  • Intel SE7520JR2 - page 40

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 40 E D/R D/R E E D/R D/R S/R S/R E D/R S/R Table 5: Supported DDR2-400 DIMM Populations Bank 3 – DIMMs 3A, 3B Bank 2 – DIMMs 2A, 2B Bank 1 – DIMMs 1A, 1B S/R S/R S/R E S/R S/R E E S/R E D/R D/R E E D/R E S/R D/R MCH S/R S/R D/R Note: On the Server Board SE7520JR2, ...

  • Intel SE7520JR2 - page 41

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 41 status of the extended memory test is displayed on the console. The status of base and extended memory tests are also displayed on an LCD control panel if present. The extended memory test is configured using the BIOS Setup Utility. The coverage of the test can be con ...

  • Intel SE7520JR2 - page 42

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 42 Uncorrectable memory errors are critical errors that may cause the system to fail. The BIOS normally detects and logs these errors as IPMI SEL events for all management levels, except in the case described below. It is possible that a critical hardware error (uncorrec ...

  • Intel SE7520JR2 - page 43

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 43 engine logs the failure. Both types of errors may be reported via multiple alternate mechanisms under configuration control. The scrub hardware will also execute “demand scrub” writes when correctable errors are encountered during normal operation (on demand reads ...

  • Intel SE7520JR2 - page 44

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 44 3.3.6.5 DIMM Sparing Function To provide a more fault tolerant system, the Intel E7520 MCH includes specialized hardware to support fail-over to a spare DIMM device in the event that a primary DIMM in use exceeds a specified threshold of runtime errors. One of the DIM ...

  • Intel SE7520JR2 - page 45

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 45 3.3.6.6 Memory Mirroring The memory mirroring feature is fundamentally a way for hardware to maintain two copies of all data in the memory subsystem, such that a hardware failure or uncorrectable error is no longer fatal to the system. When an uncorrectable error is e ...

  • Intel SE7520JR2 - page 46

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 46 Figure 7. Six DIMM Memory Mirror Configuration (DDR2 Only ) These symmetry requirements are a side effect of the hardware mechanism for maintaining two copies of all main memory data while ensuring that each channel has a full copy of all data in preparation for fail- ...

  • Intel SE7520JR2 - page 47

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 47 the primary and mirror DIMMs, thereby distributing the thermal image of the workload across all populated DIMM slots, and reducing the chances of thermal-based memory traffic throttling. In the “Mirrored” operating state, the occurrence of correctable and uncorrec ...

  • Intel SE7520JR2 - page 48

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 48 Table 7: PCI Bus Segment Characteristics PCI Bus Segment Voltage Width Speed Ty pe PCI I/O Card Slots P32-A 5 V 32-bits 33 MHz PCI None. Internal component use only P64-A 3.3 V 64-bits 100 MHz PCI-X Common riser slot capable of supporting full- length PCI-X or PCI-E a ...

  • Intel SE7520JR2 - page 49

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 49 supports a maximum of 66MHz, the entire bus will throttle down to 66MHz to match the supported frequency of that card. When populating add-in cards, the add-in cards must be installed starting with the slot furthest from the baseboard. Ie) When using a three slot rise ...

  • Intel SE7520JR2 - page 50

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 50 hierarchical PCI bus under the current bridge. The PCI bus number and the subordinate PCI bus number are the same in the last hierarchical bridge. 3.4.1.7 Device Number and IDSEL Mapping Each device under a PCI bridge has its IDSEL input connected to one bit out of th ...

  • Intel SE7520JR2 - page 51

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 51 Table 8: PCI Configuration IDs and Device Numbers PCI Device IDSEL Bus# / Device# / Function# MCH host-HI bridge/DRAM controller 00 / 00 / 0 MCH DRAM Controller Error Reporting 00/00/1 MCH DMA controller 00/01/00 MCH EXP Bridge A0 00/02/00 MCH EXP Bridge A1 00/03/00 M ...

  • Intel SE7520JR2 - page 52

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 52 3.4.1.8 Resource Assignment The resource manager assigns the PIC-mode interr upt for the devices that will be accessed by the legacy code. The BIOS configures the PCI Base Address Registers (BAR) and the command register of each device. Software must not make assumpti ...

  • Intel SE7520JR2 - page 53

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 53 Both PCI and IRQ types of interrupts are handled by the ICH5-R. The ICH5-R translates these to the APIC bus. The numbers in the table below indicate the ICH5-R PCI interrupt input pin to which the associated device interrupt (INTA, INTB, INTC, INTD) is connected. The ...

  • Intel SE7520JR2 - page 54

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 54 3.4.3.3 Legacy Interrupt Sources The table below recommends the logical interrupt mapping of interrupt sources on the Server Board SE7520JR2. The actual interrupt map is defined using configuration registers in the ICH5-R. Table 10: Interrupt Definitions ISA Interrupt ...

  • Intel SE7520JR2 - page 55

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 55 3.4.3.5 IRQ Scan for PCIIRQ The IRQ / data frame structure includes the ability to handle up to 32 sampling channels with the standard implementation using the minimum 17 sampling channels. The Server Board SE7520JR2 has an external PCI interrupt serializer for PCIIRQ ...

  • Intel SE7520JR2 - page 56

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 56 Figure 9. Interrupt Routing Diagram PIRQB PIRQ PIRQ A Super I/O Time r Ke y board Serial Serial IS A Flo ppy /IS IS A RTC SCI/IS A IS A IS A Mouse/IS Co p rocessor P _ IDE/IS Not Used Cascade Serialized IRQ Interface SERIR ICH5-R Interrupt Routing SERIRQ USB 1.1 Contr ...

  • Intel SE7520JR2 - page 57

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 57 Figure 10. PCI Interrupt Mapping Diagram Figure 11. PCI Interrupt Mapping Diagram for 2U Active Riser Card ...

  • Intel SE7520JR2 - page 58

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 58 3.4.4 SCSI Support The SCSI sub-system consists of the LSI 53C1030 Dual Channel Ultra320 SCSI controller, one internal 80-pin connector (SCSI Channel A), one external high 80-pin density SCSI connector (SCSI channel B), and on-board termination for both SCSI channels. ...

  • Intel SE7520JR2 - page 59

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 59 • Quick arbitrate and select (QAS) • Skew compensation • Inter-symbol interference (ISI) compensation • Cyclic redundancy check (CRC) • Domain validation technology The LSI53C1030 contains the following SCSI performance features: • Supports Ultra320 SCSI ? ...

  • Intel SE7520JR2 - page 60

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 60 • Reduces Interrupt Service Routine (ISR) overhead with interrupt coalescing • Supports 32-bit or 64-bit data bursts with variable burst lengths • Supports the PCI Cache Line Size register • Supports the PCI Memory Write and Invalidate, Memory Read Line, and M ...

  • Intel SE7520JR2 - page 61

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 61 The BIOS initializes and supports ATAPI devices such as LS-120/240, CDROM, CD-RW and DVD. The BIOS initializes and supports S-ATA devices just like P-ATA devices. It initializes the embedded the IDE controllers in the chipset and any S-ATA devices that are connected t ...

  • Intel SE7520JR2 - page 62

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 62 3.4.6.1 SATA RAID The Intel ® RAID Technology solution, available with the 82801ER ICH5 R (ICH5R), offers data striping for higher performance (RAID Level 0), alleviating disk bottlenecks by taking advantage of the dual independent SATA controllers integrated in the ...

  • Intel SE7520JR2 - page 63

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 63 Table 11: Video Modes 2D Video Mode Support 2D Mode Refresh Rate (Hz) 8 bpp 16 bpp 24 bpp 32 bpp 640x480 60, 72, 75, 90, 100 Support ed Supported Suppor ted Supported 800x600 60, 70, 75, 90, 100 Support ed Supported Suppor ted Supported 1024x768 60, 72, 75, 90, 100 Su ...

  • Intel SE7520JR2 - page 64

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 64 CKE O Clock Enable for Memory CS#[1..0] O Chip Se lect for Memory DQM[7..0] O Memory Data By te Mask DSF O Memory Special Function Enable HCLK O Memory Clock [11..0] O Memory Address Bus MD[31..0] I/O Memo ry Data Bus RAS# O Row Address Select WE# O Write Enable 3.4.7 ...

  • Intel SE7520JR2 - page 65

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 65 3.4.8.1 NIC Connector and Status LEDs The 82546GB drives the two LEDs that are located on each network interface connector. The link/activity LED to the left of the connector indicates network connection when on, and transmit/receive activity when blinking. The speed ...

  • Intel SE7520JR2 - page 66

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 66 Pin Name IO/GPIO SE7520JR2 Use 2 GPIOE11/XA10 I/O,I(E)1 XBUS_A<10> 3 GPIOE12/XA9 I/O,I(E)1 XBUS_A<9> 4 GPIOE13/XA8 I/O,I(E)1 XBUS_A<8> 5 GPIOE14/XA7 I/O,I(E)1 XBUS_A<7> 6 GPIOE15/XA6 I/O,I(E)1 XBUS_A<6> 7 GPIOE16/XA5 I/O,I(E)1 XBUS_A<5 ...

  • Intel SE7520JR2 - page 67

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 67 3.4.10.2 Serial Ports The baseboard provides two serial ports: an external RJ45 Serial B port, and an internal DH10 Serial A header. The following sub-sections provide details on the use of the serial ports. 3.4.10.2.1 Serial Port A Serial A is an optional port, acces ...

  • Intel SE7520JR2 - page 68

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 68 BMC Bus Exchange SIO 2 to 1 Mux Level shif ter Level Shifter Header R ear RJ45 Serial B Serial A Figure 12. Serial Port Mux Logic 3.4.10.2.4 Rear RJ45 Serial B Port Configuration The rear RJ45 Serial B port is a fully functional serial port that can support any standa ...

  • Intel SE7520JR2 - page 69

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 69 Note: The appropriate RJ45-to-DB9 adapter should match the configuration of the serial device used. One of two pin-out configurations is us ed, depending on whether the serial device requires a DSR or DCD signal. The final adapter configur ation should also match the ...

  • Intel SE7520JR2 - page 70

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 70 3.5 Configuration and Initialization This section describes the initial programming environment including address maps for memory and I/O, techniques and considerations for programming ASIC registers, and hardware options configuration. 3.5.1 Memory Space At the highe ...

  • Intel SE7520JR2 - page 71

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 71 3.5.1.1 DOS Compatibility Region The first region of memory below 1 MB was defined for early PCs, and must be maintained for compatibility reasons. The region is divided into sub-regions as shown in the following figure. Figure 15. DOS Compatibility Region = Mappable ...

  • Intel SE7520JR2 - page 72

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 72 3.5.1.1.1 DOS Area The DOS region is 512 KB in the address range 0 to 07FFFFh. This region is fixed and all accesses go to main memory. 3.5.1.1.2 ISA Window Memory The ISA Window Memory is 128 KB between the address of 080000h to 09FFFFh. This area can be mapped to th ...

  • Intel SE7520JR2 - page 73

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 73 3.5.1.2 Extended Memory Extended memory is defined as all address space greater than 1MB. Extended Memory region covers 8GB maximum of address space from addresses 0100000h to FFFFFFFh, as shown in the following figure. PCI memory space can be remapped to top of memor ...

  • Intel SE7520JR2 - page 74

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 74 3.5.1.2.1 Main M emory All installed memory greater than 1MB is mapped to local main memory, up to 8GB of physical memory. Memory between 1MB to 15MB is c onsidered to be standard ISA extended memory. 1MB of memory starting at 15MB can be optionally mapped to the PCI ...

  • Intel SE7520JR2 - page 75

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 75 3.5.1.4 System Management Mode Handling The chipset supports System Management Mode (SMM) operation in one of three modes. System Management RAM (SMRAM) provides code and data storage space for the SMI_L handler code, and is made visible to the processor only on entry ...

  • Intel SE7520JR2 - page 76

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 76 3.5.2 I/O Map The baseboard I/O addresses are mapped to the processor bus or through designated bridges in a multi-bridge system. Other PCI devices, in cluding the ICH5-R, have built-in features that support PC-compatible I/O devices and functions, which are mapped to ...

  • Intel SE7520JR2 - page 77

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 77 Address (es) Resource Notes 0071h RTC Data 0073h RTC Data Aliased from 0071h 0075h RTC Data Aliased from 0071h 0077h RTC Data Aliased from 0071h 0080h – 0081h BIOS Timer 0080h – 008F DMA Low Page Register 0090h – 0091h DMA Low Page Register (aliased) 0092h Syste ...

  • Intel SE7520JR2 - page 78

    Functional Architecture Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 78 Address (es) Resource Notes 03F8h – 03FFh Serial Port A (primary) 0400h – 043Fh DMA Controller 1, Extended Mode Registers 0461h Extended NMI / Reset Control 0480h – 048Fh DMA High Page Register 04C0h – 04CFh DMA Controller 2, High Base Register 04D0h – 04D1h ...

  • Intel SE7520JR2 - page 79

    Intel® Server Board SE7520JR2 Functional Architecture Revision 1.0 C78844-002 79 3.5.3.1 CONFIG_ADDRESS Register CONFIG_ADDRESS is 32 bits wide and contains the field format shown in the following figure. Bits [23::16] choose a specific bus in the syst em. Bits [15::11] choose a specific device on the selected bus. Bits [10:8] choose a specific fu ...

  • Intel SE7520JR2 - page 80

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 80 4. System BIOS The BIOS is implemented as firmware that resi des in the Flash ROM. It provides hardware- specific initialization algorithms and standard PC-c ompatible basic input/output (I/O) services, and standard Intel ® Server Board features. The Flash ROM also contains firm ...

  • Intel SE7520JR2 - page 81

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 81 As such, the BIOS ID for this platform takes the following form: • SE7520JR2 supporting DDR memory SE7520JR22.86B.P.01.00.0002.081320031156 • SE7520JR2 supporting DDR2 memory SE7520JR23.86B.P.01.00.0002.081320031156 4.2 Flash Architecture and Flash Update Utility The flash RO ...

  • Intel SE7520JR2 - page 82

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 82 Figure 18. POST Console Interface 4.3.1.1 System Activity Window The top row of the screen is reserved for the system state window. On a graphics console, the window is 640x48. On a text console, the window is 80x2. The system state window may be in one of three forms, either an ...

  • Intel SE7520JR2 - page 83

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 83 The Static Information Display area presents the following information: • Copyright message • BIOS ID • Current processor configuration • Installed physical memory size 4.3.1.2.2 Quiet Boot / OEM Splash Screen The BIOS implements Quiet Boot, providing minimal startup disp ...

  • Intel SE7520JR2 - page 84

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 84 Table 17: Sample BIOS Popup Menu Please select boot device: 1 st Floppy Hard Drives ATAPI CDROM LAN PXE EFI Boot Manager ↓ and ↑ to move selection Enter to select boot device ESC to boot using defaults 4.4 BIOS Setup Utility The BIOS Setup utility is provided to perform syste ...

  • Intel SE7520JR2 - page 85

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 85 Key Option Description ↔ Select Menu The left and right arrow keys are used to move between the major menu pages. The keys have no affect if a sub-menu or pick list is displayed. Tab Select F ield The Tab key is used to move between fields. For example, Tab can be used to move ...

  • Intel SE7520JR2 - page 86

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 86 Feature Options Help Text Description System Overview AMI BIOS Version N/A N/A BIOS ID string (excluding the build time and date) Build Date N/A N/A BIOS build date Processor Type N/A N/A Processor brand ID string Speed N/A N/A Calculated processor speed Count N/A N/A Detected nu ...

  • Intel SE7520JR2 - page 87

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 87 4.4.2.2.1 Processor Configuration Sub-menu Table 21: BIOS Setup, Processor Configuration Sub-menu Options Feature Options Help Text Description Configure Advanced Processor Settings Manufacturer Intel N/A Displays processor manufacturer string Brand String N/A N/A Displays proces ...

  • Intel SE7520JR2 - page 88

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 88 4.4.2.2.2 IDE Configuration Sub-menu Table 22: BIOS Setup IDE Configuration Menu Options Feature Options Help Text Description IDE Configuration Onboard P-ATA Channels Disabled Primary Secondary Both Disabled: disables the integrated P-ATA Controller. Primary: enables only the Pr ...

  • Intel SE7520JR2 - page 89

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 89 Feature Options Help Text Description Third IDE Master N/A While entering setup, BIOS auto detects the presence of IDE devices. This displays the status of auto detection of IDE devices. Selects submenu with additional device details. Fourth IDE Master N/A While entering setup, B ...

  • Intel SE7520JR2 - page 90

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 90 Table 24: BIOS Setup, IDE Device Configuration Sub-menu Selections Feature Options Help Text Description Primary/Secondary/Third/Fourth IDE Master/Slave Device N/A N/A Display detected device info Vendor N/A N/A. Display IDE device vendor. Size N/A N/A Display IDE DISK size. LBA ...

  • Intel SE7520JR2 - page 91

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 91 4.4.2.2.3 Floppy Configuration Sub-menu Table 25: BIOS Setup, Floppy C onfiguration Sub-menu Selections Feature Options Help Text Description Floppy Configuration Floppy A Disabled 720 KB 3 1/2" 1.44 MB 3 1/2" 2.88 MB 3 1/2" Select the type of floppy drive connecte ...

  • Intel SE7520JR2 - page 92

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 92 4.4.2.2.5 USB Configuration Sub-menu Table 27: BIOS Setup, USB C onfiguration Sub-menu Selections Feature Options Help Text Description USB Configuration USB Devices Enabled N/A N/A List of USB devices detected by BIOS. USB Function Disabled Enabled Enables USB HOST controllers. ...

  • Intel SE7520JR2 - page 93

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 93 Feature Options Help Text Description Device #n N/A N/A Only displayed if a device is detected, includes a DeviceID string returned by the USB device. Emulation Type Au t o Floppy Forced FDD Hard Disk CDROM If Auto, USB devices less than 530MB will be emulated as Floppy and remai ...

  • Intel SE7520JR2 - page 94

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 94 Feature Options Help Text Description Slot 1 Option ROM Disabled Enabled PCI-X 64/133 Slot 2 Option ROM Disabled Enabled PCI-X 64/133 Slot 3 Option ROM Disabled Enabled PCI-X 64/133 Visible only when installed riser supports this slot. Slot 4 Option ROM Disabled Enabled PCI-X 64/ ...

  • Intel SE7520JR2 - page 95

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 95 Feature Options Help Text Description DIMM 3A Installed Not Installed Disabled Mirror Spare Informational display. DIMM 3B Installed Not Installed Disabled Mirror Spare Informational display. Extended Memory Test 1 MB 1 KB Every Location Disabled Settings for extended memory test ...

  • Intel SE7520JR2 - page 96

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 96 4.4.2.3.1 Boot Settings Configuration Sub-menu Selections Table 32: BIOS Setup, Boot Settings Configuration Sub-menu Selections Feature Options Help Text Descrip tion Boot Settings Configuration Quick Boot Disabled Enabled Allows BIOS to skip certain tests w hile booting. This wi ...

  • Intel SE7520JR2 - page 97

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 97 4.4.2.3.2 Boot Device Priority Sub-menu Selections Table 33: BIOS Setup, Boot De vice Priority Sub-menu Selections Feature Options Help Text Description Boot Device Priority 1st Boot Device Varies Spec ifies the boot sequence from the available devices. A device enclosed in paren ...

  • Intel SE7520JR2 - page 98

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 98 nth Drive Varies Specifies the boot sequence from the available devices. Varies based on system configuration. 4.4.2.4 Security Menu Table 37: BIOS Setup, Security Menu Options Feature Options Help Text Description Security Settings Administrator Password is N/A Install / Not ins ...

  • Intel SE7520JR2 - page 99

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 99 Feature Options Help Text Description Secure Mode Boot Disabled Enabled When enabled, allows the host system to complete the boot process without a passw ord. The keyboard w ill remain locked until a password is entered. A passw ord is required to boot from diskette. This node is ...

  • Intel SE7520JR2 - page 100

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 100 Feature Options Help Text Descriptio n Late POST Timeout Disabled 5 minutes 10 minutes 15 minutes 20 minutes This controls the time limit for add-in card detection. The system is reset on timeout. Hard Disk OS Boot Timeout Disabled 5 minutes 10 minutes 15 minutes 20 minutes This ...

  • Intel SE7520JR2 - page 101

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 101 4.4.2.5.2 Serial Console Features Sub-menu Selections Table 40: BIOS Setup, Serial C onsole Features Sub-menu Selections Feature Options Help Text Description Serial Console Features If enabled, BIOS uses the specified serial port to redirect the console to a remote ANSI termina ...

  • Intel SE7520JR2 - page 102

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 102 Feature Options Help Text Description BIOS Event Logging Disabled Enabled Select enabled to allow logging of BIOS events. Enables BIOS to log events to the SEL. This option controls BIOS events only. Critical Event Logging Disabled Enabled If enabled, BIOS will detect and log ev ...

  • Intel SE7520JR2 - page 103

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 103 The BIOS relies on specialized hardware and additional flash space to accomplish online update/rolling of the BIOS. To this end, the flash is divided into two partitions, primary and secondary. The active partition from which the system boots shall be referred to as the primary ...

  • Intel SE7520JR2 - page 104

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 104 4.5.1.4 BIOS Recovery The BIOS has a ROM image size of 2 MB. A standard 1.44MB floppy diskette cannot hold the entire ROM file due to the large file size. To compensate for this, a Multi-disk recovery method is available for BIOS recovery. The BIOS contains a primary and seconda ...

  • Intel SE7520JR2 - page 105

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 105 4.6 OEM Binary System customers can supply 16 KB of code and data for use during POST and at run-time. Individual platforms may support a larger user binary. User binary code is executed at several defined hook points during POST. The user binary code is stored in the system fla ...

  • Intel SE7520JR2 - page 106

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 106 4.7.1 Operating Model The following table summarizes the operation of security features supported by the BIOS. Some security features require the Intel Management Module (IMM) to be installed. These include “Diskette Write Protect”, “Video Blanking”, and “Power Switch ...

  • Intel SE7520JR2 - page 107

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 107 Administrator/User Passwords and F2 Setup Usage Model Notes : • Visible=option string is active and changeable • Hidden=option string is inactive and not visible • Shaded=option string is gray-out and view-only There are three possible password scenarios: Scenario #1 Admin ...

  • Intel SE7520JR2 - page 108

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 108 Set User Password (visible) User Access Level [Full] (visible) Clear User Password (hidden) Login Type: <Enter> Set Admin Password (hidden) Set User Password (visible) User Access Level [Full] (Shaded) Clear User Password (hidden) 4.7.2 Password Clear Jumper If the user or ...

  • Intel SE7520JR2 - page 109

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 109 PC200x specifications are intended for systems that are designed to work with Windows 2000* and Windows XP* class operating systems. The Hardware Design Guide (HDG) for the Windows XP platform is intended for systems that are designed to work with Windows XP class operating syst ...

  • Intel SE7520JR2 - page 110

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 110 The BIOS supports a control panel sleep button. The sleep button may not be provided on all control panel designs. On systems where the sleep button is optional, a system configuration option will be provided to enable or disable the sleep button. The ACPI tables will be updated ...

  • Intel SE7520JR2 - page 111

    Intel® Server Board SE7520JR2 System BIOS Revision 1.0 C78844-002 111 4.9.2.6 Sleep to On (ACPI) If an operating system is loaded, the sleep button generates a wake event to the ACPI chipset and a request (via SCI) to the OS to place the system in the “On” state. The OS retains control of the system and OS policy determines what sleep state (i ...

  • Intel SE7520JR2 - page 112

    System BIOS Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 112 4.10 PXE BIOS Support The BIOS will support PXE-compliant implementations that: • Locate and configure all PXE-capable boot devices (UNDI Option ROMs) in the system, both built-in and add-ins. • Supply a PXE according to the specification if the system includes a built-in ne ...

  • Intel SE7520JR2 - page 113

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 113 BIOS Console Redirection is intended to accomplish the implementation of VT-UTF8 console redirection support in Intel® server BIOS products. That implementation will meet the functional requirements set forth in the Microsoft Whistler WHQL requirements for headless oper ...

  • Intel SE7520JR2 - page 114

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 114 Element On-Board Platform Instrumentation Intel® Management Module - Professional Edition Intel® Management Module - Adv anced Edition IPMI Channels, and Sessions Limited Yes Yes EMP (Emergency Management Port) - IPMI Messaging over Serial/Modem. This feature is also r ...

  • Intel SE7520JR2 - page 115

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 115 5.1 Platform Management Architecture Overview Figure 19. On-Board Platform Management Architecture CPU2 PC874 2 7 SI O Chassis FANI N1 FANI N2 Secur i t y LM 93 Tach1 Tach2 PWM 1 PWM2 CPU1 Th er mal Di ode CPU2Th er mal Di ode P 1 _ V ID [5 :0 ] P 2 _ V ID [5 :0 ] +12V1 ...

  • Intel SE7520JR2 - page 116

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 116 5.1.1 5V Standby The power supply must provide a 5V Standby power source for the platform to provide any management functionality. 5V Standby is a low power 5V supply that is active whenever the system is plugged into AC power. 5V Standby is used by the following onboard ...

  • Intel SE7520JR2 - page 117

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 117 5.1.3 IPMI ‘Sensor Model’ An IPMI-compatible ‘Sensor Model’ is used to unify the way that temperature, voltage, and other platform management status and control is r epresented and accessed. The implementation of this model is done according to command and data f ...

  • Intel SE7520JR2 - page 118

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 118 5.1.4 Private Management Busses A ‘Private Management Bus’ is a single-master I 2 C bus that is controlled by the management controller. Access to any of the devices on the Private Management Bus is accomplished indirectly via commands to the management controller vi ...

  • Intel SE7520JR2 - page 119

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 119 These interfaces remain active on standby power, providing a mechanism where the SEL, SDR, and recovery control features can be acce ssed even when the system is powered down. Because the management controller operates independently from the main processor(s), the manage ...

  • Intel SE7520JR2 - page 120

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 120 • Platform Event Filtering (PEF) • Keyboard Controller Style (KCS) IPMI-System Interface (Professional and Advanced systems only) • SMBus IPMI-System Interface (On-board Pl atform Instrumentation systems only) • Intelligent Chassis Management Bus (ICMB) support ( ...

  • Intel SE7520JR2 - page 121

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 121 5.2 On-Board Platform Management Features and Functionality The National Semiconductor PC87431M mini-Bas eboard Management Controller (mBMC) is an Application Specific Integrated Circuit (ASIC) with a Reduced Instruction Set Computer (RISC)- based processor and many peri ...

  • Intel SE7520JR2 - page 122

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 122 5.2.1 Server Management I 2 C Buses The table below describes the server management I 2 C bus assignments and lists the devices that are connected to the indicated bus. The column labeled “I 2 C Bus ID” represents the physical I 2 C bus connected to the mBMC. Only th ...

  • Intel SE7520JR2 - page 123

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 123 Figure 21. External Interfaces to mBMC 5.3 mBMC Hardware Architecture The following figure shows an example of the internal functional modules of the mBMC in a block diagram. The mBMC controls various serv er management functions, such as the system power/reset control, ...

  • Intel SE7520JR2 - page 124

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 124 Figure 22. mBMC Block Diagram 5.3.1 Power Supply Interface Signals The mBMC supports two power supply control signals: Power On and Power Good . The Power On signal connects to the chassis power subsystem through the chipset and is used to request power state changes (as ...

  • Intel SE7520JR2 - page 125

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 125 The following figure shows the power supply control signals and their sources. To turn on the system, the mBMC asserts the Power On signal and waits for the Power Good signal to assert in response, indicating that DC power is on. Figure 23. Pow er Supply Control Signals ...

  • Intel SE7520JR2 - page 126

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 126 5.3.2 Power Control Sources The sources listed in the following table can initiate power-up and/or power-down activity. Table 47: Pow er Control Initiators Source External Signal Na me or Internal Subsystem Capabilities Power button Front control power button Turns power ...

  • Intel SE7520JR2 - page 127

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 127 5.3.5.2 Reset Control Sources The following table shows the reset sources and the actions taken by the system. Table 48: System Reset Sources and Actions Reset Source System Reset? mBMC Reset Standby pow er comes up No (no DC power) Yes DC power comes up Yes No Reset but ...

  • Intel SE7520JR2 - page 128

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 128 • Combined power and reset button assertion If DC power is off, an assertion of the PWBTIN while the RSTIN is asserted generates an OEM-specific Control Panel event to PEF. The event attributes are: Sensor Type code - 14h (Button) and Sensor Specific offset - 07h. This ...

  • Intel SE7520JR2 - page 129

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 129 5.3.5.4.2 Fault / Status LED The following table shows mapping of sensors/faults to the LED state. Table 50: Fault / Status LED Color Condition When Solid System ready Green Blink System ready, but degraded: CPU disabled Solid Critical failure: critical f an, voltage, or ...

  • Intel SE7520JR2 - page 130

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 130 5.3.5.5.1 Chassis Intrusion Some platforms support chassis intrusion detection. On those platforms, the mBMC monitors chassis intrusion by polling the server input/ output (SIO) device. The state of the chassis intrusion input is provided by the status register of the SI ...

  • Intel SE7520JR2 - page 131

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 131 time, the LED will turn off. If the LED is on, a button press or IPMI Chassis Identify command turns off the LED. Upon assertion of the chassis identify button, a SEL event is generated by the chassis identity sensor button. The event attributes are: Sensor Type code - 1 ...

  • Intel SE7520JR2 - page 132

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 132 5.3.10.1 SEL Erasure It can take up to one minute to clear a System Event Log based upon other concurrent mBMC operations. 5.3.10.2 Timestamp Clock The mBMC maintains a four-byte internal timestamp clock used by the SEL and SDR subsystems. This clock is incremented once ...

  • Intel SE7520JR2 - page 133

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 133 5.3.12 Field Replaceable Unit (FRU) Inventory Devices An enterprise-class system typically has F RU information for each major system board, (processor board, memory board, I/O board, etc.). The FRU data includes information such as serial number, part number, model, and ...

  • Intel SE7520JR2 - page 134

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 134 5.3.16 mBMC Self Test The mBMC performs various tests as part of its initialization. If a failure is determined (e.g., corrupt mBMC FRU, SDR, or SEL), the mBMC stores the error internally. 5.3.17 Messaging Interfaces This section describes the supported mBMC communicatio ...

  • Intel SE7520JR2 - page 135

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 135 • SMBus data signal (SDAH) • Optional SMBus alert signal (SMBAH). The signal notifies the host that the PC87431x has data to provide. When the system main power is off (PWRGD signal is low), the host interface signals are in TRI-STATE to perform “passive” bus iso ...

  • Intel SE7520JR2 - page 136

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 136 LA N Channel Capability Options Privilege Levels User, Operator, Administrator Authentication Types None, Straight Password, MD5 Number of LAN Alert Destinations 1 Address Resolution Protocol (ARP) Gratuitous ARP 5.3.18 Event Filtering and Alerting The mBMC implements mo ...

  • Intel SE7520JR2 - page 137

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 137 down, power cycle, and/or reset actions, the actions are performed according to PEF Action Priorities. Note: An action that has changed from delayed to non-delayed, or an action whose delay time has been reduced automatically has higher priority. The mBMC can be configur ...

  • Intel SE7520JR2 - page 138

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 138 mBMC sensors 01h – 08h are internal sensors to the mBMC and are used for event generation only. These sensors are not for use with the ‘Get Sensor Reading’ IPMI command and may return an error when read. Table 55: Platform Sensors for On-Board Platform Instrumentat ...

  • Intel SE7520JR2 - page 139

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 139 Sensor Name Sensor # Sensor Type Event / Reading Type Event Offset Triggers A ssert / Deassert Readable Value/Offsets Event Data PEF A ction SDR Record Type Physical Security Violation 0Ah Physical Security 05h Sensor Specific 6Fh General Chassis Intrusion As & De Ge ...

  • Intel SE7520JR2 - page 140

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 140 Sensor Name Sensor # Sensor Type Event / Reading Type Event Offset Triggers A ssert / Deassert Readable Value/Offsets Event Data PEF A ction SDR Record Type Tach Fan 6 20h Fan 04h Threshold 01h [u,l][ c,nc] As & De Analog R, T Fault LED Action 01 Tach Fan 7 21h Fan 0 ...

  • Intel SE7520JR2 - page 141

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 141 ...

  • Intel SE7520JR2 - page 142

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 142 5.3.20 IMM BMC Sensor Support The following tables are for the built-in and the external sensors for the platform when either an Intel Management Module Professional or Advanced is installed. Table 56. Platform Sensors for Intel Management Modules - Professional and Adva ...

  • Intel SE7520JR2 - page 143

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 143 Sensor Name Sensor Number Sensor Type Event / Reading Type Event Offset Triggers A ssert / Deassert Readable Value / Offsets EventData Rearm Standby Critical Inerrupt Sensor 07h Critical Interrupt 13h Sensor Specific 6Fh Front Panel NMI Bus Error As & De – T rig Of ...

  • Intel SE7520JR2 - page 144

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 144 Sensor Name Sensor Number Sensor Type Event / Reading Type Event Offset Triggers A ssert / Deassert Readable Value / Offsets EventData Rearm Standby Tach Fan 1 40h Fan 04h Threshold 01h [u,l][nr,c,nc] As & De Analog R, T M – Tach Fan 2 41h Fan 04h Threshold 01h [u, ...

  • Intel SE7520JR2 - page 145

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 145 Sensor Name Sensor Number Sensor Type Event / Reading Type Event Offset Triggers A ssert / Deassert Readable Value / Offsets EventData Rearm Standby Digital Fan 10 59h F an 04h Digital Discrete 06h Performance Met or Lags As & De – Trig Offset M – Digital Fan 11 ...

  • Intel SE7520JR2 - page 146

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 146 Sensor Name Sensor Number Sensor Type Event / Reading Type Event Offset Triggers A ssert / Deassert Readable Value / Offsets EventData Rearm Standby System Event 83h System Event 12h Sensor Specific 6Fh OEM System Boot Event (Hard Reset) PEF Action As – Trig Offset A ? ...

  • Intel SE7520JR2 - page 147

    Intel® Server Board SE7520JR2 Platform Management Revision 1.0 C78844-002 147 Sensor Name Sensor Number Sensor Type Event / Reading Type Event Offset Triggers A ssert / Deassert Readable Value / Offsets EventData Rearm Standby Processor 2 Status 91h Processor 07h Sensor Specific 6Fh IERR Thermal Trip FRB1, FRB2, FRB3 Config Error Presence Disabled ...

  • Intel SE7520JR2 - page 148

    Platform Management Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 148 Sensor Name Sensor Number Sensor Type Event / Reading Type Event Offset Triggers A ssert / Deassert Readable Value / Offsets EventData Rearm Standby DIMM 4 E3h Slot Connector 21h Sensor Specific 6Fh Fault Status Asserted Device Installed Disabled As – Trig Offset A – ...

  • Intel SE7520JR2 - page 149

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 149 6. Error Reporting and Handling This section defines how errors are handled. Also discussed is the role of the BIOS in error handling and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling. In additi ...

  • Intel SE7520JR2 - page 150

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 150 system reset (ASR). The Sahalee BMC retains status bits that can be read by the BIOS later in the POST for the purpose of disabling the previously failing processor, logging the appropriate event into the System Event Log (SEL), and displaying an appropriate err ...

  • Intel SE7520JR2 - page 151

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 151 If the BIOS is going to boot to a known PXE-compliant device, then the BIOS reads a user option for OS Watchdog Timer for PXE Boots and either disables the timer or enables the timer with a value read from the option (5, 10, 15, or 20 minutes). If the OS Watchdo ...

  • Intel SE7520JR2 - page 152

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 152 does not alter the BSP and attempts to boot from the original BSP. Error messages are displayed on the console, and errors are logged in the event log of a processor failure. If the user replaces a processor that has been marked bad by the system, the system mus ...

  • Intel SE7520JR2 - page 153

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 153 The following table shows memory error handling with both a mBMC and Sahalee BMC. Table 57: Memory Error Handling mBMC v s Sahalee Memory with RAS mode Server with mBMC Server with IMM Sahalee BMC Sparing mode / Mirroring mode When Sparing or Mirroring occurs: - ...

  • Intel SE7520JR2 - page 154

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 154 In non-RAS mode, BIOS will assert a Non-Maskable-Interrupt (NMI) on the first Double Bit ECC (DBE) error. Table 58: Memory Error Handling in non-RAS mode Non-RAS mode Server with mBMC Server with IMM Sahalee BMC Single Bit ECC (SBE) errors SBE error events will ...

  • Intel SE7520JR2 - page 155

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 155 6.3 Error Logging This section defines how errors are handled by the system BIOS. Also discussed is the role of the BIOS in error handling and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling. In a ...

  • Intel SE7520JR2 - page 156

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 156 6.3.4 Memory Bus Error The hardware is programmed to generate an SMI on single-bit data errors in the memory array if ECC memory is installed. The SMI handler records the error and the DIMM location to the system event log. Double-bit errors in t he memory array ...

  • Intel SE7520JR2 - page 157

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 157 Gate20 Error T he BIOS is unable to properly control the motherboard’s Gate A20 function, which controls access of memory over 1 MB. This may indicate a problem with the motherboard. Multi-Bit ECC Error This message will only occur on sy stems using ECC enable ...

  • Intel SE7520JR2 - page 158

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 158 Message Displayed Description detect and configure IDE/ATAPI devices in POST. Primary Slave Hard Disk Error The IDE/ ATAPI device configured as Primary Slave could not be properly initialized by the BIOS. This message is typically display ed when the BIOS is try ...

  • Intel SE7520JR2 - page 159

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 159 Message Displayed Description configure IDE/ATAPI devices in POST. Secondary Master Drive - ATAPI Incompatible T he IDE/ATAPI device confi gured as Secondary Master failed an ATAPI compatibility test. This message is typically display ed when the BIOS is trying ...

  • Intel SE7520JR2 - page 160

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 160 Message Displayed Description when it detects an imminent failure. This message can be reported by an ATAPI device using the S.M.A.R.T. error repor ting standard. S.M.A.R.T. failure messages may indicate the need to replace the hard disk. Table 62: Virus Related ...

  • Intel SE7520JR2 - page 161

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 161 Message Displayed Descriptio n of channel 2 of the 8254 timer. This may indicate a problem with sy stem hardware. Interrupt Controller-1 error BIOS POST could not initialize t he Master Interrupt Controller. This may indicate a problem with sy stem hardware. Int ...

  • Intel SE7520JR2 - page 162

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 162 Message Displayed Description bit data structure while the U SB is ported w ith 32-bit data structure. Table 67: SMBIOS BIOS Error Messages Message Displayed Description Not enough space in Runtime area!! . SMBIOS data will not be available. This message is disp ...

  • Intel SE7520JR2 - page 163

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 163 Error Code Error Message Respo nse 0012 CMOS time not set Pause 0014 PS2 Mouse not found Not an error 0040 Refresh timer test failed Halt 0041 Display memory test failed Pause 0042 CMOS Display Type Wrong Pause 0043 ~<INS> Pressed Pause 0044 DMA Controller ...

  • Intel SE7520JR2 - page 164

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 164 Error Code Error Message Respo nse 8130 Processor 01 disabled Warning 8131 Processor 02 disabled Warning 8140 Processor 01 failed FRB-3 timer Warning 8141 Processor 02 failed FRB-3 timer Warning 8150 Processor 01 failed initialization on last boot. Warning 8151 ...

  • Intel SE7520JR2 - page 165

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 165 Error code Error messages 196 Processor cache mismatch detected. 198 Processor speed mismatch detected. 00019700 Processor P0 failed BIST. 00019701 Processor P1 failed BIST. 00150100 Multi-bit error occurred: forcing NMI DIMM = ?? 00150100 Multi-bit error occurr ...

  • Intel SE7520JR2 - page 166

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 166 Table 71: Troubleshooting BIOS Beep Codes Number of Beeps Troubleshooting Ac tion 1, 2 or 3 Reseat the memory, or replace with know n good modules. 4-7, 9-11 Fatal error indicating a serious problem wi th the system. Consult your sy stem manufacturer. Before dec ...

  • Intel SE7520JR2 - page 167

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 167 Table 73: BMC Beep Code Code Reason for Beep 1 Front panel CMOS clear initiated 1-5-1-1 FRB failure (processor failure) 1-5-2-1 No processors installed or processor socket 1 is empty. 1-5-2-3 Processor configuration error (e.g., mi smatched VIDs, Processor slot ...

  • Intel SE7520JR2 - page 168

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 168 Result Amber Green Red Off MSB LSB Figure 24. Location of Diagnostic LEDs on Baseboard 6.5.3 POST Code Checkpoints Table 75: POST Code Checkpoints Diagnostic LED Decoder G=Green, R=Red, A=Amber Checkpoint MSB LSB Description 03 OFF OFF G G Disable NMI, parity, v ...

  • Intel SE7520JR2 - page 169

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 169 Diagnostic LED Decoder G=Green, R=Red, A=Amber Checkpoint MSB LSB Description C6 R A G OFF Re-enable cache for boot strap processor C7 R A G G Early CPU Init Exit 0A G OFF G OFF Initializes the 8042 compatible Key Board Controller. 0B G OFF G G Detects the prese ...

  • Intel SE7520JR2 - page 170

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 170 Diagnostic LED Decoder G=Green, R=Red, A=Amber Checkpoint MSB LSB Description 8C A G OFF OFF Late POST initia lization of chipset registers. 8D A G OFF G Build ACPI tables (if ACPI is supported) 8E A G G OFF Program the peripheral par ameters. Enable/Disabl e NM ...

  • Intel SE7520JR2 - page 171

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 171 Diagnostic LED Decoder G=Green, R=Red, A=Amber Checkpoint MSB LSB Description D4 R A OFF R Test base 512KB memory. Adjust policies and cache first 8MB. Set stack. D5 R A OFF A Bootblock code is copied from ROM to lower system memory and control is given to it. B ...

  • Intel SE7520JR2 - page 172

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 172 Diagnostic LED Decoder G=Green, R=Red, A=Amber Checkpoint MSB LSB Description FA A R A R Check the validity of the recovery file configurati on to the current configuration of the flash part. FB A R A A Make flash write enabled through ch ipset and OEM specific ...

  • Intel SE7520JR2 - page 173

    Intel® Server Board SE7520JR2 Error Reporting and Handling Revision 1.0 C78844-002 173 6.5.7 ACPI Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The following table describes the type of checkpoints that may occur during ACPI sleep or wake events: Table 79: ACPI Runti ...

  • Intel SE7520JR2 - page 174

    Error Reporting and Handling Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 174 Tpoint Description 0E5h MEM_ERR_SIZE_MISMATCH 0E6h MEM_ERR_ECC_MISMATCH 0E8h MEM_ERR_ROW_ADDR_BITS 0E9h MEM_ERR_INTERNAL_BANKS 0EAh MEM_ERR_TIMING 0EBh MEM_ERR_INST_ORDER_ERR 0ECh MEM_ERR_NONREG_MIX 0EDh MEM_ERR_LATENCY 0EEh MEM_ERR_NOT_SUPPORTED 0EFh MEM_ERR_CO ...

  • Intel SE7520JR2 - page 175

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 175 7. Connectors and Jumper Blocks 7.1 Power Connectors The main power supply connection is obtained using a SSI Compliant 2x12 pin connector. In addition, there are three additional power related connectors; one SSI compliant 2x4 pin power connector (J4J1) providi ...

  • Intel SE7520JR2 - page 176

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 176 Table 83: Pow er Supply Signal Connector (J1G1) Pin Signal Color 1 5VSB_SCL Orange 2 5VSB_SDA Black 3 PS_ALTER_L, Not used Red 4 3.3V SENSE- Yellow 5 3.3V SENSE+ Green Table 84: IDE Pow er Connector Pinout (U2E1) Pin Signal 1 GND 2 5V VCC 7.2 Riser Slots The bas ...

  • Intel SE7520JR2 - page 177

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 177 Pin- Side B PCI Spec Signal Description Pin- Side A PCI Spec Signal Description 96 + 5V 96 INT A# T his pin will be connected on the 2U riser to INT_A# of the bottom PCI slot, INT_D# of the middle slot and INT_C# of the top slot. 95 INT B# This pin will be conne ...

  • Intel SE7520JR2 - page 178

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 178 Pin- Side B PCI Spec Signal Description Pin- Side A PCI Spec Signal Description 62 GND 62 FRAME# 61 IRDY# 61 GND KEYWAY KEYWAY KEYWAY KEYWAY 60 +3.3V 60 TRDY# 59 DEVSEL# 59 GND 58 PCI-XCAP 58 STOP# 57 LOCK# 57 +3.3V 56 PERR# 56 SMBD Daisy chain to all slots 55 + ...

  • Intel SE7520JR2 - page 179

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 179 Pin- Side B PCI Spec Signal Description Pin- Side A PCI Spec Signal Description 24 AD[57] 24 GND 23 GND 23 AD[56] 22 AD[55] 22 AD[54] 21 AD[53] 21 V (I/O) 3.3V or 1.5V 20 GND 20 AD[52] 19 AD[51] 19 AD[50] 18 AD[49] 18 GND 17 V (I/O) 3.3V or 1.5V 17 AD[48] 16 AD[ ...

  • Intel SE7520JR2 - page 180

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 180 Table 86: Full-height Riser Slot Pinout Pin-Side B PCI Spec Signal Description Pin-Side A PCI Spec Signal Description 140 12V 140 12V 139 12V 139 12V 138 Ground 138 GND 137 -12V 137 3.3VAux 375ma per slot and 3 slots 136 12V 136 Wake# 135 GND 135 12V Two slots = ...

  • Intel SE7520JR2 - page 181

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 181 Pin-Side B PCI Spec Signal Description Pin-Side A PCI Spec Signal Description 101 HSOn(7) 101 GND 100 GND 100 HSIp(7) 99 +5V 99 HSIn(7) 98 INT B# This pin will be connected on the 2U riser to INT_B# of the bottom PCI slot, INT_A# of the middle slot and INT_D# of ...

  • Intel SE7520JR2 - page 182

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 182 Pin-Side B PCI Spec Signal Description Pin-Side A PCI Spec Signal Description 77 +3.3V Was Vio 3.3V or 1.5V 77 GNT1# Lowest PCI slot (SLOT1) 76 PME2# active riser only, PME needed per PCI segment, reserved for passive riser 76 Ground 75 AD[31] 75 PME1# for passi ...

  • Intel SE7520JR2 - page 183

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 183 Pin-Side B PCI Spec Signal Description Pin-Side A PCI Spec Signal Description 38 Ground 38 AD[02] 37 AD[01] 37 AD[00] 36 +3.3V Was Vio 3.3V or 1.5V 36 +3.3V Was Vio 3.3V or 1.5V 35 ACK64# 35 REQ64# 34 +5V 34 +5V 33 +5V 33 +5V 32 Reserved 32 + 5V W as gnd 31 Grou ...

  • Intel SE7520JR2 - page 184

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 184 Pin-Side B PCI Spec Signal Description Pin-Side A PCI Spec Signal Description (2U)01=3x PCI (2U)10=PXH 3 PCI-X-D (2U)11=No Riser 1 Size 0=1U, 1 = 2U 1 PXH_PWR OK Input to indicate to PXH on active riser that baseboard power is OK 7.3 System Management Headers Th ...

  • Intel SE7520JR2 - page 185

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 185 FMC Signal Name FMC Pin Description FML_SINTEX 27 Fast Management Link Slave Interrup t/Clock Extension. This signal is driven by the FML Slave, and has a dual usage: Used as an Alert signal for the slave to notify master that data is ready to be read from slave ...

  • Intel SE7520JR2 - page 186

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 186 FMC Signal Name FMC Pin Description LAN_I2C_3VSB_SCL 58 LAN usage HDD_FLT_LED_N 64 Drive Fault LE D output driven when FMM detects a bad drive from the Hot Swap controller on the Hot Sw ap disk Drive sub-system. FMM_PS_PWR_ON_N 65 Power On Request to the sy stem ...

  • Intel SE7520JR2 - page 187

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 187 FMC Signal Name FMC Pin Description FMM_RI_BUF_N 97 Ring Indicator from the EMP serial port on the baseboard RST_PWRGD_PS 101 Power good signal from pow er subsystem. In typical sy stem, this signal is connected to PWR_OK signal on power supply . This signal is ...

  • Intel SE7520JR2 - page 188

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 188 Table 89: IPMB Connector Pin-out (J3F1) Pin Signal Name Description 1 Local I2C SDA BMC IMB 5 V STNDBY Data Line 2 GND 3 Local I2C SCL BMC IMB 5 V STNDBY Clock Line ...

  • Intel SE7520JR2 - page 189

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 189 7.3.4 OEM RMC Connector (J3B2) A white eight pin connector (J3B2) used for OEM specific management cards. Table 90: OEM RMC Connector Pinout (J3B2) Pin Signal Name Description 1 PERIPH_I2C_3VSB_SDA 2 PERIPH_I2C_3VSB_SCL 3 POST_STAT US 4 +5V 5 GROUND 6 5V_STBY 7 ...

  • Intel SE7520JR2 - page 190

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 190 Pin Signal Name Pin Signal Name A20 GND B20 FP_PWR_LED_L A21 P5V_STBY B21 RST _IDE_S_L A22 RST_IDE_L B22 FD_HDSEL_L A23 FD_DSKCHG_L B23 FD_RDATA_L A24 FD_WPD_L B24 FD_WDATA_L A25 FD_TRK0_L B25 FD_ST EP_L A26 FD_WGATE_L B26 FD_MTR0_L A27 FD_DIR_L B27 FD_DENSEL0 A ...

  • Intel SE7520JR2 - page 191

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 191 Pin# Signal Name Pin # Signal Name 19 LAN_ACT_B_L 20 FP_RST_BT N_L 21 PS_I2C_5VSB_SDA 22 GND 23 PS_I2C_5VSB_SCL 24 FP_ID_BTN_L 25 FP_CHASSIS_INTRU 26 TP_J1H5_26 27 LAN_LINKA_L 28 LAN_ACT_A_L 29 GND 30 FP_NMI_BT N_L 31 SPB_EN_L 32 SPB_DSR 33 SPB_SOUT 34 SPB_SIN 3 ...

  • Intel SE7520JR2 - page 192

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 192 Figure 25. 34-Pin SSI Compliant Control Panel Header 7.5 I/O Connectors 7.5.1 VGA Connector The following table details the pin-out definition of the VGA connector. Table 94: VGA Connector Pin-out Pin Signal Name 1 Red (analog color signal R) 2 Green (analog col ...

  • Intel SE7520JR2 - page 193

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 193 Pin Signal Name 12 DDCDAT 13 HSYNC (horizontal sync) 14 VSYNC (vertical sync) 15 DDCCLK 7.5.2 NIC Connectors The Server Board SE7520JR2 provides two RJ45 NIC connectors oriented side by side on the back edge of the board. The pin-out for each connector is identi ...

  • Intel SE7520JR2 - page 194

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 194 Pin# Signal Name Signal Name Pin# 2 +DB(13) -DB(13) 36 3 +DB(14) -DB(14) 37 4 +DB(15) -DB(15) 38 5 +DB(P1) -DB(P1) 39 6 +DB(0) -DB(0) 40 7 +DB(1) -DB(1) 41 8 +DB(2) -DB(2) 42 9 +DB(3) -DB(3) 43 10 +DB(4) -DB(4) 44 11 +DB(5) -DB(5) 45 12 +DB(6) -DB(6) 46 13 +DB(7 ...

  • Intel SE7520JR2 - page 195

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 195 Pin Signal Name Pin Signal Name 1 RST_IDE_P_L 2 GND 3 IDE_PDD_7 4 IDE_PDD_8 5 IDE_PDD_6 6 IDE_PDD_9 7 IDE_PDD_5 8 IDE_PDD_10 9 IDE_PDD_4 10 IDE_PDD_11 11 IDE_PDD_3 12 IDE_PDD_12 13 IDE_PDD_2 14 IDE_PDD_13 15 IDE_PDD_1 16 IDE_PDD_14 17 IDE_PDD_0 18 IDE_PDD_15 19 ...

  • Intel SE7520JR2 - page 196

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 196 Table 99: Legacy 34-pin Floppy Dr ive Connector Pin-out (J3K2) Pin Signal Name Pin Signal Name 1 GND 2 FD_DENSEL0 3 GND 4 Test Point 5 KEY 6 FD_DENSEL1 7 GND 8 FD_INDEX_L 9 GND 10 FD_MT R0_L 11 GND 12 FD_DS1_L 13 GND 14 FD_DS0_L 15 GND 16 FD_MTR1_L 17 Test Point ...

  • Intel SE7520JR2 - page 197

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 197 3 RXD (receive data) 4 RTS (request to send) 5 TXD (Transmit data) 6 CTS (clear to send) 7 DTR (Data terminal ready) 8 RI (Ring Indicate) 9 Ground 7.5.8 Keyboard and Mouse Connector Two stacked PS/2 ports are provided to support both a keyboard and a mouse. Eith ...

  • Intel SE7520JR2 - page 198

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 198 4 GND One internal 1x10 connector on the baseboard (J1F1) provides an option to support an additional two USB 2.0 ports. This connector is used in both the Intel Server Chassis SR1400 1U and SR2400 2U bringing USB support to the control panel. The pin-out of the ...

  • Intel SE7520JR2 - page 199

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 199 There are two SSI compliant processor fan headers, CPU1 (J7F1) and CPU2 (J5F2), which are not fan speed controlled. They are powered by a constant +12V. The pinout for these two connector is defined in the following table. Table 106: CPU1/CPU2 Fan Conn ector Pin ...

  • Intel SE7520JR2 - page 200

    Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 200 24 BB_FAN_LED6_R IN The 1x3 fan header (J3K3) is used to control a syst em fan in the Intel Server Chassis SR1400. The pinout for this connector is found in the following table. Table 108: 3-Pin Fan Speed Controlled Fan Header (J3K3) Pin Signal Name Ty pe Descri ...

  • Intel SE7520JR2 - page 201

    Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Revision 1.0 C78844-002 201 7.8 Jumper Blocks The baseboard has several jumper blocks used to configure or enable/disable various features. This section describes the usage and settings of each. Table 111: Jumper Block Definitions Reference ID Name Description Settings J1H2 (A) CMOS Clear ...

  • Intel SE7520JR2 - page 202

    Design and Environmental Specifications Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 202 8. Design and Environment al Specifications 8.1 Server Board SE7520JR2 Design Specification Operation of the Server Board SE7520JR2 at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute ...

  • Intel SE7520JR2 - page 203

    Intel® Server Board SE7520JR2 Design and Environmental Specifications Revision 1.0 C78844-002 203 Note : The following diagram shows the power harness spec drawing as defined for use in Intel server chassis. Reference chassis designs may or may not require all of the connectors shown and different wiring material may be needed to m eet specific pl ...

  • Intel SE7520JR2 - page 204

    Design and Environmental Specifications Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 204 P1 Main Power Connector • Connector housing: 24-pin Molex* Mini-Fit Jr. 39-01-2245 or equivalent • Contact: Molex Mini-Fit, HCS, female, crimp 44476 or equivalent Table 113: P1 Main Pow er Connector Pin SIgnal 18 A WG Color Pin SIgnal 18 AWG Color ...

  • Intel SE7520JR2 - page 205

    Intel® Server Board SE7520JR2 Design and Environmental Specifications Revision 1.0 C78844-002 205 P3 Power Signal Connector • Connector housing: 5-pin Molex 50-57-9705 or equivalent • Contacts: Molex 16-02-0087 or equivalent Table 115: P3 Baseboard Signal Connector Pin SIgnal 24 AWG Color 1 I2C Clock W hite/Green Stripe 2 I2C Data White/Yellow ...

  • Intel SE7520JR2 - page 206

    Design and Environmental Specifications Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 206 enclosure). This grounding must be designed to ensure passing the maximum allowed Common Mode Noise levels. The power supply shall be provided with a reliable protective earth ground. All secondary circuits shall be connected to protective earth groun ...

  • Intel SE7520JR2 - page 207

    Intel® Server Board SE7520JR2 Design and Environmental Specifications Revision 1.0 C78844-002 207 8.2.5 Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise. All outputs are measured with refer ...

  • Intel SE7520JR2 - page 208

    Design and Environmental Specifications Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 208 8.2.7 Capacitive Loading The power supply shall be stable and meet all requirements with the following capacitive loading ranges. Table 120: Capacitve Loading Conditions Output MIN MAX Units +3.3V 250 6,800 µ F +5V 400 4,700 µ F +12V(1, 2, 3) 500 ea ...

  • Intel SE7520JR2 - page 209

    Intel® Server Board SE7520JR2 Design and Environmental Specifications Revision 1.0 C78844-002 209 8.2.11 Soft Starting The power supply shall contain control circuit that provides monotonic soft start for its outputs without overstress of the AC line or any power supply components at any specified AC line or load conditions. There is no requiremen ...

  • Intel SE7520JR2 - page 210

    Design and Environmental Specifications Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 210 Figure 28. Output Voltage Timing Table 123: Turn On/Off Timing Item Description Minimum Maximum Units T sb_on_delay Delay from AC being applied to 5VSB being within regulation. 1500 msec T ac_on_delay Delay from AC being applied to all output voltages ...

  • Intel SE7520JR2 - page 211

    Intel® Server Board SE7520JR2 Design and Environmental Specifications Revision 1.0 C78844-002 211 Figure 29. Turn On/Off Timing (Pow er Supply Signals) 8.2.14 Residual Voltage Immunity in Standby Mode The PS supply should be immune to any residual voltage placed on its outputs (Typically a leakage voltage through the system from standby output) up ...

  • Intel SE7520JR2 - page 212

    Design and Environmental Specifications Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 212 8.3 Product Regulatory Compliance 8.3.1 Product Safety Compliance The Server Board SE7520JR2 complies with the following safety requirements: • UL60950 – CSA 60950(USA / Canada) • EN60950 (Europe) • IEC60950 (International) • CB Certificate ...

  • Intel SE7520JR2 - page 213

    Intel® Server Board SE7520JR2 Design and Environmental Specifications Revision 1.0 C78844-002 213 8.3.3 Certifications / Regi strations / Declarations • UL Certification (US/Canada) • CE Declaration of Conformity (CENELEC Europe) • FCC/ICES-003 Class A Attestation (USA/Canada) • C-Tick Declaration of Conformity (Australia) • MED Declarat ...

  • Intel SE7520JR2 - page 214

    Design and Environmental Specifications Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 214 8.4 Electromagnetic Compatibility Notices 8.4.1 FCC (USA) This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any ...

  • Intel SE7520JR2 - page 215

    Intel® Server Board SE7520JR2 Design and Environmental Specifications Revision 1.0 C78844-002 215 This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled: “Digital Apparatus,” ICES-003 of the Canadian Department of Communications. ...

  • Intel SE7520JR2 - page 216

    Miscellaneous Board Information Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 216 9. Miscellaneous Board Information 9.1 Updating the System Software To ensure your Server Board SE7520JR2 has the latest board fixes, it is highly recommended to load the latest system software. Thes e include System BIOS, mBMC firmware, and FRUSDR Utility. I ...

  • Intel SE7520JR2 - page 217

    Intel® Server Board SE7520JR2 Miscellaneous Board Information Revision 1.0 C78844-002 217 • Replacing a bad baseboard • Adding/Removing a Redundancy Feature (IMM Systems Only) o Redundant Power Supplies o Redundant Fans • Adding/Removing a CPU fan (IMM Systems Only) Failure to run the FRUSDR Update Utility may cause the platform management s ...

  • Intel SE7520JR2 - page 218

    Miscellaneous Board Information Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 218 Clear state and power the system up. This feature can be enabled or disabled via the CMOS Clear Options command. The following sequence of events must occur to invoke the Control Panel CMOS Clear feature. 1. Standby power must be on, system power must be off, ...

  • Intel SE7520JR2 - page 219

    Intel® Server Board SE7520JR2 Miscellaneous Board Information Revision 1.0 C78844-002 219 • Recovery from multiple floppy disks. o Prepare 2 blank disks. o The first disk(disk0) must be made bootable o Copy amiboot.000 to disk0, and amiboot.001 to disk1. • Execute BIOS Recovery o set Recovery Boot Jumper by moving jumper J1H2 row B from Pins 1 ...

  • Intel SE7520JR2 - page 220

    ...

  • Intel SE7520JR2 - page 221

    Intel® Server Board SE7520JR2 Appendix A: Integration and Usage Tips Revision 1.0 C78844-002 221 Appendix A: Integration and Usage Tips The following Integration and Usage Tips are provided to assist with answering miscellaneous questions about the Server Board SE7520JR2 or as a guide to assist with troubleshooting common errors. • The use of DD ...

  • Intel SE7520JR2 - page 222

    Glossary Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 222 Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms followin ...

  • Intel SE7520JR2 - page 223

    Intel® Server Board SE7520JR2 Glossary Revision 1.0 C78844-002 223 Term Definition IFB I/O and firmw are bridge IMM Intel Management Module INTR IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-target probe KB 1024 bytes. KCS Keyboard controller style LAN Local area net ...

  • Intel SE7520JR2 - page 224

    Glossary Intel® Server Board SE7520JR2 Revision 1.0 C78844-002 224 Term Definition SEEPROM Serial electrically erasable programmable read-only memory SEL System Event Log SIO Server Input/output SMI Server management interrupt. SMI is t he highest priority nonmaskable interrupt. SMM Server management mode. SMS Server management softw are SNMP Simp ...

  • Intel SE7520JR2 - page 225

    Intel® Server Board SE7520JR2 Reference Documents Revision 1.0 C78844-002 225 Reference Documents Refer to the following documents for additional information: • Intel ® Server Board SE7520JR2 Server Management External Architecture Specification (EAS). Intel Corporation. • Intel ® Server Board SE7520JR2 BIOS External Product Specification. I ...

Manufacturer Intel Category Computer Hardware

Documents that we receive from a manufacturer of a Intel SE7520JR2 can be divided into several groups. They are, among others:
- Intel technical drawings
- SE7520JR2 manuals
- Intel product data sheets
- information booklets
- or energy labels Intel SE7520JR2
All of them are important, but the most important information from the point of view of use of the device are in the user manual Intel SE7520JR2.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Intel SE7520JR2, service manual, brief instructions and user manuals Intel SE7520JR2. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Intel SE7520JR2.

Similar manuals

A complete manual for the device Intel SE7520JR2, how should it look like?
A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Intel SE7520JR2 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Intel SE7520JR2.

A complete Intel manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

1. Preface and tips on how to use the manual Intel SE7520JR2 - At the beginning of each manual we should find clues about how to use the guidelines. It should include information about the location of the Contents of the Intel SE7520JR2, FAQ or common problems, i.e. places that are most often searched by users in each manual
2. Contents - index of all tips concerning the Intel SE7520JR2, that we can find in the current document
3. Tips how to use the basic functions of the device Intel SE7520JR2 - which should help us in our first steps of using Intel SE7520JR2
4. Troubleshooting - systematic sequence of activities that will help us diagnose and subsequently solve the most important problems with Intel SE7520JR2
5. FAQ - Frequently Asked Questions
6. Contact detailsInformation about where to look for contact to the manufacturer/service of Intel SE7520JR2 in a specific country, if it was not possible to solve the problem on our own.

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