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Manual Maxim DS33R11

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  • Maxim DS33R11 - page 1

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceive r ww w .maxim-ic.com GENERAL DESCRIPTION The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a T1/E1/J1 data stream. The device performs store-and-forward of packets with full wire-speed transport capability. The built- ...

  • Maxim DS33R11 - page 2

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 2 of 344 TABLE OF CONTENTS 1 DESCRIPTION ............................................................................................................................... .... 9 2 FEATURE HIGHLIGHTS ........................................................................................... ...

  • Maxim DS33R11 - page 3

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 3 of 344 9.14.1 DTE and DCE Mode ............................................................................................................................. 58 9.15 E THER NET MAC .......................................................................................................... ...

  • Maxim DS33R11 - page 4

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 4 of 344 10.17.4 FIFO Information ............................................................................................................................... ....96 10.17.5 Receive Packet-Bytes Available ................................................................................ ...

  • Maxim DS33R11 - page 5

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 5 of 344 12.4 E1 M ODE ............................................................................................................................... ..... 308 13 OPERATING PARAMETERS ....................................................................................................... ...

  • Maxim DS33R11 - page 6

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 6 of 344 LIST OF FIGURES Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) ......................................................................... 17 Figure 6-1. Main Block Diagram ........................................................................................... ...

  • Maxim DS33R11 - page 7

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 7 of 344 Figure 12-19. Transmit-Side 2.048MHz B oundary Timing (Elastic Store Enabled) ................................................ 307 Figure 12-20. Receive-Side Timing .................................................................................................................. ...

  • Maxim DS33R11 - page 8

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 8 of 344 LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ...................................................................................... 16 Table 7-1. Detailed Pin Descriptions ................................................................................. ...

  • Maxim DS33R11 - page 9

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 9 of 344 1 DESCRIPTION The DS33R11 provides interconnection and mapping functi onality between Ethernet Packet Systems and T1/E1/J1 WAN Time-Division Multiplexed (TDM ) systems. The device is compos ed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate Controller (CIR), ...

  • Maxim DS33R11 - page 10

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 10 of 344 The integrated Ethernet Mapper is software compatible wi th the DS33Z11 Ethernet mapper. There are a few things to note when porting a DS33Z11 application to this device: • The SPI and hardware modes are not supported. • RSER has been renamed to RSERI. • RCLK has been ren ...

  • Maxim DS33R11 - page 11

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 11 of 344 2 FEATURE HIGHLIGHTS 2.1 General • 256-pin, 27mm BGA package • 1.8V and 3.3V supplies • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes evaluation kit, dr iver source code, and reference designs • Ref ...

  • Maxim DS33R11 - page 12

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 12 of 344 2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver • Two additional independent HDLC controllers • Fast load and unload features for FIFOs • SS7 support for FISU transmit and receive • Independent 128-byte Rx and Tx buffers with interrupt support • ...

  • Maxim DS33R11 - page 13

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 13 of 344 2.9 T1/E1/J1 Line Interface • Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation • Fully software configurable • Short-haul and long-haul applications • Automatic receive sensitivity adjustments • Ranges ...

  • Maxim DS33R11 - page 14

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 14 of 344 2.12 T1/E1/J1 Framer • Fully independent transmit and receive functionality • Full receive and transmit path transparency • T1 framing formats include D4 (SLC-96) and ESF • Detailed alarm and status reporting with optional interrupt support • Large path and line error ...

  • Maxim DS33R11 - page 15

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 15 of 344 2.14 Test and Diagnostics • IEEE 1149.1 support • Programmable on-chip bit error-rate tester (BERT) • Pseudorandom patterns including QRSS • User-defined repetitive patterns • Daly pattern • Error insertion single and continuous • Total bit and errored bit counts ...

  • Maxim DS33R11 - page 16

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 16 of 344 2.15 Specifications Compliance The DS33R11 meets relevant telecommuni cations specifications. The following table provides the specifications and relevant sections that are applicable to the DS33R11. Table 2-1. T1-Related Telecommunications Specifications IEEE 802.3-2002—CSMA ...

  • Maxim DS33R11 - page 17

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 17 of 344 3 APPLICATIONS The DS33R11 is ideal for application areas such as trans parent LAN service, LAN ext ension, and Ethernet delivery over T1/E1/J1, T3/E3, OC-1 /EC-1, G.SHDSL, or HDSL2/4. For an example of a complete LAN-to-WAN design, refer to Application Note 3411: DS33Z11—Eth ...

  • Maxim DS33R11 - page 18

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 18 of 344 4 ACRONYMS AND GLOSSARY • BERT: Bit Error-Rate Tester • DCE: Data Communication Interface • DTE: Data Terminating Interface • FCS: Frame Check Sequence • HDLC: High-Level Data Link Control • MAC: Media Access Control • MII: Media Independent Interface • RMII: Re ...

  • Maxim DS33R11 - page 19

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 19 of 344 5 MAJOR OPERATING MODES Microprocessor control is possible through the 8-bit para llel control port and provides configuration for all the features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86 encapsulation. The integrated t ...

  • Maxim DS33R11 - page 20

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 20 of 344 6 BLOCK DIAGRAMS Figure 6-1. Main Block Diagram TTIP TRING RTIP RRING SYSCLKI (RMII MODE) RXD[0:1] RX_CLK CRS_DV RX_ERR REF_CLK REF_CLKO TX_EN TXD[0:1] MDC MDIO MCLK TDCLKI TDCLKO TPOSI TPOSO TNEGI TNEGO TCHBLK TCHCLK TCLKT TSERI TSERO TCLKE TDEN JTAG Pin s LIUC RDCLKI RDCLKO R ...

  • Maxim DS33R11 - page 21

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 21 of 344 Figure 6-2. Block Diagra m of T1/E1/J1 Transceiver TX LIU CLO C K ADAPT ER BACKPL ANE INTERFACE CIRCUIT HOST I NTE RF AC E T1/ E1 /J 1 NETWORK CLOCK JTAG ES IB RX LIU JITTER ATTENUA TOR LOCAL LOOPBACK REMOTE LOOPBACK FRAMER LOOPBACK PAYLOAD LOOPBACK MUX MUX EXTERNAL ACCESS TO R ...

  • Maxim DS33R11 - page 22

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 22 of 344 Figure 6-3. Receive and Transmit T1/E1/J1 LIU LOCAL LOOPBACK TRI NG TTIP JI TTER AT TENU ATOR TRAN SMIT OR RECEI VE PATH RECEIVE LINE I/F RRING RTIP REMOTE LO OPBACK VCO / PLL MCLK 8XCLK 32 .7 68MH z XTALD RPOSO RNEGO RNEGI RPOSI TPOS I TNEGI TNEGO TPOS O RDCLKO RDCLKI TDCLKI T ...

  • Maxim DS33R11 - page 23

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 23 of 344 Figure 6-4. Receive and Transmit T1/E1/J1 Framer RECEIVE FRAM ER TRAN SMIT FRAM ER DATA CLOCK SYNC SYNC CLOCK DATA FRAME R LOOP BACK XMIT HDLC # 1 MAPPER XMIT HDLC # 2 MAPPER 128 B yt e FIFO 128 B yt e FIFO MAPPER M APPER REC HDLC # 1 REC HDLC # 2 128 B yt e FIFO 128 B yt e FIF ...

  • Maxim DS33R11 - page 24

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 24 of 344 Figure 6-5. T1/E1/J1 Backplane Interface RLINK RLCLK RSIG RSIGFR RSERO RCLKO RSYNC RDATA RFSYN C RMSYNC ELASTIC STORE SIGNAL ING BUFF ER Sa BIT /FDL EXTRACTION DATA CLOCK SYN C RCHBLK RCHCLK CHANNEL TIMING RSYSCLK TSERI TSI G TSSY NC TSYNC TDATA TESO TCHBLK TCHCLK TLI NK TLCL K ...

  • Maxim DS33R11 - page 25

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 25 of 344 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG patterns. LEGEND: I = input, O = output, Ipu = input with pullup, Oz = output with tri-state, IO = bidire ctional ...

  • Maxim DS33R11 - page 26

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 26 of 344 NAME PIN TYPE FUNCTION RD / DS B11 I Read Data Strobe (Intel Mode): The DS33R11 drives the data bus (D0-D7) with the contents of the addressed register while RD and CS are both low. Data Strobe (Motorola Mode): Used to latch data through the microprocessor interface. DS must be ...

  • Maxim DS33R11 - page 27

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 27 of 344 NAME PIN TYPE FUNCTION MII/RMII PHY PORT COL_DET N18 I Collision Detect (MII): Asserted by the MAC PHY to indicate that a collision is occurring. In DCE Mode this signal should be connected to ground. This signal is only valid in half duplex mode, and is ignored in full duplex ...

  • Maxim DS33R11 - page 28

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 28 of 344 NAME PIN TYPE FUNCTION TXD[0] F19 TXD[1] F18 TXD[2] E20 TXD[3] E19 O Transmit Data 0 through 3(MII): TXD [3:0] is presented synchronously with the rising edge of TX_CLK. TXD [0] is the least significant bit of the data. W hen TX_EN is low the data on TXD should be ignored. Tran ...

  • Maxim DS33R11 - page 29

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 29 of 344 NAME PIN TYPE FUNCTION PHY MANAGEMENT BUS MDC C19 O Management Data Clock (MII): Clocks management data between the PHY and DS33R11. The clock is derived from theSYSCLKI, with a maximum frequency is 1.67MHz. The user must leave this pin unconnected in the DCE Mode. MDIO C20 IO ...

  • Maxim DS33R11 - page 30

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 30 of 344 NAME PIN TYPE FUNCTION SDATA[0] W2 SDATA[1] Y4 SDATA[2] Y2 SDATA[3] Y5 SDATA[4] Y3 SDATA[5] W5 SDATA[6] V5 SDATA[7] W6 SDATA[8] V6 SDATA[9] W4 SDATA[10] V4 SDATA[11] V2 SDATA[12] V3 SDATA[13] V1 SDATA[14] W3 SDATA[15] W1 SDATA[16] Y16 SDATA[17] Y17 SDATA[18] V18 SDATA[19] Y19 S ...

  • Maxim DS33R11 - page 31

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 31 of 344 NAME PIN TYPE FUNCTION T1/E1/J1 ANALOG LINE INTERFACE TTIP R1, R2 O Transmit Analog Tip Output for the T1/E1/J1 Transceiver: Analog line-driver outputs. Tw o connections are provided to improve signal quality. These pins connect via a 1:2 step-up transformer to the network. See ...

  • Maxim DS33R11 - page 32

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 32 of 344 NAME PIN TYPE FUNCTION TSIG B4 I Transmit Signaling Input for the T1/E1/J1 Transceiver: When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLKT when the transmit-side elastic store is disabled. Sample ...

  • Maxim DS33R11 - page 33

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 33 of 344 NAME PIN TYPE FUNCTION RSYNC G4 I/O Receive Sy nc for the T1/E1/J1 Transceiver: An extracted pulse, one RCLKO wide, is output at this pi n, which identifies either frame (TR.IOCR1.5 = 0) or multiframe (TR.IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via TR.IO ...

  • Maxim DS33R11 - page 34

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 34 of 344 NAME PIN TYPE FUNCTION ETHERNET MAPPER RECEIVE SERIAL INTERFACE RSERI H1 I Receive Serial Data Input to Ethernet Mapper: Receive Serial data arrives on the rising edge of RCLKI. Normally connected to RSERO. RCLKI F2 I Serial Interface Receive Clock Input to the Ethernet Mapper: ...

  • Maxim DS33R11 - page 35

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 35 of 344 NAME PIN TYPE FUNCTION TDCLKO C2 O Transmit Clock Output from the T1/E1/J1 Framer: Buffered clock that is used to clock data through the transmit-side formatter (either TCLKT or RDCLKI). This pin is normally tied to TDCLKI. TNEGI C3 I Transmit Negative-Data Input: Sampled on th ...

  • Maxim DS33R11 - page 36

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 36 of 344 NAME PIN TYPE FUNCTION HARDWARE AND STATUS PINS LIUC B2 I Line Interface Unit Connect: When a logic low is present on this input pin, the T1/E1/J1 Fram er and LIU are not internally connected. The line interface circuitry will be separated from the framer/formatter circuitry an ...

  • Maxim DS33R11 - page 37

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 37 of 344 NAME PIN TYPE FUNCTION SYSTEM CLOCKS SYSCLKI V8 I System Clock In for Ethernet Mapper: 100MHz System Clock input to the DS33R11, used for internal operation. This clock is buffered and provided at SDCLKO for the SDRAM interface. The DS33R11 also provides a divided ve rsion outp ...

  • Maxim DS33R11 - page 38

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 38 of 344 NAME PIN TYPE FUNCTION JTAG INTERFACE JTCLK1 A7 Ipu JTAG Clock 1 for the Ethernet Mapper: This signal is used to shift data into JTDI1 on the rising edge and out of JTDO1 on the falling edge. JTDI1 C9 Ipu JTAG Data In 1 for the Ethernet Mapper: Test instructions and data are cl ...

  • Maxim DS33R11 - page 39

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 39 of 344 NAME PIN TYPE FUNCTION POWER SUPPLIES RVDD K3, L1 — Receive Analog Positive Supply : Connect to 3.3V power supply. RVSS J1, J2, K2, L2, M2 — Receive Analog Signal Ground: Connect to the common supply ground. TVDD U1 – Transmit Analog Positive Supply : Connect to 3.3V powe ...

  • Maxim DS33R11 - page 40

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 40 of 344 Figure 7-1. 256-Ball BGA Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A RCHBLK TCHBLK RFSYNC TDATA TSSYNC JT CLK2 JTCLK1 RS T N.C. INT CS D6 D3 D0 VSS A6 A3 A0 REF_CLK REF_ CLKO B BPCLK LIUC TPOSI T SIG RCL JT DI2 JTDO1 JTRST2 J TMS2 VDD1.8 RD/DS D7 D4 D1 VDD1.8 A7 ...

  • Maxim DS33R11 - page 41

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 41 of 344 8 FUNCTIONAL DESCRIPTION The DS33R11 provides interconnection and mapping functi onality between Ethernet packet LANs and T1/E1/J1 WAN Time-Division Multiplexed (TDM ) systems. The device is compos ed of a 10/100 Ethernet MAC, packet arbiter, committed information rate controll ...

  • Maxim DS33R11 - page 42

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 42 of 344 Both the transmit and receive path of the integrated T1/E 1/J1 transceiver also have two HDLC controllers. The HDLC controllers transmit and receive data through the fr amer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a time slo ...

  • Maxim DS33R11 - page 43

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 43 of 344 9 ETHERNET MAPPER 9.1 Ethernet Mapper Clocks The DS33R11 clocks sources and functions are as follows: • Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can be continuous or gapped. • ...

  • Maxim DS33R11 - page 44

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 44 of 344 Figure 9-1. Clocking for the DS33R11 TTIP TRING RTIP RRING SYSCLKI REF_CLKO RX_CLK REF_CLK TX_CLK MDC MCLK XTALD 8XCLK BPCLK TDCLKI TDCLKO TSYSCLK TCHBLK TCHCLK TCLKT TCLKE TDEN JTCLK2 RDCLKI RDCLKO RSYSCL K RCHBL K RCHCL K RCLKO RCLKI RDEN TRANSMIT LIU RECEIVE LIU TRANSMIT FRA ...

  • Maxim DS33R11 - page 45

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 45 of 344 9.1.1 Ethernet Interface Clock Modes The Ethernet PHY interface has several different cl ocking requirements, depending on the mode of operation. Table 9-1 outlines the possible clocking modes for the Ether net Interface. The buffered REF_CLKO output is generated by division of ...

  • Maxim DS33R11 - page 46

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 46 of 344 9.2 Resets and Low Pow er Modes The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset signal resets the status and control registers on the chip (except the GL.CR1 . RST bit) to their default values and resets all the o ...

  • Maxim DS33R11 - page 47

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 47 of 344 9.3 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Apply 3.3V supplies, then apply 1.8V supplies. STEP 2: Reset the integrated Ethernet Mapper by pulling the RST pin low or by using the software reset bits outlined in Section 9.2 . Clear all re ...

  • Maxim DS33R11 - page 48

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 48 of 344 9.6 Device Interrupts Figure 9-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pi n. When an interrupt occurs, the host can read the Global Latched Status registers GL. ...

  • Maxim DS33R11 - page 49

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 49 of 344 Figure 9-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet 7 Receive A borted Packet 6 Receive Inv alid Packet Detected 5 Receive Small Packet Detect ed 4 Receive Large Packet Detect ed 3 Receive FCS Errored Packet Count 2 Receive A borted Packet Count 1 R ...

  • Maxim DS33R11 - page 50

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 50 of 344 9.7 Interrupt Information Registers The interrupt information registers provide an indicati on of which status registers (SR1 through SR9) are generating an interrupt. When an interrupt occurs, the hos t can read TR.IIR1 and TR.IIR2 to quickly identify which of the nine status ...

  • Maxim DS33R11 - page 51

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 51 of 344 9.11 Connections and Queues The multi-port devices in this product family provide bidirectional cross-c onnections between the multiple Ethernet ports and Serial ports when operating in software mode. A single connection is preserved in this single-port device to provide softwa ...

  • Maxim DS33R11 - page 52

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 52 of 344 It is recommended that the user reset the queue pointers fo r the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/c onnect procedure is not followed, incorrect data may be transmitted. The proper procedure for setting u ...

  • Maxim DS33R11 - page 53

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 53 of 344 9.13 Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33R11 allows for optional flow control based on the queue high wa termark or through host processor intervention. There are 2 basic mechanisms that are used ...

  • Maxim DS33R11 - page 54

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 54 of 344 9.13.1 Full Duplex Flow Control Automatic flow control is enabled by default. The hos t processor can disable this functionality with SU.GCR .ATFLOW. The flow control mechanism is governed by the high watermarks ( SU.RQHT ). The SU.RQLT low threshold can be used as indication t ...

  • Maxim DS33R11 - page 55

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 55 of 344 Figure 9-3. Flow Control Using Pause Control Frame Receive Queue Growth Receive Queue High W ater Mark Initiate Flo w con trol 8 Rx Data Receive Queue Low Wa te r 9.13.2 Half Duplex Flow Control Half duplex flow control uses a jamming sequence to exert backpressure on the trans ...

  • Maxim DS33R11 - page 56

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 56 of 344 9.14 Ethernet Interface Port The Ethernet port interface allows for direct connecti on to an Ethernet PHY. The interface consists of a 10/100Mbit/s MII/RMII interface and an Ethernet MAC. In RMII operation, the interface c ontains seven signals with a reference clock of 50 MHz. ...

  • Maxim DS33R11 - page 57

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 57 of 344 The MAC circuitry generates a frame status for every frame t hat is received. This real time status can be read by SU.RFSB0 to SU.RFSB3 . Note the frame status is the “real ti me” status and hence the value will change as new frames are received. Hence the real time status ...

  • Maxim DS33R11 - page 58

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 58 of 344 9.14.1 DTE and DCE Mode The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE Mode it can be connected to an Ethernet PHY. In DCE m ode, the port can be connected to MII/RMII MAC devices other than an Ethernet PHY. The DTE/DCE ...

  • Maxim DS33R11 - page 59

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 59 of 344 Figure 9-6. DS33R11 Configured as a DCE in MII Mode MAC TXD[3:0] RXD[3:0] TX_CLK RX_CLK TX_ER R RX_ERR TX_EN RX_CRS COL_DET COL_DET DTE DCE TX_EN RX DV MDC MDIO TXD[3:0] RXD[3:0] TX_CLK DS33Z11 MAC RX_CLK RXDV RX_CRS MDIO MDC Rx Tx Tx Rx 9.15 Ethernet MAC Indirect addressing is ...

  • Maxim DS33R11 - page 60

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 60 of 344 Table 9-6. MAC Control Registers ADDRESS REGISTER DESCRIPTION 0000h-0003h SU.MACCR MAC Control Register. This register is used for programming full duplex, half duplex, promiscuous mode, and back-off limit for half duplex. The transmit and receive enable bits must be set for th ...

  • Maxim DS33R11 - page 61

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 61 of 344 9.15.1 MII Mode Options The Ethernet interface can be configured for MII operati on by setting the hardware pin RMIIMIIS low. The MII interface consists of 17 pins. For instructions on clocki ng the Ethernet Interface while in MII mode, see Section 9.1 . Diagrams of system conn ...

  • Maxim DS33R11 - page 62

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 62 of 344 9.15.3 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for data. The ...

  • Maxim DS33R11 - page 63

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 63 of 344 9.16.1 Receive Data Interface 9.16.1.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receiv e pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least sig ...

  • Maxim DS33R11 - page 64

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 64 of 344 9.16.2 Repetitive Pattern Synchronization Repetitive pattern synchronization sync hronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by sear ching each incoming data stream bit position for the repetitive pat ...

  • Maxim DS33R11 - page 65

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 65 of 344 9.16.4.1 Error Insertion Error insertion inserts errors into t he outgoing pattern data stream. Errors are inserted one at a time Single bit error insertion can be initiated from the microprocessor interf ace. If pattern inversion is enabled, the data stream is inverted before ...

  • Maxim DS33R11 - page 66

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 66 of 344 9.18 Receive Packet Processor The Receive Packet Processor accepts data from the Re ceive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abor t detection, destuffing, packet size checking, FCS error monitoring, FCS byte ext ...

  • Maxim DS33R11 - page 67

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 67 of 344 Bit reordering changes the bit order of each byte. If bit reordering is dis abled, the incoming 8-bit data stream DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[7] (or 15, 23, or 31) and the LSB in RFD[0] (or 8, 16, or ...

  • Maxim DS33R11 - page 68

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 68 of 344 9.19 X.86 Encoding and Decoding X.86 protocol provides a method fo r encapsulating Ethernet Frame onto L APS. LAPS provides HDLC type framing structure for encapsulation of Ethernet frames. L APS encapsulated frames can be used to send data onto a SONET/SDH network. The DS33R11 ...

  • Maxim DS33R11 - page 69

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 69 of 344 Figure 9-13. X.86 Encapsulation of the MAC frame Flag(0x7E) Address(0x04) Control(0x03) 1st Octect o f SAPI(0xfe ) 2nd Octect of SAPI (0x01) Destinati on Adrs(DA) Source Adrs( SA) Length/Type Number of B ytes 1 1 1 1 1 6 6 2 MAC Client Data 46-1500 PAD FCS for MA C 4 FCS for L ...

  • Maxim DS33R11 - page 70

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 70 of 344 The X86 received frame is aborted if: • If 7d,7E is detected. This is an abort packet sequence in X.86. • Invalid FCS is detected. • The received frame has less than 6 octets. • Control, SAPI and address field are mismatched to the programmed value. • Octet 7d and oct ...

  • Maxim DS33R11 - page 71

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 71 of 344 9.20 Committed Information Rate Controller The DS33R11 provides a CIR provisioning facility. The CIR can be used rest ricts the transport of received MAC data to a programmable rate. The CIR location is shown in the Figure 6-1 . The CIR will restrict the data flow from the Rece ...

  • Maxim DS33R11 - page 72

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 72 of 344 10 INTEGRATED T1/E1/J1 TRANSCEIVER 10.1 T1/E1/J1 Clocks Figure 10-1 shows the clock map of the T1/E1 transceiver. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuat ...

  • Maxim DS33R11 - page 73

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 73 of 344 Table 10-1. T1/E1/J1 Transmit Clock Source TCSS1 TCSS0 TRANSMIT CLOCK SOURCE 0 0 The TCLKT pin (C) is always the source of transmit clock. 0 1 Switch to the recovered clock (B ) when the signal at the TCLKT pin fails to transition after one channel time. 1 0 Use the scaled sign ...

  • Maxim DS33R11 - page 74

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 74 of 344 10.4 T1 Framer/Formatter Control and Status The T1 framer portion of the transceiver is configured through a set of nine control regist ers. Typically, the control registers are only accessed when the system is first pow ered up. Once the transceiver has been initialized, the c ...

  • Maxim DS33R11 - page 75

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 75 of 344 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (TR.T1RDMR1/2/3) to determine which of the 24 T1 c hannels of the T1 line going to the backplane should be overwritten ...

  • Maxim DS33R11 - page 76

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 76 of 344 10.5 E1 Framer/Formatter Control and Status The E1 framer portion of the transceiver is configured by a set of four control regist ers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control regi ...

  • Maxim DS33R11 - page 77

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 77 of 344 10.5.1 Automatic Alarm Generation The device can be programmed to automatically transmit AI S or remote alarm. When automatic AIS generation is enabled (TR.E1TCR2.1 = 1), the device monitors the rece ive-side framer to determine if any of the following conditions are present: l ...

  • Maxim DS33R11 - page 78

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 78 of 344 10.7 Error Counters The transceiver contains four c ounters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options incl ude one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Con ...

  • Maxim DS33R11 - page 79

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 79 of 344 10.7.2 Path Code Violation Count Register (TR.PCVCR) In T1 mode, the path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF fram ing mode, TR.PCVCR records errors in the CRC6 codewords. W ...

  • Maxim DS33R11 - page 80

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 80 of 344 10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) In T1 mode, TR.FOSCR is used to count the number of mult iframes that the receive sy nchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss- of-frame count (LOFC) and ESF er ...

  • Maxim DS33R11 - page 81

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 81 of 344 10.8 DS0 Monitoring Function The transceiver has the ability to monitor one DS0 64k bps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the trans mit direction, the user determines which channel is to be monitored by properly ...

  • Maxim DS33R11 - page 82

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 82 of 344 10.9 Signaling Operation There are two methods to access receive signaling dat a and provide transmit signaling data, processor-based (software-based) or hardware-based. Processor-based re fers to access through the transmit and receive signaling registers RS1–RS16 and TS1– ...

  • Maxim DS33R11 - page 83

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 83 of 344 10.9.2 Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSERO pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 robbed bit or E1 TS16 ...

  • Maxim DS33R11 - page 84

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 84 of 344 Figure 10-3. Simplified Diagram of Transmit Signaling Path TRANSM I T SIGNA LING RE GI ST ERS SIGNA LING BUF FER S PER-CH ANNEL CONTROL TSER TSI G T1/E1 DATA STREA M PER-CHA NNEL CONTROL TR .SSIE1 - TR.S SIE4 B7 TR.T1 TCR1. 4 1 0 0 1 0 1 TR.PCPR.3 ONLY A P PLIES T O T1 M ODE 10 ...

  • Maxim DS33R11 - page 85

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 85 of 344 10.9.3.2 E1 Mode In E1 mode, TS16 carries the signaling information. Th is information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. T he 32 time slots are referenced by two different channel number schemes in E1. In “Channel” ...

  • Maxim DS33R11 - page 86

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 86 of 344 10.10 Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are us ed by the device, the rema ining channels, CH25–CH32, are not use ...

  • Maxim DS33R11 - page 87

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 87 of 344 10.10.1 Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh . Write TR.IAAR = 02h ;select channel 3 in the array Write TR.PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, 5, and 6 idle code to 7Eh and enables transmission of ...

  • Maxim DS33R11 - page 88

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 88 of 344 10.11 Channel Blocking Registers The receive channel blocking registers (TR.RCBR1/T R.RCBR2/TR.RCBR3/TR.RCBR4 ) and the transmit channel blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR 3/TR.TCBR4) control RCHB LK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user- ...

  • Maxim DS33R11 - page 89

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 89 of 344 10.12.2 Transmit Elastic Store See the TR.IOCR1 and TR.IOCR2 registers for informati on about clock and I/O configurations. The operation of the transmit elastic store is very sim ilar to the receive side. If the transmit- side elastic store is enabled, a 1.544MHz or 2.048MHz c ...

  • Maxim DS33R11 - page 90

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 90 of 344 10.13 G.706 Intermediate CRC-4 Updating (E1 Mode Only) The device can implement the G.706 CRC- 4 recalculation at intermediate pat h points. When this mode is enabled, the data stream presented at TSERI already has t he FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksu ...

  • Maxim DS33R11 - page 91

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 91 of 344 10.14 T1 Bit-Oriented Code (BOC) Controller The transceiver contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 10.14.1 Transmit BOC Bits 0 to 5 in the TR.TFDL register contain the BO C message to ...

  • Maxim DS33R11 - page 92

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 92 of 344 10.15 Additional (Sa) and Internati onal (Si) Bit Operation (E1 Only) When operated in the E1 mode, the tran sceiver provides two methods for accessing the Sa and the Si bits. The first method involves using the internal TR.R AF/TR.RNAF and TR.TAF/TR.TNAF registers (Section 10. ...

  • Maxim DS33R11 - page 93

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 93 of 344 10.16 Additional HDLC Controllers in T1/E1/J1 Transceiver This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FD L (T1 mode). Each HDLC controller has 128-byte buffers in ...

  • Maxim DS33R11 - page 94

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 94 of 344 Table 10-12. HDLC Controller Registers REGISTER FUNCTION CONTROL AND CONFIGURATION TR.H1TC , HDLC #1 Transmit Control Register TR.H2TC , HDLC #2 Transmit Control Register General control over the transmit HDLC controllers TR.H1RC , HDLC #1 Receive Control Register TR.H2RC , HDL ...

  • Maxim DS33R11 - page 95

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 95 of 344 10.16.2 FIFO Control The FIFO control register (TR.HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When the transmit FIFO empties below the low waterm ...

  • Maxim DS33R11 - page 96

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 96 of 344 10.16.4 FIFO Information The transmit FIFO buffer-available register indicates the num ber of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffe ...

  • Maxim DS33R11 - page 97

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 97 of 344 10.17 Legacy FDL Support (T1 Mode) 10.17.1 Overview To provide backward compatibility to the older DS21x52 T1 device, the transceiver main tains the circuitry that existed in the previous generation of the T1 framer. In new applications, it is recommended that the HDLC controll ...

  • Maxim DS33R11 - page 98

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 98 of 344 10.17.3 Transmit Section The transmit section shifts out into the T1 data stream eit her the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TR.TFDL). When a new value is written to TR.TFDL, it is multiplexed seriall ...

  • Maxim DS33R11 - page 99

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 99 of 344 10.19 Programmable In-Band Loop Code Generation and Detection The transceiver has the ability to generate and detect a repeati ng bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user loads the patte ...

  • Maxim DS33R11 - page 100

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 100 of 344 10.20 Line Interface Unit (LIU) The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuat or. These three sections are controlled by the line interface control registers ( ...

  • Maxim DS33R11 - page 101

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 101 of 344 10.20.2.1 Receive Level Indicator and Threshold Interrupt The device reports the signal strengt h at RTIP and RRING in 2.5dB in crements through RL3–RL0 located in Information Register 2 (TR.INFO2). This feature is helpful when trouble-shooting line-performance problems. The ...

  • Maxim DS33R11 - page 102

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 102 of 344 10.20.3 Transmitter The transceiver uses a phase-lock loop along with a prec ision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. T he waveforms created by the dev ice meet the latest ETSI, ITU-T, ANSI, and AT&T speci ...

  • Maxim DS33R11 - page 103

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 103 of 344 10.21 MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz cl ock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1 . TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 interfaces. A prescale ...

  • Maxim DS33R11 - page 104

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 104 of 344 10.24 Recommended Circuits Figure 10-7. Basic Interface Refer to Application Note 324: T1/E1 Network Interface Design for more information on protected interfaces. TTIP TRING RTIP RRING DVDD TVDD RVDD VDD DVSS TVSS RVSS DS33R11 R R 2:1 1:1 C 0.1 μ F 0.1 μ F 0.1 μ F 0.01 μ ...

  • Maxim DS33R11 - page 105

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 105 of 344 Figure 10-8. E1 Transmit Pulse Template 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 TIME (ns) SCALED AMPLITUDE 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (IN 75 Ω SYSTEMS, 1.0 ON THE SCALE = 2.37VPEAK IN 120 Ω SYSTEMS, 1.0 ON THE SCALE = ...

  • Maxim DS33R11 - page 106

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 106 of 344 Figure 10-10. Jitter Tolerance FREQUENCY (Hz) UNIT INTERVALS (UI P-P ) 1k 100 10 1 0.1 10 100 1k 10k 100k DEVICE TOLERANCE 1 TR 62411 (DEC. 90) ITU-T G. 823 Figure 10-11. Jitter Tolerance (E1 Mode) FREQUENCY (Hz) UNIT INTERVALS (UI P-P ) 1k 100 10 1 0.1 10 100 1k 10k 100k DEVI ...

  • Maxim DS33R11 - page 107

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 107 of 344 Figure 10-12. Jitter Attenuation (T1 Mode) FREQUE NCY (Hz) 0dB -20dB -40dB -60dB 1 10 100 1K 10K JITTER ATT ENUATION (dB) 100K TR 62 41 1 (De c . 9 0) Pr ohibit ed A rea C u r v e B Curve A T1 MOD E Figure 10-13. Jitter Attenuation (E1 Mode) FREQUENCY (Hz) 0 -20 -40 -60 1 10 1 ...

  • Maxim DS33R11 - page 108

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 108 of 344 Figure 10-14. Optional Crystal Connections XTALD C1 C2 1.544MHz/2.048MHz MCLK NOTE: C1 AND C2 SHOULD BE 5pF LOWER THAN TWO TIMES THE NOMINAL LOADING CAPACITANCE OF THE CRYSTAL TO ADJUST FOR THE INPUT CAPACITANCE OF THE DEVICE. 10.25 T1/E1/J1 TRANSCEIVER BERT FUNCTION The BERT ...

  • Maxim DS33R11 - page 109

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 109 of 344 Figure 10-15. Simplified Diagram of BERT in Network Direction PER-CHANNEL AND F-BIT (T1 MODE) MAPPING BERT TRANSMITTER BERT RECEIVER 1 0 FROM RECEIVE FRAMER TO RECEIVE SYSTEM BACKPLANE INTERFACE FROM TRANSMIT SYSTEM BACKPLANE INTERFACE TO TRANSMIT FRAMER Figure 10-16. Simplifi ...

  • Maxim DS33R11 - page 110

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 110 of 344 10.25.3 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32 bits, the pattern s ...

  • Maxim DS33R11 - page 111

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 111 of 344 10.26 Payload Error-Insertion Function (T1 Mode Only ) An error-insertion function is available in the transceiver and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only ava ilable in T1 mode. Errors c an be inserted ove ...

  • Maxim DS33R11 - page 112

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 112 of 344 10.27 Programmable Backplane Clock Synthesizer The transceiver contains an on-chip clock synthesizer t hat generates a user-selectabl e clock output on the BPCLK pin, referenced to the recovered receive clock (RCLKO ). The synthesizer uses a phase-locked loop to generate low-j ...

  • Maxim DS33R11 - page 113

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 113 of 344 10.29 T1/E1/J1 Transmit Flow Diagrams Figure 10-17. T1/J1 Transmit Flow Diagram ESCR. 4 TESE TSER TSIG HSIE1-3 through PCPR TX ESTORE Off-Chip Connecti on RDATA From T1_rcv_l ogic LBCR1.1 PLB HDLC Engine #1 THMS1 H1TC.4 H1TCS1-3 H1TTSBS HDLC Engine #2 THMS2 H2 TC.4 H2TCS1-3 H2 ...

  • Maxim DS33R11 - page 114

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 114 of 344 B8ZS Encoding Bipolar/ NRZ coding T1TCR2.7 B8ZSE IOCR1.0 ODF 1/2 CLK/ FULL CLK CCR1.4 ODM TPOS TNEG FDL Mux ESF Yellow From BOC Mux From F-bit Mux From ESF Yellow Alarm TFPT T1TCR1.5 TFM T1CCR1.2 TYEL T1TCR1.0 CRC Mux TCPT T1TCR1.5 D4 bit 2 Yellow Alm BERT Engine BERT Mux F-bi ...

  • Maxim DS33R11 - page 115

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 115 of 344 Figure 10-18. E1 Transmit Flow Diagram TSER TSIG HSIE1-4 through PCPR TX ESTO RE ESCR.4 TESE TESO TDATA Off-Chip Connect ion RDATA From E1_rcv _logic LBCR1.1 PLB HDLC Engine #1 THMS1 H1TC.4 H1TCS1-4 H1TTSBS T1SaBE4- T1SaBE8 THMS1 H1TC.4 H1TTSBS.4 - H1TT SBS.0 HDLC Engi ne #2 T ...

  • Maxim DS33R11 - page 116

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 116 of 344 Per-Channel Loopback From Idle Code Mux RDATA From E1_rcv_logic PCLR1-4 Sa-bit Mux TNAF THMS1 THMS2 H1TC.4 H2TC.4 TS0 Mux TAF/TNAF(non Sa) Si-bit Mux E1TCR1.4 TSIS Auto E- bit Gen TLINK Mux TLINK Auto RA Gen TSaCR M ...

  • Maxim DS33R11 - page 117

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 117 of 344 11 DEVICE REGISTERS Ten address lines are used to address the register space. Table 11-1 shows the register map for the DS33R11. The addressable range for the device is 0000h to 08FFh. Each Register Section is 64 bytes deep. Global Registers are preserved for software compatib ...

  • Maxim DS33R11 - page 118

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 118 of 344 11.1 Register Bit Maps Table 11-2 , Table 11-3 , Table 11-4 , Table 11-5 , Table 11-6 , and Table 11-7 contain the regist ers of the DS33R11. Bits that are reserved are noted with a single dash “-“. A ll registers not listed are reserved and should be initialized with a va ...

  • Maxim DS33R11 - page 119

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 119 of 344 11.1.2 Arbiter Register Bit Map Table 11-3. Arbiter Register Bit Map A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 40h AR . R QS C 1 RQSC7 RQSC6 RQSC5 RQSC4 RQSC3 RQSC2 RQSC1 RQSC0 41h AR . T QS C 1 TQSC7 TQSC6 TQSC5 TQSC4 TQSC3 TQSC2 TQSC1 TQSC0 11.1.3 ...

  • Maxim DS33R11 - page 120

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 120 of 344 11.1.4 Serial Interface Register Bit Map Table 11-5. Serial Interface Register Bit Map A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0C0h LI.TSLCR - - - - - - - TDENPLT 0C1h LI.RSTPD - - - - - - RESET - 0C2h LI.LPBK - - - - - - - QLP 0C3h Reserved - - - ...

  • Maxim DS33R11 - page 121

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 121 of 344 A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 114h LI.RSPCB0 RSPC7 RSPC6 RSPC5 RSPC4 RSPC3 RSPC2 RSPC1 RSPC0 115h LI.RSPCB1 RSPC15 RSPC14 RSPC13 RSPC12 RSPC11 RSPC10 RSPC9 RSPC8 116h LI.RSPCB2 RSPC23 RSPC22 RSPC21 RSPC20 RSPC19 RSPC18 RSPC17 RSPC16 118h ...

  • Maxim DS33R11 - page 122

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 122 of 344 11.1.5 Ethernet Interface Register Bit Map Table 11-6. Ethernet Interface Register Bit Map A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 140h SU.MACRA DL MACRA7 MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRA0 141h SU.MACRA DH MACRA15 MACRA14 MACRA13 MAC ...

  • Maxim DS33R11 - page 123

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 123 of 344 11.1.6 MAC Register Bit Map Table 11-7. MAC Indir ect Register Bit Map A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0000h SU.MA CCR 31:24 Reserved Reserved Reserved HDB PS Reserved Reserved Reserved 0001h 23:16 DRO OML1 OML0 F PM PAM Reserved Reserved 0 ...

  • Maxim DS33R11 - page 124

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 124 of 344 A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 112h RESERVED – initialize to FF Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 113h RESERVED – initialize to FF Reserved Reserved Reserved Reserved Reserved Reserved Reserved Res ...

  • Maxim DS33R11 - page 125

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 125 of 344 Table 11-8. T1/E1/J1 Transceiver Re gister Bit Map (Active when CST = 0) A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 000 h TR.MSTRREG — — — — TEST1 TEST0 T1/E1 SFTRST 001 h TR.IOCR1 RSMS RSMS2 RSMS1 RSIO TSDW TSM TSIO ODF 002 h TR.IOCR2 RDCLKI ...

  • Maxim DS33R11 - page 126

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 126 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 h 01A h TR.SR3 LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA 01B h TR.IMR3 LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA 01C h TR.SR4 RAIS-CI RSA1 RSA0 TMF TAF RMF RCMF RAF 01D h TR.IMR4 RAIS-CI RSA1 RSA0 TMF TAF RMF ...

  • Maxim DS33R11 - page 127

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 127 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 h 035 h TR.E1TCR1 TFPT T16S TUA1 TSi S TSA1 THDB3 TG802 TCRC4 036 h TR.E1TCR2 Reserved Reserved Reserved Reserved Reserved AEBE AAIS ARA 037 h TR.BOCC — — — RBOCE RBR RBF1 RBF0 SBOC 038 h TR.RSINFO1 CH ...

  • Maxim DS33R11 - page 128

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 128 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 h 050 h TR.TS1 Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition. 051 h TR.TS2 Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition. 052 h TR.TS ...

  • Maxim DS33R11 - page 129

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 129 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 06A h TR.RS11 Receive Signaling Bit Format Changes With Op erating Mode. See Register Definition. 06B h TR.RS12 Receive Signaling Bit Format Changes With Op erating Mode. See Register Definition. 06C h TR.RS ...

  • Maxim DS33R11 - page 130

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 130 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 085 h TR.RCICE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 086 h TR.RCICE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 087 h TR.RCICE4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 088 h TR.RCBR1 CH8 CH7 CH6 CH5 CH4 CH3 C ...

  • Maxim DS33R11 - page 131

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 131 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0A0 h TR.H2TC NOFS TEOML THR THMS TFS TEOM TZSD TCRCD 0A1 h TR.H2FC — — TFLWM2 TFLWM1 TFLWM0 RFHWM2 RFHWM1 RFHWM0 0A2 h TR.H2RCS1 RHCS8 RHCS7 RHCS6 RHCS5 RHCS4 RHCS3 RHCS2 RHCS1 0A3 h TR.H2RCS2 RHCS16 RH ...

  • Maxim DS33R11 - page 132

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 132 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0C1 h TR.TFDL TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0 0C2 h TR.RFDLM1 RFDLM7 RFDLM6 RFDLM5 RFDLM4 RFDLM3 RFDLM2 RFDLM1 RFDLM0 0C3 h TR.RFDLM2 RFDLM7 RFDLM6 RFDLM5 RFDLM4 RFDLM3 RFDLM2 RFDLM1 RFDLM0 0 ...

  • Maxim DS33R11 - page 133

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 133 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0DC h TR.BRP1 RPAT7 RPAT6 RPAT5 RPAT4 RPAT3 RPAT2 RPAT1 RPAT0 0DD h TR.BRP2 RPAT15 RPAT14 RPAT13 RPAT12 RPAT11 RPAT10 RPAT9 RPAT8 0DE h TR.BRP3 RPAT23 RPAT22 RPAT21 RPAT20 RPAT19 RPAT18 RPAT17 RPAT16 0DF h T ...

  • Maxim DS33R11 - page 134

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 134 of 344 11.2 Global Register Definitions for Ethernet Mapper Functions contained in the global registers include: fram er reset, LIU reset, device ID, and BERT interrupt status. These registers are preserved to provide code compatibility with the multiport devices in this product fami ...

  • Maxim DS33R11 - page 135

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 135 of 344 Register Name: GL.CR1 Register Description: Global Control Register 1 Register Address: 02h Bit # 7 6 5 4 3 2 1 0 Name - - - - - REF_CLKO INTM RST Default 0 0 0 Bit 2: REF_CLKO OFF (REF_CLKO) This bit determines if the REF_CLKO is turned off 1 = REF_CLKO is disabled and output ...

  • Maxim DS33R11 - page 136

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 136 of 344 Register Name: GL.RTCAL Register Description: Global Receive and Transmit Serial Port Clock Activity Latched Status Register Address: 04h Bit # 7 6 5 4 3 2 1 0 Name - - - RLCALS1 - - - TLCALS1 Default - - - - - - - - Bit 4: Receive Serial Interface Clock Activi ty Latched Stat ...

  • Maxim DS33R11 - page 137

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 137 of 344 Register Name: GL.LIS Register Description: Global Serial Interface Interrupt Status Register Address: 07h Bit # 7 6 5 4 3 2 1 0 Name - - - LIN1TIS - - - LIN1RIS Default 0 0 0 0 0 0 0 0 Bit 4: Serial Interface 1 TX Interrupt Status (LINE1TIS) This bit is set if Serial Interfac ...

  • Maxim DS33R11 - page 138

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 138 of 344 Register Name: GL.TRQIE Register Description: Global Transmit Receive Queue Interrupt Enable Register Address: 0Ah Bit # 7 6 5 4 3 2 1 0 Name - - - TQ1IE - - - RQ1IE Default 0 0 0 0 0 0 0 0 Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE) Setting this bit to 1 enables an inter ...

  • Maxim DS33R11 - page 139

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 139 of 344 Register Name: GL.BIS Register Description: Global BERT Interrupt Status Register Address: 0Dh Bit # 7 6 5 4 3 2 1 0 Name - - - - - - - BIS Default 0 0 0 0 0 0 0 0 Bit 0: BERT Interrupt Status (BIS) This bit is set to 1 if the BERT has an enabled interrupt generating event. Re ...

  • Maxim DS33R11 - page 140

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 140 of 344 Register Name: GL.C1QPR Register Description: Connection 1 Queue Pointer Reset Register Address: 12h Bit # 7 6 5 4 3 2 1 0 Name - - - - C1MRPR C1HWPR C1MHPR C1HRPR Default 0 0 0 0 0 0 0 0 Bit 3: MAC Read Pointer Reset (C1MRPR) Setting this bit to 1 resets the receive queue rea ...

  • Maxim DS33R11 - page 141

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 141 of 344 Register Name: GL.BISTPF Register Description: BIST Pass-Fail Register Address: 21h Bit # 7 6 5 4 3 2 1 0 Name - - - - - - BISTDN BISTPF Default 0 0 0 0 0 0 0 0 Bit 1: BIST DONE (BISTDN) If this bit is set to 1, the DS33R11 has comp leted the BIST Test initiated by BISTE. The ...

  • Maxim DS33R11 - page 142

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 142 of 344 Register Name: GL.SDMODE2 Register Description: Global SDRAM Mode Register 2 Register Address: 3Bh Bit # 7 6 5 4 3 2 1 0 Name - - - - - LTMOD2 LTMOD1 LTMOD0 Default 0 0 0 0 0 0 1 0 Bits 0 - 2: CAS Latency Mode (LTMOD0 - LTMOD2) These bits are used to setup CAS Latency Note: On ...

  • Maxim DS33R11 - page 143

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 143 of 344 11.3 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing and dequeuing data to an external SDRAM. The arbiter handl es requests from the HDLC and MAC to transfer data to/from the SDRAM. The base ...

  • Maxim DS33R11 - page 144

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 144 of 344 11.4 BERT Registers Register Name: BCR Register Description: BERT Control Register Register Address: 80h Bit # 7 6 5 4 3 2 1 0 Name - PMU RNPL RPIC MPR APRD TNPL TPIC Default 0 0 0 0 0 0 0 0 Bit 7: This bit must be kept low for proper operation. Bit 6: Performance Monitoring U ...

  • Maxim DS33R11 - page 145

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 145 of 344 Register Name: BPCLR Register Description: BERT Pattern Configuration Low Register Register Address: 82h Bit # 7 6 5 4 3 2 1 0 Name - QRSS PTS PLF4 PLF3 PLF2 PLF1 PLF0 Default 0 0 0 0 0 0 0 0 Bit 6: QRSS Enable (QRSS) When 0, the pattern generator configurat ion is controlled ...

  • Maxim DS33R11 - page 146

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 146 of 344 Register Name: BSPB0R Register Description: BERT Pattern By te0 Register Register Address: 84h Bit # 7 6 5 4 3 2 1 0 Name BSP7 BSP6 BSP5 BSP4 BSP3 BSP2 BSP1 BSP0 Default 0 0 0 0 0 0 0 0 Bits 0 to 7: BERT Pattern (BSP[7:0]) Lower eight bits of 32 bits. Regist er description fol ...

  • Maxim DS33R11 - page 147

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 147 of 344 Register Name: TEICR Register Description: Transmit Error Insertion Control Register Register Address: 88h Bit # 7 6 5 4 3 2 1 0 Name - - TIER2 TIER1 TIER0 BEI TSEI - Default 0 0 0 0 0 0 0 0 Bits 3 to 5: Transmit Error Insertion Rate (TEIR[2:0]) These three bits indicate the r ...

  • Maxim DS33R11 - page 148

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 148 of 344 Register Name: BSRL Register Description: BERT Status Register Latched Register Address: 8Eh Bit # 7 6 5 4 3 2 1 0 Name - - - - PMSL BEL BECL OOSL Default - - - - - - - - Bit 3: Performance Monitor Update Status Latched (PMSL) This bit is set when the PMS bit transitions from ...

  • Maxim DS33R11 - page 149

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 149 of 344 Register Name: RBECB0R Register Description: Receive Bit Error Count By te 0 Register Register Address: 94h Bit # 7 6 5 4 3 2 1 0 Name BEC7 BEC6 BEC5 BEC4 BEC3 BEC2 BEC1 BEC0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Bit Error Count (BEC[0:7]) Lower eight bits of 24 bits. Register d ...

  • Maxim DS33R11 - page 150

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 150 of 344 Register Name: RBCB1 Register Description: Receive Bit Count By te 1 Register #1 Register Address: 99h Bit # 7 6 5 4 3 2 1 0 Name BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Bit Count (BC[8:15]) Eight bits of a 32 bit value. Register description b ...

  • Maxim DS33R11 - page 151

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 151 of 344 11.5 Serial Interface Registers The Serial Interface contains the Serial HDLC transport ci rcuitry and the associated serial port. The Serial Interface register map consists of registers that are comm on functions, transmit functi ons, and receive functions. Bits that are unde ...

  • Maxim DS33R11 - page 152

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 152 of 344 Register Name: LI.LPBK Register Description: Serial Interface Loopback Control Register Register Address: 0C2h Bit # 7 6 5 4 3 2 1 0 Name - - - - - - - QLP Default 0 0 0 0 0 0 0 0 Bit 0: Queue Loopback Enable (QLP) If this bit set to 1, data received on the Serial Interface is ...

  • Maxim DS33R11 - page 153

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 153 of 344 Register Name: LI.TIFGC Register Description: Transmit Inter-Frame Gapping Control Register Register Address: 0C5h Bit # 7 6 5 4 3 2 1 0 Name TIFG7 TIFG6 TIFG5 TIFG4 TIFG3 TIFG2 TIFG1 TIFG0 Default 0 0 0 0 0 0 0 1 Bits 0 - 7: Transmit Inter-Frame Gapping (TIFG[7:0]) – These ...

  • Maxim DS33R11 - page 154

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 154 of 344 Register Name: LI.TEPHC Register Description: Transmit Errored Packet High Control Register Register Address: 0C7h Bit # 7 6 5 4 3 2 1 0 Name MEIMS TPER6 TPER5 TPER 4 TPER3 TPER2 TPER1 TPER0 Default 0 0 0 0 0 0 0 0 Bit 7: Manual Error Insert Mode Select (MEIMS) – When 0, the ...

  • Maxim DS33R11 - page 155

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 155 of 344 Register Name: LI.TPPSR Register Description: Transmit Packet Processor Status Register Register Address: 0C8h Bit # 7 6 5 4 3 2 1 0 Name - - - - - - - TEPF Default 0 0 0 0 0 0 0 0 Bit 0: Transmit Errored Packet Insertion Finished (TEPF) – This bit is set when the number of ...

  • Maxim DS33R11 - page 156

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 156 of 344 Register Name: LI.TPCR0 Register Description: Transmit Packet Count By te 0 Register Address: 0CCh Bit # 7 6 5 4 3 2 1 0 Name TPC7 TPC6 TPC5 TPC4 TPC3 TPC2 TPC1 TPC0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Transmit Packet Count (TPC[7:0]) – Eight bits of 24 bit value. Register ...

  • Maxim DS33R11 - page 157

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 157 of 344 Register Name: LI.TBCR0 Register Description: Transmit By te Count Byte 0 Register Address: 0D0h Bit # 7 6 5 4 3 2 1 0 Name TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Transmit Byte Count (TBC[0:7]) – Eight bits of 32 bit value. Register des ...

  • Maxim DS33R11 - page 158

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 158 of 344 Register Name: LI.THPMUU Register Description: Serial Interface Transmit HDLC PMU Update Register Register Address: 0D6h Bit # 7 6 5 4 3 2 1 0 Name - - - - - - - TPMUU Default 0 0 0 0 0 0 0 0 Bit 0: Transmit PMU Update (TPMUU) This signal causes the transmit cell/packet proces ...

  • Maxim DS33R11 - page 159

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 159 of 344 11.5.2 X.86 Registers X.86 transmit and common registers are used to c ontrol the operation of the X.86 encoder and decoder. Register Name: LI.TX86EDE Register Description: X.86 Encoding Decoding Enable Register Address: 0D8h Bit # 7 6 5 4 3 2 1 0 Name - - - - - - - X86ED Defa ...

  • Maxim DS33R11 - page 160

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 160 of 344 Register Name: LI.TRX86SAPIL Register Description: Transmit Receive X.86 SAPIL Register Address: 0DCh Bit # 7 6 5 4 3 2 1 0 Name TRSAPIL7 TRSAPIL6 TRSAPIL5 TRSAPIL4 TRSAPIL3 TRSAPIL2 TRSAPIL1 TRSAPIL0 Default 0 0 0 0 0 0 0 1 Bits 0 – 7: X86 Transmit Receive Control (TRSAPIL0 ...

  • Maxim DS33R11 - page 161

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 161 of 344 11.5.3 Receive Serial Interface Serial Receive Registers are used to control the HDLC Rece iver associated with each Seri al Interface. Note that throughout this document HDLC Processor is also refe rred to as “Packet Processor”. The receive packet processor block has seve ...

  • Maxim DS33R11 - page 162

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 162 of 344 Register Name: LI.RMPSCL Register Description: Receive Maximum Packet Size Control Low Register Register Address: 102h Bit # 7 6 5 4 3 2 1 0 Name RMX7 RMX6 RMX5 RMX4 RMX3 RMX2 RMX1 RMX0 Default 1 1 1 0 0 0 0 0 Bits 0 - 7: Receive Maximum Packet Size (RMX[7:0]) Eight bits of a ...

  • Maxim DS33R11 - page 163

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 163 of 344 Register Name: LI.RPPSRL Register Description: Receive Packet Processor Status Register Latched Register Address: 105h Bit # 7 6 5 4 3 2 1 0 Name REPL RAPL RIPDL RSPDL RLPDL REPCL RAPCL RSPCL Default - - - - - - - - Bit 7: Receive FCS Errored Packet Latched (REPL) This bit is ...

  • Maxim DS33R11 - page 164

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 164 of 344 Register Name: LI.RPPSRIE Register Description: Receive Packet Processor Status Register Interrupt Enable Register Address: 106h Bit # 7 6 5 4 3 2 1 0 Name REPIE RAPIE RIPDIE RSPDIE RLPDIE REPCIE RAPCIE RSPCIE Default 0 0 0 0 0 0 0 0 Bit 7: Receive FCS Errored Packet Interrupt ...

  • Maxim DS33R11 - page 165

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 165 of 344 Register Name: LI.RPCB0 Register Description: Receive Packet Count By te 0 Register Register Address: 108h Bit # 7 6 5 4 3 2 1 0 Name RPC7 RPC6 RPC5 RPC4 RPC3 RPC2 RPC1 RPC0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Receive Packet Count (RPC [7:0]) Eight bits of a 24-bit value. Regi ...

  • Maxim DS33R11 - page 166

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 166 of 344 Register Name: LI.RFPCB0 Register Description: Receive FCS Errored Packet Count By te 0 Register Register Address: 10Ch Bit # 7 6 5 4 3 2 1 0 Name RFPC7 RFPC6 RFPC5 RFPC4 RFPC3 RFPC2 RFPC1 RFPC0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Receive FCS Errored Packet Count (RFPC[7:0]) ...

  • Maxim DS33R11 - page 167

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 167 of 344 Register Name: LI.RAPCB0 Register Description: Receive Aborted Packet Count By te 0 Register Register Address: 110h Bit # 7 6 5 4 3 2 1 0 Name RAPC7 RAPC6 RAPC5 RAPC4 RAPC3 RAPC2 RAPC1 RAPC0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Receive Aborted Packet Count (RAPC [7:0]) Eight bi ...

  • Maxim DS33R11 - page 168

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 168 of 344 Register Name: LI.RSPCB0 Register Description: Receive Size Violation Packet Count By te 0 Register Register Address: 114h Bit # 7 6 5 4 3 2 1 0 Name RSPC7 RSPC6 RSPC5 RSPC4 RSPC3 RSPC2 RSPC1 RSPC0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Receive Size Viol ation Packet Count (RSPC ...

  • Maxim DS33R11 - page 169

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 169 of 344 Register Name: LI.RBC0 Register Description: Receive Byte Count 0 Register Register Address: 118h Bit # 7 6 5 4 3 2 1 0 Name RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Receive By te Count (RBC [7:0]) Eight bits of a 32-bit value. Register descr ...

  • Maxim DS33R11 - page 170

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 170 of 344 Register Name: LI.RAC0 Register Description: Receive Aborted Byte Count 0 Register Register Address: 11Ch Bit # 7 6 5 4 3 2 1 0 Name REBC7 REBC6 REBC5 REBC4 REBC3 REBC2 REBC1 REBC0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Receive Aborted By te Count (RBC [7:0]) Eight bits of a 32-b ...

  • Maxim DS33R11 - page 171

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 171 of 344 Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDLC PMU Update Register Register Address: 120h Bit # 7 6 5 4 3 2 1 0 Name - - - - - - - RPMUU Default 0 0 0 0 0 0 0 0 Bit 0: Receive PMU Update (RPMUU) This signal causes the receive cell/packet processor ...

  • Maxim DS33R11 - page 172

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 172 of 344 Register Name: LI.RX86LSIE Register Description: Receive X.86 Interrupt Enable Register Address: 123h Bit # 7 6 5 4 3 2 1 0 Name - - - - SAPINE01IM SAPINEFEIM CNE3LI M ANE4IM Default 0 0 0 0 0 0 0 0 Bit 3: SAPI Octet not equal to LI.TRX86SAPIH Interrupt Enable (SAPINE01IM) If ...

  • Maxim DS33R11 - page 173

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 173 of 344 Register Name: LI.TQTIE Register Description: Serial Interface Transmit Queue Cross Threshold Interrupt Enable Register Address: 126h Bit # 7 6 5 4 3 2 1 0 Name - - - - TFOVFIE TQOVFIE TQHTIE TQLTIE Default 0 0 0 0 0 0 0 0 Bit 3: Transmit FIFO Overflow for Connection Interrupt ...

  • Maxim DS33R11 - page 174

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 174 of 344 11.6 Ethernet Interface Registers The Ethernet Interface registers are used to configur e RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addr essed directly from the Processor port. The registers below are used to p ...

  • Maxim DS33R11 - page 175

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 175 of 344 Register Name: SU.MACRD1 Register Description: MAC Read Data By te 1 Register Address: 143h Bit # 7 6 5 4 3 2 1 0 Name MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 MACRD9 MACRD8 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: MAC Read Data 1 (MACRD8-15) One of four bytes of data read f ...

  • Maxim DS33R11 - page 176

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 176 of 344 Register Name: SU.MACWD1 Register Description: MAC Write Data 1 Register Address: 147h Bit # 7 6 5 4 3 2 1 0 Name MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWD09 MACWD08 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: MAC Write Data 1 (MACWD8-15) One of four bytes of data to be ...

  • Maxim DS33R11 - page 177

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 177 of 344 Register Name: SU.MACAWH Register Description: MAC Address Write High Register Address: 14Bh Bit # 7 6 5 4 3 2 1 0 Name M A C A W 1 5 M A C A W 1 4 M A C A W 1 3 MACAW12 MACAW11 MACAW10 MACAW9 MACAW8 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: MAC Write Address (MACAW8-15) High byte ...

  • Maxim DS33R11 - page 178

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 178 of 344 Register Name: SU.LPBK Register Description: Ethernet Interface Loopback Control Register Register Address: 14Fh Bit # 7 6 5 4 3 2 1 0 Name - - - - - - - QLP Default 0 0 0 0 0 0 0 0 Bit 0: Queue Loopback Enable (QLP) If this bit is set to 1, data from the Ethernet Interface re ...

  • Maxim DS33R11 - page 179

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 179 of 344 Register Name: SU.TFRC Register Description: Transmit Frame Resend Control Register Address: 151h Bit # 7 6 5 4 3 2 1 0 Name - - - - NCFQ TP DFCB TPRHBC TPRCB Default 0 0 0 0 0 0 0 0 Bit 3: No Carrier Queue Flush Bar (NCFQ) If this bit is set to 1, the queue for data passing f ...

  • Maxim DS33R11 - page 180

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 180 of 344 Register Name: SU.TFSL Register Description: Transmit Frame Status Low Register Address: 152h Bit # 7 6 5 4 3 2 1 0 Name UR EC LC ED LOC NOC - FABORT Default 0 0 0 0 0 0 0 0 Bit 7: Under Run (UR) When this bit is set to 1, the frame was aborted due to a data under run conditio ...

  • Maxim DS33R11 - page 181

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 181 of 344 Register Name: SU.RFSB0 Register Description: Receive Frame Status By te 0 Register Address: 154h Bit # 7 6 5 4 3 2 1 0 Name FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Frame Length (FL[0:7]) These 8 bits are the low byte of the l ength (in bytes) of th ...

  • Maxim DS33R11 - page 182

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 182 of 344 Register Name: SU.RFSB3 Register Description: Receive Frame Status By te 3 Register Address: 157h Bit # 7 6 5 4 3 2 1 0 Name MF - - BF MCF UF CF LE Default 0 0 0 0 0 0 0 0 Bit 7: Missed Frame (MF) This bit is set to 1 if the packet is not su ccessfully received from the MAC by ...

  • Maxim DS33R11 - page 183

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 183 of 344 Register Name: SU.RMFSRL Register Description: Receiver Maximum Frame Low Register Register Address: 158h Bit # 7 6 5 4 3 2 1 0 Name RMPS7 RMPS6 RMPS5 RMPS4 RMPS3 RMPS2 RMPS1 RMPS0 Default 1 1 1 0 0 0 0 0 Bits 7- 0: Receiver Maximum Frame (RMPS[0:7]) Eight bits of sixteen bit ...

  • Maxim DS33R11 - page 184

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 184 of 344 Register Name: SU.QRIE Register Description: Receive Queue Cross Threshold enable Register Address: 15Ch Bit # 7 6 5 4 3 2 1 0 Name - - - - RFOVFIE RQVFIE RQLTIE RQHTIE Default 0 0 0 0 0 0 0 0 Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE) If this bit is set, the inte ...

  • Maxim DS33R11 - page 185

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 185 of 344 Register Name: SU.RFRC Register Description: Receive Frame Rejection Control Register Address: 15Eh Bit # 7 6 5 4 3 2 1 0 Name - UCFR CFRR LERR CRCERR DBR MIIER BFR Default 0 0 0 0 0 0 0 0 Bit 6: Uncontrolled Control Frame Reject (UCFR) When set to 1, Control Frames other than ...

  • Maxim DS33R11 - page 186

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 186 of 344 11.6.2 MAC Registers The control Registers related to the control of the individual Mac’s are s hown in the following Table. The DS33R11 keeps statistics for the packet traffic sent and received. The register address map is shown in the following Table. Note that the address ...

  • Maxim DS33R11 - page 187

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 187 of 344 Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retr ansmission of late collisions is disabled. Bit 10: Disable Retry (DRTY) When set to 1, the MAC makes only a single atte ...

  • Maxim DS33R11 - page 188

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 188 of 344 Register Name: SU.MACMIIA Register Description: MAC MII Management (MDIO) Address Register Register Address: 0014h (indirect) 0014h: Bit # 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserv ed Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0015h: Bit # ...

  • Maxim DS33R11 - page 189

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 189 of 344 Register Name: SU.MACMIID Register Description: MAC MII (MDIO) Data Register Register Address: 0018h (indirect) 0018h: Bit # 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserv ed Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0019h: Bit # 23 22 21 20 1 ...

  • Maxim DS33R11 - page 190

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 190 of 344 Register Name: SU.MACFCR Register Description: MAC Flow Control Register Register Address: 001Ch (indirect) 001Ch: Bit # 31 30 29 28 27 26 25 24 Name PT15 PT14 PT13 PT12 PT11 PT10 PT09 PT08 Default 0 0 0 0 0 0 0 0 001Dh: Bit # 23 22 21 20 19 18 17 16 Name PT07 PT06 PT05 PT04 P ...

  • Maxim DS33R11 - page 191

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 191 of 344 Register Name: SU.MMCCTRL Register Description: MAC MMC Control Register Register Address: 0100h (indirect) 0100h: Bit # 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserv ed Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0101h: Bit # 23 22 21 20 19 18 ...

  • Maxim DS33R11 - page 192

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 192 of 344 Register Name: Reserved Register Description: MAC Reserved Control Register Register Address: 010Ch (indirect) 010Ch: Bit # 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserv ed Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 010Dh: Bit # 23 22 21 20 19 ...

  • Maxim DS33R11 - page 193

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 193 of 344 Register Name: Reserved Register Description: MAC Reserved Control Register Register Address: 0110h (indirect) 0110h: Bit # 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserv ed Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0111h: Bit # 23 22 21 20 19 ...

  • Maxim DS33R11 - page 194

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 194 of 344 Register Name: SU.RxFrmCtr Register Description: MAC All Frames Received Counter Register Address: 0200h (indirect) 0200h: Bit # 31 30 29 28 27 26 25 24 Name RXFRMC31 RXF RMC30 RXFRMC29 RXFRMC28 RX FRMC27 RXFRMC26 RXFRMC25 RXFRMC24 Default 0 0 0 0 0 0 0 0 0201h: Bit # 23 22 21 ...

  • Maxim DS33R11 - page 195

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 195 of 344 Register Name: SU.RxFrmOkCtr Register Description: MAC Frames Received OK Counter Register Address: 0204h (indirect) 0204h: Bit # 31 30 29 28 27 26 25 24 Name RXFRMOK31 RXFRMOK30 RXFRMOK29 RXFRMOK28 RXFRMOK27 RXFRMOK26 RXFRMOK25 RXFRMOK24 Default 0 0 0 0 0 0 0 0 0205h: Bit # 2 ...

  • Maxim DS33R11 - page 196

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 196 of 344 Register Name: SU.TxFrmCtr Register Description: MAC All Frames Transmitted Counter Register Address: 0300h (indirect) 0300h: Bit # 31 30 29 28 27 26 25 24 Name TXFRMC31 TXFRMC30 TXFRMC29 TXFRMC28 T XFRMC27 TXFRMC26 TXFRMC25 TXFRMC24 Default 0 0 0 0 0 0 0 0 0301h: Bit # 23 22 ...

  • Maxim DS33R11 - page 197

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 197 of 344 Register Name: SU.TxBytesCtr Register Description: MAC All By tes Transmitted Counter Register Address: 0308h (indirect) 0308h: Bit # 31 30 29 28 27 26 25 24 Name TXBYTEC31 TXBYT EC30 TXBYTEC29 TXBYTEC28 T XBYTEC27 TXBYTEC26 T XBYTEC25 TXBYTEC24 Default 0 0 0 0 0 0 0 0 0309h: ...

  • Maxim DS33R11 - page 198

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 198 of 344 Register Name: SU.TxBytesOkCtr Register Description: MAC By tes Transmitted OK Counter Register Address: 030Ch (indirect) 030Ch: Bit # 31 30 29 28 27 26 25 24 Name TXBYTEOK31 TXBY TEOK30 TXBYTEOK29 TXBYTEOK28 TXBYTEOK27 TXBY TEOK26 TXBYTEOK25 TXBYTEOK24 Default 0 0 0 0 0 0 0 0 ...

  • Maxim DS33R11 - page 199

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 199 of 344 Register Name: SU.TxFrmUndr Register Description: MAC Transmit Frame Under Run Counter Register Address: 0334h (indirect) 0334h: Bit # 31 30 29 28 27 26 25 24 Name TXFRMU31 TXFRMU30 TXFRMU29 TXFRMU28 T XFRMU27 T XFRMU26 TXFRMU25 TXFRMU24 Default 0 0 0 0 0 0 0 0 0335h: Bit # 23 ...

  • Maxim DS33R11 - page 200

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 200 of 344 Register Name: SU.TxBdFrmCtr Register Description: MAC All Frames Aborted Counter Register Address: 0338h (indirect) 0338h: Bit # 31 30 29 28 27 26 25 24 Name TXFRMBD31 TXFRMBD30 TXFRMBD29 TXFRMBD28 T XFRMBD27 TXFRMBD26 TXFRMBD25 TXFRMBD24 Default 0 0 0 0 0 0 0 0 0339h: Bit # ...

  • Maxim DS33R11 - page 201

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 201 of 344 11.7 T1/E1/J1 Transceiver Registers Register Name: TR.MSTRREG Register Description: Master Mode Register Register Address: 00h Bit # 7 6 5 4 3 2 1 0 Name — — — — TEST1 TEST0 T1/E1 SFTRST Default 0 0 0 0 0 0 0 0 Bits 2 – 3: Test Mode Bits (TEST0, TEST1) Test modes are ...

  • Maxim DS33R11 - page 202

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 202 of 344 Register Name: TR.IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 5 4 3 2 1 0 Name RSMS RSMS2 RSMS1 RS IO TSDW TSM TSIO ODF Default 0 0 0 0 0 0 0 0 Bit 7: RSYNC Multiframe Skip Control (RSMS) Useful in framing format conversions from D4 ...

  • Maxim DS33R11 - page 203

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 203 of 344 Register Name: TR.IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 5 4 3 2 1 0 Name RCLKINV TCLKINV RSYNCINV TSYNCI NV TSSYNCINV H100EN TSCLKM RSCLKM Default 0 0 0 0 0 0 0 0 Bit 7: RCLKO Invert (RCLKINV) 0 = no inversion 1 = inverts sign ...

  • Maxim DS33R11 - page 204

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 204 of 344 Register Name: TR.T1RCR1 Register Description: T1 Receive Control Register 1 Register Address: 03h Bit # 7 6 5 4 3 2 1 0 Name — ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC Default 0 0 0 0 0 0 0 0 Bit 6: Auto Resync Criteria (ARC) 0 = resync on OOF or RCL event 1 = resync on OOF o ...

  • Maxim DS33R11 - page 205

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 205 of 344 Register Name: TR.T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 5 4 3 2 1 0 Name — RFM RB8ZS RSLC96 RZSE — RJC RD4YM Default 0 0 0 0 0 0 0 0 Bit 6: Receive Frame Mode Select (RFM) 0 = D4 framing mode 1 = ESF framing mode Bit 5: ...

  • Maxim DS33R11 - page 206

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 206 of 344 Register Name: TR.T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 5 4 3 2 1 0 Name TJC TFPT TCPT TSSE GB7S TFDLS TBL TYEL Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Japanese CRC6 Enable (TJC) 0 = use ANSI/AT&T/ITU CRC6 calculation ( ...

  • Maxim DS33R11 - page 207

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 207 of 344 Register Name: TR.T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 5 4 3 2 1 0 Name TB8ZS TSLC96 TZSE FBCT2 FBCT1 TD4YM — TB7ZS Default 0 0 0 0 0 0 0 0 Bit 7: Transmit B8ZS Enable (TB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 6: Tr ...

  • Maxim DS33R11 - page 208

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 208 of 344 Register Name: TR.T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 07h Bit # 7 6 5 4 3 2 1 0 Name — — — TRAI-CI TAIS-CI TFM PDE TLOOP Default 0 0 0 0 0 0 0 0 Bit 4: Transmit RAI-CI Enable (TRAI-CI). Setting this bit causes the ESF RA I-CI code ...

  • Maxim DS33R11 - page 209

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 209 of 344 Register Name: TR.SSIE1 (E1 Mode) Register Description: Softw are Signaling Insertion Enable 1 Register Address: 08h Bit # 7 6 5 4 3 2 1 0 Name CH7 CH6 CH5 CH4 CH3 CH2 CH1 UCAW Default 0 0 0 0 0 0 0 0 Bits 1 – 7: Softw are Signaling-Insertion Enable for Channels 1 to 7 (CH1 ...

  • Maxim DS33R11 - page 210

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 210 of 344 Register Name: TR.SSIE3 (T1 Mode) Register Description: Softw are Signaling-Insertion Enable 3 Register Address: 0Ah Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Softw are Signaling Insertion Enable for Channels 17 to ...

  • Maxim DS33R11 - page 211

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 211 of 344 Register Name: TR.T1RDMR1 Register Description: T1 Receive Digital-Milliwatt Enable Register 1 Register Address: 0Ch Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Receive Digital-Milliwatt Enable for Channels 1 to 8 (CH1 to CH8) ...

  • Maxim DS33R11 - page 212

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 212 of 344 Register Name: TR.IDR Register Description: Device Identification Register Register Address: 0Fh Bit # 7 6 5 4 3 2 1 0 Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Default 1 0 1 1 X X X X Bits 4 - 7: Device ID (ID4 to ID7). The upper four bits of TR.IDR are used to display the transce ...

  • Maxim DS33R11 - page 213

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 213 of 344 Register Name: TR.INFO2 Register Description: Information Register 2 Register Address: 11h Bit # 7 6 5 4 3 2 1 0 Name BSYNC BD TCLE TOCD RL3 RL2 RL1 RL0 Default 0 0 0 0 0 0 0 0 Bit 7: BERT Real-Time Sy nc hronization Status (BSYNC). Real-time status of the synchronizer (this b ...

  • Maxim DS33R11 - page 214

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 214 of 344 Register Name: TR.INFO3 Register Description: Information Register 3 Register Address: 12h Bit # 7 6 5 4 3 2 1 0 Name — — — — — CRCRC FASRC CASRC Default 0 0 0 0 0 0 0 0 Bit 2: CRC Resync Criteria Met Ev ent (CRCRC). Set when 915/1000 codewords are received in error. ...

  • Maxim DS33R11 - page 215

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 215 of 344 Register Name: TR.SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6 5 4 3 2 1 0 Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC Default 0 0 0 0 0 0 0 0 Bit 7: Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RR ...

  • Maxim DS33R11 - page 216

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 216 of 344 Register Name: TR.IMR1 Register Description: Interrupt Mask Register 1 Register Address: 17h Bit # 7 6 5 4 3 2 1 0 Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC Default 0 0 0 0 0 0 0 0 Bit 7: Input Level Under Threshold (ILUT) 0 = interrupt masked 1 = interrupt enabled Bit ...

  • Maxim DS33R11 - page 217

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 217 of 344 Register Name: TR.SR2 Register Description: Status Register 2 Register Address: 18h Bit # 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0 Bit 7: Receive Yellow Alarm Clear Event (RYELC) (T1 Only). Set when the receive Yellow Alarm condi ...

  • Maxim DS33R11 - page 218

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 218 of 344 Register Name: TR.IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19h Bit # 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0 Bit 7: Receive Yellow Alarm Clear Event (RYELC) 0 = interrupt masked 1 = interrupt enable ...

  • Maxim DS33R11 - page 219

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 219 of 344 Register Name: TR.SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0 Bit 7: Spare Code Detected Condition (LSPARE) (T1 Only). Set when the spare code as defined in the TR ...

  • Maxim DS33R11 - page 220

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 220 of 344 Register Name: TR.IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0 Bit 7: Spare Code Detected Condition (LSPARE) 0 = interrupt masked 1 = interrupt enabled—i ...

  • Maxim DS33R11 - page 221

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 221 of 344 Register Name: TR.SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 5 4 3 2 1 0 Name RAIS-CI RSAO RSAZ TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0 Bit 7: Receive AIS-CI Event (RAIS-CI) (T1 Only ). Set when the receiver detects t he AIS-CI pattern as ...

  • Maxim DS33R11 - page 222

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 222 of 344 Register Name: TR.IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 5 4 3 2 1 0 Name RAIS-CI RSAO RSAZ TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0 Bit 7: Receive AIS-CI Event (RAIS-CI) 0 = interrupt masked 1 = interrupt enabled Bit 6: Receiv ...

  • Maxim DS33R11 - page 223

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 223 of 344 Register Name: TR.SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 5 4 3 2 1 0 Name — — TESF TESEM TSLIP RESF RESEM RSLIP Default 0 0 0 0 0 0 0 0 Bit 5: Transmit Elastic Store Full Event (TESF). Set when the transmit elastic st ore buffer fills a ...

  • Maxim DS33R11 - page 224

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 224 of 344 Register Name: TR.IMR5 Register Description: Interrupt Mask Register 5 Register Address: 1Fh Bit # 7 6 5 4 3 2 1 0 Name — — TESF TESEM TSLIP RESF RESEM RSLIP Default 0 0 0 0 0 0 0 0 Bit 5: Transmit Elastic Store Full Event (TESF) 0 = interrupt masked 1 = interrupt enabled ...

  • Maxim DS33R11 - page 225

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 225 of 344 Register Name: TR.SR6, TR.SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Register 7 Register Address: 20h, 22h Bit # 7 6 5 4 3 2 1 0 Name — TMEND RPE RPS RHWM RNE TLWM TNF Default 0 0 0 0 0 0 0 0 Bit 6: Transmit Message-End Event (TMEND). Set when the tra ...

  • Maxim DS33R11 - page 226

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 226 of 344 Register Name: TR.IMR6, TR.IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 Register Address: 21h, 23h Bit # 7 6 5 4 3 2 1 0 Name — TMEND RPE RPS RHWM RNE TLWM TNF Default 0 0 0 0 0 0 0 0 Bit 6: Transmit Message-End Event (TMEN ...

  • Maxim DS33R11 - page 227

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 227 of 344 Register Name: TR.INFO5, TR.INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # 7 6 5 4 3 2 1 0 Name — — TEMPTY TFULL REMPTY PS2 PS1 PS0 Default 0 0 0 0 0 0 0 0 Bit 5: Transmit FIFO Empty (TEMPTY). A real-t ...

  • Maxim DS33R11 - page 228

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 228 of 344 Register Name: TR.SR8 Register Description: Status Register 8 Register Address: 24h Bit # 7 6 5 4 3 2 1 0 Name — — BOCC RFDLAD RFDLF TFDLE RMTCH RBOC Default 0 0 0 0 0 0 0 0 Bit 5: BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence. Bit 4: RFDL Ab ...

  • Maxim DS33R11 - page 229

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 229 of 344 Register Name: TR.SR9 Register Description: Status Register 9 Register Address: 26h Bit # 7 6 5 4 3 2 1 0 Name — BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC Default 0 0 0 0 0 0 0 0 Bit 6: BERT Bit-Error Det ected (BED) Event (BBED). A latched bit that is set when a bit error is det ...

  • Maxim DS33R11 - page 230

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 230 of 344 Register Name: TR.IMR9 Register Description: Interrupt Mask Register 9 Register Address: 27h Bit # 7 6 5 4 3 2 1 0 Name — BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC Default 0 0 0 0 0 0 0 0 Bit 6: Bit-Error Detected Event (BBED) 0 = interrupt masked 1 = interrupt enabled Bit 5: BER ...

  • Maxim DS33R11 - page 231

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 231 of 344 Register Name: TR.PCPR Register Description: Per-Channel Pointer Register Register Address: 28h Bit # 7 6 5 4 3 2 1 0 Name RSAOICS RSRCS RFCS BRCS THSCS PEICS TFCS BTCS Default 0 0 0 0 0 0 0 0 Bit 7: Receive Signaling All-Ones In sertion Channel Select (RSAOICS) Bit 6: Receive ...

  • Maxim DS33R11 - page 232

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 232 of 344 Register Name: TR.PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h Bit # 7 6 5 4 3 2 1 0 Name — — — — — — — — Default CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Register Name: TR.PCDR2 Register Description: Per-Channel Data Register 2 Register ...

  • Maxim DS33R11 - page 233

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 233 of 344 Register Name: TR.INFO7 Register Description: Information Register 7 (Real-T ime, Non-Latched Register) Register Address: 30h Bit # 7 6 5 4 3 2 1 0 Name CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA Default 0 0 0 0 0 0 0 0 Bits 3 – 7: CRC4 Sync Counter Bits (CSC0, CSC2 to CSC4 ...

  • Maxim DS33R11 - page 234

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 234 of 344 Register Name: TR.E1RCR1 Register Description: E1 Receive Control Register 1 Register Address: 33h Bit # 7 6 5 4 3 2 1 0 Name RSERC RSIGM RHDB3 RG802 RCRC4 FRC SYNCE RESYNC Default 0 0 0 0 0 0 0 0 Bit 7: RSERO Control (RSERC) 0 = allow RSERO to output data as received under al ...

  • Maxim DS33R11 - page 235

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 235 of 344 Register Name: TR.E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h Bit # 7 6 5 4 3 2 1 0 Name TFPT T16S TUA1 TSiS TSA1 THDB3 TG802 TCRC4 Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Time Slot 0 Pass-Through (TFPT) 0 = FAS bits/Sa bits/remote alarm s ...

  • Maxim DS33R11 - page 236

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 236 of 344 Register Name: TR.E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 36h Bit # 7 6 5 4 3 2 1 0 Name - - - - - AEBE AAIS ARA Default 0 0 0 0 0 0 0 0 Bit 2: Automatic E-Bit Enable (AEBE) 0 = E-bits not automatically set in the transmit direction 1 = E- ...

  • Maxim DS33R11 - page 237

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 237 of 344 Register Name: TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4 Register Description: Receive Signaling Change-of-State Information Register Address: 38h, 39h, 3Ah, 3Bh (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RSINFO1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RSINFO2 CH24 CH23 C ...

  • Maxim DS33R11 - page 238

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 238 of 344 Register Name: TR.SIGCR Register Description: Signaling Control Register Register Address: 40h Bit # 7 6 5 4 3 2 1 0 Name GRSRE — — RFE RFF RCCS TCCS FRSAO Default 0 0 0 0 0 0 0 0 Bit 7: Global Receive Signaling Reinsertion Enable (GRSRE). This bit allows the user to reins ...

  • Maxim DS33R11 - page 239

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 239 of 344 Register Name: TR.ERCNT Register Description: Error-Counter Configuration Register Register Address: 41h Bit # 7 6 5 4 3 2 1 0 Name — MECU ECUS EAMS VCRFS FSBE MOSCRF LCVCRF Default 0 0 0 0 0 0 0 0 Bit 6: Manual Error-Counter Update (MECU). When enabled by TR.ERCNT.4, the ch ...

  • Maxim DS33R11 - page 240

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 240 of 344 Register Name: TR.LCVCR1 Register Description: Line-Code Violation Count Register 1 Register Address: 42h Bit # 7 6 5 4 3 2 1 0 Name LCVC15 LCVC14 LCVC13 LCVC 12 LCVC11 LCVC10 LCVC9 LCVC8 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Line-Code Violation Counter Bits 8 to 15 (LCVC8 to ...

  • Maxim DS33R11 - page 241

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 241 of 344 Register Name: TR.FOSCR1 Register Description: Frames Out-of-Sync Count Register 1 Register Address: 46h Bit # 7 6 5 4 3 2 1 0 Name FOS15 FOS14 FOS13 FOS12 FOS11 FOS10 FOS9 FOS8 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Frames Out-of-Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS1 ...

  • Maxim DS33R11 - page 242

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 242 of 344 Register Name: TR.LBCR Register Description: Loopback Control Register Register Address: 4Ah Bit # 7 6 5 4 3 2 1 0 Name — — — LIUC LLB RLB PLB FLB Default 0 0 0 0 0 0 0 0 Bit 4: Line Interface Unit Mux Control (LIUC). This is a software version of the LIUC pin. When the ...

  • Maxim DS33R11 - page 243

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 243 of 344 Register Name: TR.PCLR1 Register Description: Per-Channel Loopback Enable Register 1 Register Address: 4Bh Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Per-Channel Loopback Enable for Channels 1 to 8 (CH1 to CH8) 0 = loopback ...

  • Maxim DS33R11 - page 244

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 244 of 344 Register Name: TR.ESCR Register Description: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 5 4 3 2 1 0 Name TESALGN TESR TESMDM TESE RESALGN RESR RESMDM RESE Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Elastic Store Align (TESALGN). Setting this bit from a 0 to a ...

  • Maxim DS33R11 - page 245

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 245 of 344 Register Name: TR.TS1 to TR.TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h to 5Fh (MSB) (LSB) 0 0 0 0 X Y X X TS1 CH2-A CH2-B CH2-C CH2-D CH1-A CH1-B CH1-C CH1-D TS2 CH4-A CH4-B CH4-C CH4-D CH3-A CH3-B CH3-C CH3-D TS3 CH6-A ...

  • Maxim DS33R11 - page 246

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 246 of 344 Register Name: TR.TS1 to TR.TS16 Register Description: Transmit Signaling Registers (E1 Mode, CCS Format) Register Address: 50h to 5Fh (MSB) (LSB) 1 2 3 4 5 6 7 8 TS1 9 10 11 12 13 14 15 16 TS2 17 18 19 20 21 22 23 24 TS3 25 26 27 28 29 30 31 32 TS4 33 34 35 36 37 38 39 40 TS5 ...

  • Maxim DS33R11 - page 247

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 247 of 344 Register Name: TR.TS1 to TR.TS12 Register Description: Transmit Signaling Registers (T1 Mode, ESF Format) Register Address: 50h to 5Bh (MSB) (LSB) CH2-A CH2-B CH2-C CH2-D CH1 -A CH1-B CH1-C CH1-D TS1 CH4-A CH4-B CH4-C CH4-D CH3-A CH3-B CH3-C CH3-D TS2 CH6-A CH6-B CH6-C CH6-D C ...

  • Maxim DS33R11 - page 248

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 248 of 344 Register Name: TR.TS1 to TR.TS12 Register Description: Transmit Signaling Registers (T1 Mode, D4 Format) Register Address: 50h to 5Bh (MSB) (LSB) CH2-A CH2-B CH2-A CH2-B CH1-A CH1-B CH1-A CH1-B TS1 CH4-A CH4-B CH4-A CH4-B CH3-A CH3-B CH3-A CH3-B TS2 CH6-A CH6-B CH6-A CH6-B CH5 ...

  • Maxim DS33R11 - page 249

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 249 of 344 Register Name: TR.RS1 to TR.RS12 Register Description: Receive Signaling Registers (T1 Mode, ESF Format) Register Address: 60h to 6Bh (MSB) (LSB) CH2-A CH2-B CH2-C CH2-D CH1 -A CH1-B CH1-C CH1-D RS1 CH4-A CH4-B CH4-C CH4-D CH3-A CH3-B CH3-C CH3-D RS2 CH6-A CH6-B CH6-C CH6-D CH ...

  • Maxim DS33R11 - page 250

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 250 of 344 Register Name: TR.RS1 to TR.RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h to 6Fh (MSB) (LSB) 0 0 0 0 X Y X X RS1 CH2-A CH2-B CH2-C CH2-D CH1-A CH1-B CH1-C CH1-D RS2 CH4-A CH4-B CH4-C CH4-D CH3-A CH3-B CH3-C CH3-D RS3 CH6-A C ...

  • Maxim DS33R11 - page 251

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 251 of 344 Register Name: TR.CCR1 Register Description: Common Control Register 1 Register Address: 70h Bit # 7 6 5 4 3 2 1 0 Name MCLKS CRC4R SIE ODM DICAI TCSS1 TCSS0 RLOSF Default 0 0 0 0 0 0 0 0 Bit 7: MCLK Source (MCLKS). Selects the source of MCLK 0 = MCLK is source from the MCLK p ...

  • Maxim DS33R11 - page 252

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 252 of 344 Register Name: TR.CCR2 Register Description: Common Control Register 2 Register Address: 71h Bit # 7 6 5 4 3 2 1 0 Name — — — — — BPCS1 BPCS0 BPEN Default 0 0 0 0 0 0 0 0 Bits 1 – 2: Backplane Clock Selects (BPCS0, BPCS1) BPCS1 BPCS0 BPCLK Frequency (MHz) 0 0 16.38 ...

  • Maxim DS33R11 - page 253

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 253 of 344 Register Name: TR.CCR4 Register Description: Common Control Register 4 Register Address: 73h Bit # 7 6 5 4 3 2 1 0 Name RLT3 RLT2 RLT1 RLT0 — — — — Default 0 0 0 0 0 0 0 0 Bits 4 – 7: Receive Level Threshold Bits (RLT0 to RLT3) RLT3 RLT2 RLT1 RLT0 Receive Level (dB) ...

  • Maxim DS33R11 - page 254

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 254 of 344 Register Name: TR.TDS0M Register Description: Transmit DS0 Monitor Register Register Address: 75h Bit # 7 6 5 4 3 2 1 0 Name B1 B2 B3 B4 B5 B6 B7 B8 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Transmit DS0 Channel Bits (B1 to B8). Transmit channel data that has been selected by the ...

  • Maxim DS33R11 - page 255

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 255 of 344 Register Name: TR.LIC1 Register Description: Line Interface Control 1 Register Address: 78h Bit # 7 6 5 4 3 2 1 0 Name L2 L1 L0 EGL JAS JABDS DJA TPD Default 0 0 0 0 0 0 0 0 Bits 5 – 7: Line Build-Out Select (L0 to L2). When using the internal termination, the user needs onl ...

  • Maxim DS33R11 - page 256

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 256 of 344 Register Name: TR.TLBC Register Description: Transmit Line Build-Out Control Register Address: 7Dh Bit # 7 6 5 4 3 2 1 0 Name — AGCE GC5 GC4 GC3 GC2 GC1 GC0 Default 0 0 0 0 0 0 0 0 Bit 6: Automatic Gain Control Enable (AGCE). 0 = use Transmit AGC, TR.TLBC bits 0–5 are “d ...

  • Maxim DS33R11 - page 257

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 257 of 344 Register Name: TR.LIC2 Register Description: Line Interface Control 2 Register Address: 79h Bit # 7 6 5 4 3 2 1 0 Name ETS LIRST IBPV TUA1 JAMUX — SCLD CLDS Default 0 0 0 0 0 0 0 0 Bit 7: E1/T1 Select (ETS) 0 = T1 mode selected 1 = E1 mode selected Bit 6: Line Interface Rese ...

  • Maxim DS33R11 - page 258

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 258 of 344 Register Name: TR.LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bit # 7 6 5 4 3 2 1 0 Name — TCES RCES MM1 MM0 RSCLKE TSCLKE TAOZ Default 0 0 0 0 0 0 0 0 Bit 6: Transmit-Clock Edge Select (TCES). Selects which TDCLKI edge to sample TPOSI and TNEGI ...

  • Maxim DS33R11 - page 259

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 259 of 344 Register Name: TR.LIC4 Register Description: Line Interface Control 4 Register Address: 7Bh Bit # 7 6 5 4 3 2 1 0 Name CMIE CMII MPS1 MPS0 TT1 TT0 RT1 RT0 Default 0 0 0 0 0 0 0 0 Bit 7: CMI Enable (CMIE) 0 = disable CMI mode 1 = enable CMI mode Bit 6: CMI Invert (CMII) 0 = CMI ...

  • Maxim DS33R11 - page 260

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 260 of 344 Register Name: TR.IAAR Register Description: Idle Array Address Register Register Address: 7Eh Bit # 7 6 5 4 3 2 1 0 Name GRIC GTIC IAA5 IAA4 IAA3 IAA2 IAA1 IAA0 Default 0 0 0 0 0 0 0 0 Bit 7: Global Receive-Idle Code (GRIC). Setting this bit causes all receiv e channels to be ...

  • Maxim DS33R11 - page 261

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 261 of 344 Register Name: TR.TCICE2 Register Description: Transmit-Channel Idle-Code Enable Register 2 Register Address: 81h Bit # 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Transmit Channels 9 to 16 Code Insertion Control Bits (CH9 ...

  • Maxim DS33R11 - page 262

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 262 of 344 Register Name: TR.RCICE2 Register Description: Receive-Channel Idle-Code Enable Register 2 Register Address: 85h Bit # 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Receive Channels 9 to 16 Code Insertion Control Bits (CH9 to ...

  • Maxim DS33R11 - page 263

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 263 of 344 Register Name: TR.RCBR2 Register Description: Receive Channel Blocking Register 2 Register Address: 89h Bit # 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Receive Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16) ...

  • Maxim DS33R11 - page 264

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 264 of 344 Register Name: TR.TCBR1 Register Description: Transmit Channel Blocking Register 1 Register Address: 8Ch Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Transmit Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8) 0 = for ...

  • Maxim DS33R11 - page 265

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 265 of 344 Register Name: TR.H1TC, TR.H2TC Register Description: HDLC #1 Transmit Control HDLC #2 Transmit Control Register Address: 90h, A0h Bit # 7 6 5 4 3 2 1 0 Name NOFS TEOML THR TH MS TFS TEOM TZSD TCRCD Default 0 0 0 0 0 0 0 0 Bit 7: Number of Flags Select (NOFS) 0 = send one flag ...

  • Maxim DS33R11 - page 266

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 266 of 344 Register Name: TR.H1FC, TR.H2FC Register Description: HDLC # 1 FIFO Control HDLC # 2 FIFO Control Register Address: 91h, A1h Bit # 7 6 5 4 3 2 1 0 Name — — TFLWM2 TFLWM1 TFLWM0 RFHWM2 RFHWM1 RFHWM0 Default 0 0 0 0 0 0 0 0 Bits 3 – 5: Transmit FIFO Low -Watermark Select ( ...

  • Maxim DS33R11 - page 267

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 267 of 344 Register Name: TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4 TR.H2RCS1, TR.H2RCS2, TR.H2RCS3, TR.H2RCS4 Register Description: HDLC # 1 Receive Channel Select HDLC # 2 Receive Channel Select Register Address: 92h, 93h, 94h, 95h A2h, A3h, A4h, A5h Bit # 7 6 5 4 3 2 1 0 Name RHCS7 R ...

  • Maxim DS33R11 - page 268

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 268 of 344 Register Name: TR.H1RTSBS, TR.H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select Register Address: 96h, A6h Bit # 7 6 5 4 3 2 1 0 Name RCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE Default 0 0 0 ...

  • Maxim DS33R11 - page 269

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 269 of 344 Register Name: TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4 TR.H2TCS1, TR.H2TCS2, TR.H2TCS3, TR.H2TCS4 Register Description: HDLC # 1 Transmit Channel Select HDLC # 2 Transmit Channel Select Register Address: 97h, 98h, 99h, 9Ah A7h, A8h, A9h, AAh Bit # 7 6 5 4 3 2 1 0 Name THCS7 ...

  • Maxim DS33R11 - page 270

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 270 of 344 Register Name: TR.H1TTSBS, TR.H2TTSBS Register Description: HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select Register Address: 9Bh, ABh Bit # 7 6 5 4 3 2 1 0 Name TCB8SE TCB7SE TCB6SE TCB5 SE TCB4SE TCB3SE TCB2SE TCB1SE Default 0 ...

  • Maxim DS33R11 - page 271

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 271 of 344 Register Name: TR.H1TF, TR.H2TF Register Description: HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO Register Address: 9Dh, ADh Bit # 7 6 5 4 3 2 1 0 Name THD7 THD6 THD5 THD4 THD3 THD2 THD1 THD0 Default 0 0 0 0 0 0 0 0 Bit 7: Transmit HDLC Data Bit 7 (THD7). MSB of an HDLC pack ...

  • Maxim DS33R11 - page 272

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 272 of 344 Register Name: TR.H1TFBA, TR.H2TFBA Register Description: HDLC # 1 Transmit FIFO Buffer Available HDLC # 2 Transmit FIFO Buffer Available Register Address: 9Fh, Afh Bit # 7 6 5 4 3 2 1 0 Name TFBA7 TFBA6 TFBA5 TFBA4 TFBA3 TFBA2 TFBA1 TFBA0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: ...

  • Maxim DS33R11 - page 273

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 273 of 344 Register Name: TR.TCD1 Register Description: Transmit Code-Definition Register 1 Register Address: B7h Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Code-Definition Bit 7 (C7). First bit of the repeating pattern. Bits 3 – 6: Trans ...

  • Maxim DS33R11 - page 274

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 274 of 344 Register Name: TR.RUPCD1 Register Description: Receive Up-Code Definition Register 1 Register Address: B9h Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Note: Writing this register resets t he detector’s integration period. Bit 7: Receive Up-Code ...

  • Maxim DS33R11 - page 275

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 275 of 344 Register Name: TR.RDNCD1 Register Description: Receive Down-Code Definition Register 1 Register Address: BBh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Note: Writing this register resets t he detector’s integration period. Bit 7: Receive Down- ...

  • Maxim DS33R11 - page 276

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 276 of 344 Register Name: TR.RSCC Register Description: In-Band Receive Spare Control Register Register Address: BDh Bit # 7 6 5 4 3 2 1 0 Name — — — — — RSC2 RSC1 RSC0 Default 0 0 0 0 0 0 0 0 Bits 3 – 7: Unused, must be set to 0 for proper operation Bits 0 – 2: Receive Spa ...

  • Maxim DS33R11 - page 277

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 277 of 344 Register Name: TR.RSCD1 Register Description: Receive Spare-Code Definition Register 1 Register Address: BEh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Note: Writing this register resets t he detector’s integration period. Bit 7: Receive Spare ...

  • Maxim DS33R11 - page 278

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 278 of 344 Register Name: TR.RFDL (TR.BOCC.4 = 1) Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 5 4 3 2 1 0 Name — — RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 Default 0 0 0 0 0 0 0 0 RFDL register bit definitions w hen TR.BOCC.4 = 1: Bit 5: BOC Bit 5 (RBOC5) Bi ...

  • Maxim DS33R11 - page 279

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 279 of 344 Register Name: TR.TFDL Register Description: Transmit FDL Register Register Address: C1h Bit # 7 6 5 4 3 2 1 0 Name TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0 Default 0 0 0 0 0 0 0 0 Note: Also used to insert Fs framing pattern in D4 framing mode. The transmit FDL registe ...

  • Maxim DS33R11 - page 280

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 280 of 344 Register Name: TR.RAF Register Description: Receive Align Frame Register Register Address: C6h Bit # 7 6 5 4 3 2 1 0 Name Si 0 0 1 1 0 1 1 Default 0 0 0 0 0 0 0 0 Bit 7: International Bit (Si) Bit 6: Frame Alignment Signal Bit (0) Bit 5: Frame Alignment Signal Bit (0) Bit 4: F ...

  • Maxim DS33R11 - page 281

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 281 of 344 Register Name: TR.RSiAF Register Description: Received Si Bits of the Align Frame Register Address: C8h Bit # 7 6 5 4 3 2 1 0 Name SiF0 SiF2 SiF4 SiF6 SiF8 SiF10 SiF12 SiF14 Default 0 0 0 0 0 0 0 0 Bit 7: Si Bit of Frame 0 (SiF0) Bit 6: Si Bit of Frame 2 (SiF2) Bit 5: Si Bit o ...

  • Maxim DS33R11 - page 282

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 282 of 344 Register Name: TR.RRA Register Description: Received Remote Alarm Register Address: Cah Bit # 7 6 5 4 3 2 1 0 Name RRAF1 RRAF3 RRAF5 RRAF7 RRAF9 RRAF11 RRAF13 RRAF15 Default 0 0 0 0 0 0 0 0 Bit 7: Remote Alarm Bit of Frame 1 (RRAF1) Bit 6: Remote Alarm Bit of Frame 3 (RRAF3) B ...

  • Maxim DS33R11 - page 283

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 283 of 344 Register Name: TR.RSa5 Register Description: Received Sa5 Bits Register Address: CCh Bit # 7 6 5 4 3 2 1 0 Name RSa5F1 RSa5F3 RSa5F5 RSa5F 7 RSa5F9 RSa5F11 RSa5F13 RSa5F15 Default 0 0 0 0 0 0 0 0 Bit 7: Sa5 Bit of Frame 1 (RSa5F1) Bit 6: Sa5 Bit of Frame 3 (RSa5F3) Bit 5: Sa5 ...

  • Maxim DS33R11 - page 284

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 284 of 344 Register Name: TR.RSa7 Register Description: Received Sa7 Bits Register Address: CEh Bit # 7 6 5 4 3 2 1 0 Name RSa7F1 Rsa7F3 RSa7F5 RSa7F 7 RSa7F9 RSa7F11 RSa7F13 RSa7F15 Default 0 0 0 0 0 0 0 0 Bit 7: Sa7 Bit of Frame 1(RSa4F1) Bit 6: Sa7 Bit of Frame 3 (RSa7F3) Bit 5: Sa7 B ...

  • Maxim DS33R11 - page 285

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 285 of 344 Register Name: TR.TAF Register Description: Transmit Align Frame Register Register Address: D0h Bit # 7 6 5 4 3 2 1 0 Name Si 0 0 1 1 0 1 1 Default 0 0 0 1 1 0 1 1 Bit 7: International Bit (Si) Bit 6: Frame Alignment Signal Bit (0) Bit 5: Frame Alignment Signal Bit (0) Bit 4: ...

  • Maxim DS33R11 - page 286

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 286 of 344 Register Name: TR.TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: D2h Bit # 7 6 5 4 3 2 1 0 Name TSiF0 TSiF2 TSiF4 TSiF6 TSiF8 TSiF10 TSiF12 TSiF14 Default 0 0 0 0 0 0 0 0 Bit 7: Si Bit of Frame 0 (TSiF0) Bit 6: Si Bit of Frame 2 (TSiF2) Bit 5 ...

  • Maxim DS33R11 - page 287

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 287 of 344 Register Name: TR.TRA Register Description: Transmit Remote Alarm Register Address: D4h Bit # 7 6 5 4 3 2 1 0 Name TRAF1 TRAF3 TRAF5 TRAF7 TRAF9 TRAF11 TRAF13 TRAF15 Default 0 0 0 0 0 0 0 0 Bit 7: Remote Alarm Bit of Frame 1 (TRAF1) Bit 6: Remote Alarm Bit of Frame 3 (TRAF3) B ...

  • Maxim DS33R11 - page 288

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 288 of 344 Register Name: TR.TSa5 Register Description: Transmitted Sa5 Bits Register Address: D6h Bit # 7 6 5 4 3 2 1 0 Name TSa5F1 TSa5F3 TSa5F5 TSa5F7 TSa5F9 TSa5F11 TSa5F13 TSa5F15 Default 0 0 0 0 0 0 0 0 Bit 7: Sa5 Bit of Frame 1 (TSa5F1) Bit 6: Sa5 Bit of Frame 3 (TSa5F3) Bit 5: Sa ...

  • Maxim DS33R11 - page 289

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 289 of 344 Register Name: TR.TSa7 Register Description: Transmit Sa7 Bits Register Address: D8h Bit # 7 6 5 4 3 2 1 0 Name TSa7F1 TSa7F3 TSa7F5 TSa7F7 TSa7F9 TSa7F11 TSa7F13 TSa7F15 Default 0 0 0 0 0 0 0 0 Bit 7: Sa7 Bit of Frame 1 (TSa4F1) Bit 6: Sa7 Bit of Frame 3 (TSa7F3) Bit 5: Sa7 B ...

  • Maxim DS33R11 - page 290

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 290 of 344 Register Name: TR.TSACR Register Description: Transmit Sa Bit Control Register Register Address: DAh Bit # 7 6 5 4 3 2 1 0 Name SiAF SiNAF RA Sa4 Sa5 Sa6 Sa7 Sa8 Default 0 0 0 0 0 0 0 0 Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF) 0 = do not insert data ...

  • Maxim DS33R11 - page 291

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 291 of 344 Register Name: TR.BRP1 Register Description: BERT Repetitive Pattern Set Register 1 Register Address: DCh Bit # 7 6 5 4 3 2 1 0 Name RPAT7 RPAT6 RPAT5 RPAT 4 RPAT3 RPAT2 RPAT1 RPAT0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: BERT Repetitive Pattern Set Bits 0 to 7 (RPAT0 to RPAT7) ...

  • Maxim DS33R11 - page 292

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 292 of 344 Register Name: TR.BC1 Register Description: BERT Control Register 1 Register Address: E0h Bit # 7 6 5 4 3 2 1 0 Name TC TINV RINV PS2 PS1 PS0 LC RESYNC Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the patt ...

  • Maxim DS33R11 - page 293

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 293 of 344 Register Name: TR.BC2 Register Description: BERT Control Register 2 Register Address: E1h Bit # 7 6 5 4 3 2 1 0 Name EIB2 EIB1 EIB0 SBE RPL3 RPL2 RPL1 RPL0 Default 0 0 0 0 0 0 0 0 Bits 5 – 7: Error Insert Bits 0 to 2 (EIB0 to EIB2). Automatically inserts bit errors at the pr ...

  • Maxim DS33R11 - page 294

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 294 of 344 Register Name: TR.BBC1 Register Description: BERT Bit Count Register 1 Register Address: E3h Bit # 7 6 5 4 3 2 1 0 Name BBC7 BBC6 BBC5 BBC 4 BBC3 BBC2 BBC1 BBC0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: BERT Bit Counter Bits 0 to 7 (BBC0 to BBC7). BBC0 is the LSB of the 32-bit cou ...

  • Maxim DS33R11 - page 295

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 295 of 344 Register Name: TR.BEC1 Register Description: BERT Error-Count Register 1 Register Address: E7h Bit # 7 6 5 4 3 2 1 0 Name EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Error Counter Bits 0 to 7 (EC0 to EC7). EC0 is the LSB of the 24-bit counter. Registe ...

  • Maxim DS33R11 - page 296

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 296 of 344 Register Name: TR.BIC Register Description: BERT Interface Control Register Register Address: EAh Bit # 7 6 5 4 3 2 1 0 Name — RFUS — TBAT TFUS — BERTDIR BERTEN Default 0 0 0 0 0 0 0 0 Bit 6: Receive Framed/Unframed Select (RFUS) 0 = BERT is not sent data from the F-bit ...

  • Maxim DS33R11 - page 297

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 297 of 344 Register Name: TR.ERC Register Description: Error-Rate Control Register Register Address: EBh Bit # 7 6 5 4 3 2 1 0 Name WNOE — — CE ER3 ER2 ER1 ER0 Default 0 0 0 0 0 0 0 0 Bit 7: Write NOE Registers (WNOE). If the host wishes to update to the TR.NOEx registers, this bit m ...

  • Maxim DS33R11 - page 298

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 298 of 344 Register Name: TR.NOE1 Register Description: Number-of-Errors 1 Register Address: ECh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Number-of-Errors Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter. Register Nam ...

  • Maxim DS33R11 - page 299

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 299 of 344 11.7.1 Number-of-Errors Left Register The host can read the TR.NOELx registers at any time to determine how many errors are left to be inserted. Register Name: TR.NOEL1 Register Description: Number-of-Errors Left 1 Register Address: EEh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C ...

  • Maxim DS33R11 - page 300

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 300 of 344 12 FUNCTIONAL TIMING 12.1 Functional Serial I/O Timing The Serial Interface provides flexible timing to interconnect with a wide variety of serial interfaces. TDEN is an input signal that can be used to enable or block the T SERO data. The “shaded bits” are not clocked by ...

  • Maxim DS33R11 - page 301

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 301 of 344 The DS33R11 provides the TBSYNC signal as a byte boundary indication to an external interface when X.86 (LAPS) functionality is selected. The functional timing of TBSYNC is shown in the following figure.TBSYNC is active high on the last bit of the byte being shifted out, and o ...

  • Maxim DS33R11 - page 302

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 302 of 344 In Half-Duplex (DTE) Mode, the DS 33R11 supports CRS and COL signals. CRS is active when the PHY detects transmit or receive activity. If there is a collision as indicated by the CO L input, the DS33R11 will replace the data nibbles with jam nibbles. After a “random“ time ...

  • Maxim DS33R11 - page 303

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 303 of 344 RMII Receive data on RXD[1:0] is ex pected to be synchronous with the ri sing edge of the 50 MHz REF_CLK. The data is only valid if CRS_DV is high. The external PH Y asynchronously drives CRS_DV low during carrier loss. Figure 12-9. RMII Receive Interface Functional Timing RXD ...

  • Maxim DS33R11 - page 304

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 304 of 344 Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled) CHANNEL 23 CHANNEL 24 CHANNEL 1 CHANNEL 23 CHANNEL 24 CHANNEL 1 RCLKO RSERO RSYNC RFSYN C RSIG RCHCLK RCHBLK 1 B A C/A D/B A C/A D/B LSB F MSB MS B LSB AB NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figu ...

  • Maxim DS33R11 - page 305

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 305 of 344 Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSER O CHANNEL 1 RCHCLK RCHBLK RSY SCLK RSYNC CHANNEL 31 CHANNEL 32 1 3 4 RSY NC 2 RMSY NC RSIG CHANNEL 31 CHANNEL 32 B A C/A D/B C/A D/B AB CHANNEL 1 LSB MSB LSB F 5 NOTE 1: RSERO DATA IN CHANNELS 1, ...

  • Maxim DS33R11 - page 306

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 306 of 344 Figure 12-16. Transmit-Side ESF Timing 12345 6789 1 0 1 1 1 2 1 2 3 TSSY NC FRAM E# TSYNC TSYNC TSYNC 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 1 2345 NOTE 1: TSYNC IN FRAME MODE (TR.IOCR1.2 = 0) AND DOUBLE -WIDE FRAME SYNC IS NOT ENABLED (TR.IOCR1.3 = 0). NOTE 2: TSYNC I ...

  • Maxim DS33R11 - page 307

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 307 of 344 Figure 12-18. Transmit-Side 1.544MHz Bounda ry Timing (Elastic Store Enabled) LSB F MS B LSB MS B CHANNEL 1 CHANNEL 24 AB C / A D / B AB C / A D / B TSYS CLK TSERI TSSY NC TSI G TCHCLK TCHBLK CHANNEL 23 A CHANNEL 23 CHANNEL 24 CHANNEL 1 1 NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK C ...

  • Maxim DS33R11 - page 308

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 308 of 344 12.4 E1 Mode Figure 12-20. Receive-Side Timing FRAME# 1 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 RSYNC 1 RSYNC RFSYN C 2 NOTE 1: RSYNC IN FRAME MODE (TR.IOCR1.5 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (TR.IOCR1.5 = 1). NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAM ...

  • Maxim DS33R11 - page 309

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 309 of 344 Figure 12-22. Receive-Side Bounda ry Timing, RSYSCLK = 1.544MHz (E-Store Enabled) R SERO CHANNEL 23/31 CHANNEL 24/3 2 CHANNEL 1/2 RCHC L K RCHB L K RSYS CL K RSYNC 2 3 RSYNC 1 RMSYNC LSB F MSB MS B LSB 4 NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPP ...

  • Maxim DS33R11 - page 310

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 310 of 344 Figure 12-24. G.802 Timing, E1 Mode Only 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 0 31 32 TS # RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK CHANNEL 26 CHANNEL 25 LSB MS B RCLKO / RSYSCLK TCLK T / TSYS CLK RSERO / TSERI RCHCLK ...

  • Maxim DS33R11 - page 311

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 311 of 344 Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled) LSB MSB LSB MS B CHANNEL 1 CHANNEL 2 CHANNEL 1 CHANNEL 2 ABC D TCLK T TSERI TSYNC TSYNC TSI G TCHCLK TCHBLK 1 2 3 Si 1 A Sa 4 Sa5 Sa 6 Sa 7 Sa8 D NOTE 1: TSYNC IS IN THE OUTPUT MODE (TR.IOCR1.1 = 1). NOTE 2: T ...

  • Maxim DS33R11 - page 312

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 312 of 344 Figure 12-28. Transmit-Side Boundary Timi ng, TSYSCLK = 2.048MHz (Elastic Store Enabled) LSB F LSB MSB CHANNEL 1 CHANNEL 32 A B C D A B TSYSCLK TSERI TSSYNC TSIG TCHCLK TCHBL K CHANNEL 31 A CHANNEL 31 CHANNEL 32 CHANNEL 1 1 4 C D NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31 ...

  • Maxim DS33R11 - page 313

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 313 of 344 13 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V SS (except V DD )….………………………………………..-0.5V to +5.5V Supply Voltage (VDD3.3) Range with Respect to V SS ……………..……………………………? ...

  • Maxim DS33R11 - page 314

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 314 of 344 13.1 Thermal Characteristics Table 13-3. Thermal Characteristics PARAMETER MIN TYP MAX Ambient Temperature (Note 1) -40°C +85°C Junction Temperature (Note 2) +125°C Theta-JA ( θ JA ) in Still Air for 256-Pin 27mm BGA (Notes 2, 3) +20.3°C/W Note 1: The package is mounted on ...

  • Maxim DS33R11 - page 315

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 315 of 344 13.2 MII Interface Table 13-5. Transmit MII Interface (Note 1, Figure 13- 1 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS TX_CLK Period t1 400 40 ns TX_CLK Low Time t2 140 260 14 26 ns TX_CLK High Time t3 140 260 14 26 ns TX_CLK to TXD, TX_EN Delay t4 0 20 0 2 ...

  • Maxim DS33R11 - page 316

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 316 of 344 Table 13-6. Receive MII Interface (Note 1, Figure 13- 2 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS RX_CLK Period t5 400 40 ns RX_CLK Low Time t6 140 260 14 26 ns RX_CLK High Time t7 140 260 14 26 ns RXD, RX_DV to RX_CLK Setup Time t8 5 5 ns RX_CLK to RXD, R ...

  • Maxim DS33R11 - page 317

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 317 of 344 13.3 RMII Interface Table 13-7. Transmit RMII Interface (Note 1, Figure 13- 3 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK Frequency 50MHz ±50ppm 50MHz ±50ppm REF_CLK Period t1 20 20 ns REF_CLK Low Time t2 7 13 7 13 ns REF_CLK High Time t3 7 13 7 13 ...

  • Maxim DS33R11 - page 318

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 318 of 344 Table 13-8. Receive RMII Interface (Note 1, Figure 13- 4 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK Frequency 50MHz ±50ppm 50MHz ±50ppm MHz REF_CLK Period t1 20 20 ns REF_CLK Low Time t2 7 13 7 13 ns REF_CLK High Time t3 7 13 7 13 ns RXD, CRS_DV t ...

  • Maxim DS33R11 - page 319

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 319 of 344 13.4 MDIO Interface Table 13-9. MDIO Interface (Note 1, Figure 13- 5 ) PARAMETER SYMBOL MIN TYP MAX UNITS MDC Frequency 1.67 MHz MDC Period t1 540 600 660 ns MDC Low Time t2 270 300 330 ns MDC High Time t3 270 300 330 ns MDC to MDIO Output Delay t4 20 10 ns MDIO Setup Time t5 1 ...

  • Maxim DS33R11 - page 320

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 320 of 344 13.5 Transmit WAN Interface Table 13-10. Transmit WAN Interface (Note 1, Figure 13- 6 ) PARAMETER SYMBOL MIN TYP MAX UNITS TCLKE Frequency 52 MHz TCLKE Period t1 19.2 ns TCLKE Low Time t2 8 ns TCLKE High Time t3 8 ns TCLKE to TSERO Output Delay t4 3 10 ns TCLKE to TBSYNC Setup ...

  • Maxim DS33R11 - page 321

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 321 of 344 13.6 Receive WAN Interface Table 13-11. Receive WAN Interface (Note 1, Figure 13- 7 ) PARAMETER SYMBOL MIN TYP MAX UNITS RCLKI Frequency 52 MHz RCLKI Period t1 19.2 ns RCLKI Low Time t2 8 ns RCLKI High Time t3 8 ns RSERI Setup Time t4 7 ns RDEN Setup Time t4 7 ns RBSYNC Setup T ...

  • Maxim DS33R11 - page 322

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 322 of 344 13.7 SDRAM Timing Table 13-12. SDRAM Interface Timing (Note 1, Figure 13- 8 ) 100 MHz PARAMETER SYMBOL MIN TYP MAX UNITS SDCLKO Period t1 9.7 10 10.3 ns SDCLKO Duty Cycle t2 4 6 ns SDCLKO to SDATA Valid Write to SDRAM t3 7 ns SDCLKO to SDATA Drive On Write to SDRAM t4 4 ns SDCL ...

  • Maxim DS33R11 - page 323

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 323 of 344 Figure 13-8. SDRAM Interface Timing SDCLKO (output) SDATA (output) t1 SDATA (input) SRAS, SCAS, SW E, SDCS (output) t2 t3 t5 t6 t7 t8 t10 t9 SDA, SBA (output) SDMASK (output) t4 t12 t11 t14 t13 ...

  • Maxim DS33R11 - page 324

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 324 of 344 13.8 Microprocessor Bus AC Characteristics Table 13-13. AC Characteristi cs—Microprocessor Bus Timing (VDD3.3 = 3.3V ± 5%, VDD1.8 = 1.8V ± 5%, T j = -40°C to +85°C.) (Note 1, Figure 13- 9 , Figure 13-1 0 , Figure 13-1 1 , and Figure 13-1 2 ) PARAMETER SYMBOL MIN TYP MAX U ...

  • Maxim DS33R11 - page 325

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 325 of 344 Figure 13-9. Intel Bus Read Timing (MODEC = 00) t2 t3 Address Va lid Data Valid t4 t9 t5 t10 ADD R[ 12:0] DAT A[7 :0] CS RD WR t1 Figure 13-10. Intel Bus Write Timing (MODEC = 00) t2 t6 Address Va lid t4 t9 t10 ADD R[ 12:0] DAT A[7 :0] RD WR t7 t8 t1 CS /CST ...

  • Maxim DS33R11 - page 326

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 326 of 344 Figure 13-11. Motorola Bus Read Timing (MODEC = 01) t2 t3 Address Va lid Data Valid t4 t9 t5 t10 ADD R[ 12:0] DAT A[7 :0] DS RW t1 CS /CST Figure 13-12. Motorola Bus Write Timing (MODEC = 01) t2 t6 Address Va lid t4 t9 t10 ADD R[ 12:0] DAT A[7 :0] RW DS t7 t8 t1 CS /CST ...

  • Maxim DS33R11 - page 327

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 327 of 344 13.9 AC Characteristics: Receive-Side Table 13-14. AC Charact eristics: Receive Side (V DD = 3.3V ± 5%, T A = -40°C to +85°C.) (Note 1, Figure 13- 3 , Figure 13-1 4 , and Figure 13-1 5 ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 488 (E1) RDCLKO Period t LP 648 (T1) ns t ...

  • Maxim DS33R11 - page 328

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 328 of 344 Figure 13-13. Receive-Side Timing t D1 1 t D2 RSERO / RDA TA / RSIG RCHCLK RCHBLK RSYNC RCLKO RFSYNC / RM SYNC t D2 t D2 t D2 1ST FR AME BIT NOTE 1: RSYNC IS IN THE OUTPUT MODE. NOTE 2: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED. ...

  • Maxim DS33R11 - page 329

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 329 of 344 Figure 13-14. Receive-Side Timi ng, Elastic Store Enabled F t t R t D3 t D4 t D4 t D4 t t SU HD RSERO / RS IG RCHCLK RCHBLK 1 RSYNC 2 RSYNC RSYSCLK SL t t SP SH t t D4 RMSYNC SEE N OTE 3 NOTE 1: RSYNC IS IN THE OUTPUT MODE. NOTE 2: RSYNC IS IN THE INPUT MODE. NOTE 3: F-BIT WHEN ...

  • Maxim DS33R11 - page 330

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 330 of 344 Figure 13-15. Receive Line Interface Timing t F t R RPOSI, RNEGI RDCLKI CL t t CP CH t t SU t HD t DD RPOSO, RNEGO RDCLKO LL t t LP LH t ...

  • Maxim DS33R11 - page 331

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 331 of 344 13.10 AC Characteristics: Backplane Clock Timing Table 13-15. AC Characteristics: Backplane Clock Synthesis (V DD = 3.3V ± 5%, T A = -40°C to +85°C.) (Note 1, ( Figure 13-1 6 ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Delay RCLKO to BPCLK t D1 10 ns Note: Timing paramet ...

  • Maxim DS33R11 - page 332

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 332 of 344 13.11 AC Characteristics: Transmit Side Table 13-16. AC Characteris tics: Transmit Side (V DD = 3.3V ± 5%, T A = 0°C to +85°C.) (Note 1, Figure 13-17 , Figure 13-18 , and Figure 13-19 ) PARAMETER SYMBOL CONDITIONS MIN TYP (E1) MAX UNITS 488 (E1) TCLKT Period t CP 648 (T1) ns ...

  • Maxim DS33R11 - page 333

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 333 of 344 Figure 13-17. Transmit-Side Timing t F t R 1 TCLKT TSERI / TS IG / TDATA TCHCLK t t CL t CH CP TSY NC TSY NC TLIN K TLC LK TCHBLK t D2 t D2 t D2 t t t t t t HD SU D2 SU HD D1 t HD 2 5 TESO t SU NOTE 1: TSYNC IS IN THE OUTPUT MODE (IOCR1.1 = 1). NOTE 2: TSYNC IS IN THE INPUT MOD ...

  • Maxim DS33R11 - page 334

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 334 of 344 Figure 13-18. Transmit-Side Timing, Elastic Store Enabled t F t R TSYSCLK TSERI TCHCLK t t SL t SH SP TSS YNC TCHBLK t D3 t D3 t t t SU HD SU t HD NOTE 1: TSERI IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSC LK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. NOTE 2: TCHCLK AND T ...

  • Maxim DS33R11 - page 335

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 335 of 344 13.12 JTAG Interface Timing Table 13-17. JTAG Interface Timing (VDD3.3 = 3.3V ± 5%,VDD1.8 = 1.8V ± 5%, T j = -40°C to +85°C.) (Note 1, Figure 13-2 0 ) PARAMETER SYMBOL MIN TYP MAX UNITS JTCLK Clock Period t1 1000 ns JTCLK Clock High:Low Time (Note 2) t2 : t3 50 500 ns JTCLK ...

  • Maxim DS33R11 - page 336

    DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 336 of 344 14 JTAG INFORMATION The DS33R11 contains two JTAG ports. Port 1 is for the Ethernet Mapper, and Port 2 is for the T1/E1/J1 Transceiver. Because of this, this device requires special consideration during JTAG test design. For more information on performing JTAG testing using th ...

  • Maxim DS33R11 - page 337

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 337 of 344 14.1 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Te st Access Port (TAP) Controller State Machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. TAP Co ...

  • Maxim DS33R11 - page 338

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 338 of 344 Update-DR A falling edge on JTCLK while in the Update-DR state will latc h the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. Select-IR-Scan All test regist ...

  • Maxim DS33R11 - page 339

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 339 of 344 Figure 14-2. TAP Controller State Diagram 1 0 0 1 11 1 1 1 1 1 11 1 1 00 0 0 0 1 0 0 0 0 1 1 0 0 0 0 Select DR-Scan Captur e DR Shift D R Exit D R Pause DR Exit2 DR Update DR Select IR- Scan Captur e IR Shi f t IR Exit I R Pause I R Exit2 IR Update IR Test Lo gic Reset Run Test ...

  • Maxim DS33R11 - page 340

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 340 of 344 Table 14-1. Instruction Cod es for IEEE 1149.1 Architecture INSTRUCTION SELECTED REGISTER INSTRUCTION CODES SAMPLE:PRELOAD Boundary Scan 010 BYPASS Bypass 111 EXTEST Boundary Scan 000 CLAMP Bypass 011 HIGHZ Bypass 100 IDCODE Device Identification 001 SAMPLE:PRELOAD This is a ma ...

  • Maxim DS33R11 - page 341

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 341 of 344 14.3 JTAG ID Codes Table 14-2. ID Code Structure DEVICE REVISION ID[31:28] DEVICE CODE ID[27:12] MANUFACTURER’S CODE ID[11:1] REQUIRED ID[0] Ethernet Mapper 0000 0000 0000 0110 0001 000 1010 0001 1 T1/E1/J1 Transceiver 0000 0000 0000 0001 0000 000 1010 0001 1 14.4 Test Regist ...

  • Maxim DS33R11 - page 342

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 342 of 344 14.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from reset state. • Shifting out the first 4 LSB bits of the IDCODE. • Shifting in the BYPASS instruct ion (111) while shifting out the mandatory X01 pattern. ? ...

  • Maxim DS33R11 - page 343

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 343 of 344 15 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect t he most current specif ications . The package number provided for each package is a link to the latest package outline inf ormation.) 15.1 256-Ball BGA (27mm x 27mm) ( 56-G6004-001 ) ...

  • Maxim DS33R11 - page 344

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 344 of 344 Maxim/Dallas Semiconductor cannot assume re sponsibility for use of any circuitry other than circuitry entirely embodied in a M a xim/Dallas Semiconductor product. No circuit patent licenses are im plied. Maxim/Dallas Semiconducto r reserves the right to change the circuitry an ...

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