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Cypress CY7C1346H - page 1
2-Mbit (64K x 36) Pipelined Sync SRAM CY7C1346H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05672 Rev . *B Revised April 26, 2006 Features • Registered inp uts and outputs for pipelined op er ation • 64K × 36 common I/O architecture • 3.3V core power supply • 3.3 ...
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Cypress CY7C1346H - page 2
CY7C1346H Document #: 38-05672 Rev . *B Page 2 of 16 Pin Configuration Selection Guide 166 MHz Unit Maximum Access T i me 3.5 ns Maximum Operating Current 240 mA Maximum CMOS S tandby Cu rrent 40 mA A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/18M NC/9M A A A A A A NC/4M DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V ...
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Cypress CY7C1346H - page 3
CY7C1346H Document #: 38-05672 Rev . *B Page 3 of 16 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the 64K addre ss loca tions . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A 1 , A 0 feed the 2-bit counter . BW A ,BW ...
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Cypress CY7C1346H - page 4
CY7C1346H Document #: 38-05672 Rev . *B Page 4 of 16 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled b y the rising edge of the clock. The CY7C1346H supports secondary cache in systems utilizing either a linear or interleave ...
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Cypress CY7C1346H - page 5
CY7C1346H Document #: 38-05672 Rev . *B Page 5 of 16 Burst Sequences The CY7C1346H provid es a two-bit wraparound counter , fed by A 1 , A 0 , that implements either an interleaved or linear burst sequence. The interleaved burst sequ ence is designed specif- ically to support Intel Pentium appli cations. The linear burst sequence is designed to sup ...
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Cypress CY7C1346H - page 6
CY7C1346H Document #: 38-05672 Rev . *B Page 6 of 16 T ruth T able [2, 3, 4, 5, 6, 7] Next Cycle Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power-down None H X X L X L X X X L-H T ri-S tate Deselect Cycle, Power-down None L L X L L X X X X L-H T ri-S tate Deselect Cycle, Power-down None L X H L L X X X X L-H Tri-S tat ...
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Cypress CY7C1346H - page 7
CY7C1346H Document #: 38-05672 Rev . *B Page 7 of 16 WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D T ruth T able (continued) [2, 3, 4, 5, 6, 7] Next Cycle Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ T ruth T able for Read/W rite [2, 3] Function GW BWE BW D BW C BW ...
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Cypress CY7C1346H - page 8
CY7C1346H Document #: 38-05672 Rev . *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ................ .............. ... –65 ° C to +150 ° C Ambient T e mperature with Power Applied .............. ... ... ........... ... ... .. ...... –55 ° C to +125 ° C ...
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Cypress CY7C1346H - page 9
CY7C1346H Document #: 38-05672 Rev . *B Page 9 of 16 Cap acit ance [10] Parameter Description T est Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V . V DDQ = 2.5V 5 pF C CLK Clock Input Capacit ance 5 pF C I/O Input/Output Capacit ance 5 pF Thermal Resist ance [10] Parameter Description T est Conditi ons 1 ...
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Cypress CY7C1346H - page 10
CY7C1346H Document #: 38-05672 Rev . *B Page 10 of 16 Switching Characteristics Over the Operating Range [1 1, 12] Parameter Description -166 Unit Min. Max. t POWER V DD (T ypical) to the First Access [13] 1 ms Clock t CYC Clock Cycle T ime 6.0 ns t CH Clock HIGH 2.5 ns t CL Clock LOW 2.5 ns Output Times t CO Data Output V ali d after CLK Rise 3. 5 ...
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Cypress CY7C1346H - page 11
CY7C1346H Document #: 38-05672 Rev . *B Page 1 1 of 16 Switching W aveforms Read Cycle Timing [17] Note: 17. On this diagram, when CE is LOW, CE 1 is LOW, C E 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BW [A:D] D a ...
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Cypress CY7C1346H - page 12
CY7C1346H Document #: 38-05672 Rev . *B Page 12 of 16 Write Cycle T iming [17, 18] Note: 18. Full width Write can be initi ated by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW[A :D] D ata Out (Q) High-Z ADV BURST READ ...
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Cypress CY7C1346H - page 13
CY7C1346H Document #: 38-05672 Rev . *B Page 13 of 16 Read/Write Cycle Timing [17, 19, 20 ] Notes: 19. The data bus (Q) remains in High- Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 20. GW is HIGH. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CES BWE, B ...
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Cypress CY7C1346H - page 14
CY7C1346H Document #: 38-05672 Rev . *B Page 14 of 16 ZZ Mode T iming [21, 22] Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descr iptions t able for all possi ble signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INP ...
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Cypress CY7C1346H - page 15
CY7C1346H Document #: 38-05672 Rev . *B Page 15 of 16 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do ...
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Cypress CY7C1346H - page 16
CY7C1346H Document #: 38-05672 Rev . *B Page 16 of 16 Document History Page Document Title: CY7C1346H 2-Mbit (64K x 36) Pipelined Syn c SRAM Document Number: 38-05672 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 3 473 57 See ECN PCI New Data sheet *A 420879 See ECN RXU Converted from Preliminary to Fi nal. Changed address of Cy ...
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