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Manual Cypress CY7C1393BV18

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  • Cypress CY7C1393BV18 - page 1

    18-Mbit DDR-II SIO SRAM 2-W ord Burst Architecture CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05623 Rev . *D Revised June 2, 2008 Features ■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz clock for hi ...

  • Cypress CY7C1393BV18 - page 2

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 2 of 31 Logic Block Diagram (CY7C1392BV18) Logic Block Diagram (CY7C1992BV18) 1M x 8 Array CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. LD Q [7:0] Reg. Reg. Reg. 8 8 16 8 NWS [1:0] V REF Write Add. Decode Wri te D ...

  • Cypress CY7C1393BV18 - page 3

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 3 of 31 Logic Block Diagram (CY7C1393BV18) Logic Block Diagram (CY7C1394BV18) 512K x 18 Array CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. LD Q [17:0] Reg. Reg. Reg. 18 36 18 BWS [1:0] V REF Write Add. Decode Wri ...

  • Cypress CY7C1393BV18 - page 4

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 4 of 31 Pin Configuration The pin configuration for CY7C1392BV18, CY7C1992 BV18, CY7C1393BV18, and CY7 C1394BV18 follows. [1] 165-Ball FBGA (13 x 15 x 1 .4 mm) Pinout CY7C1392BV18 (2M x 8) 123456789 10 11 A CQ NC/72M A R/W NWS 1 K NC/144M LD A NC/36M CQ B NC NC ...

  • Cypress CY7C1393BV18 - page 5

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 5 of 31 CY7C1393BV18 (1M x 18) 123456789 10 11 A CQ NC/144M NC/36M R/W BWS 1 K NC/28 8M LD A NC/72M CQ B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AAA V SS NC Q7 D8 D NC D1 1 Q1 0 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V SS V SS V D ...

  • Cypress CY7C1393BV18 - page 6

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 6 of 31 Pin Definitions Pin Name IO Pin Descripti on D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during val id write opera tions. CY7C1392BV18 - D [7:0] CY7C1992BV18 - D [8:0] CY7C1393BV18 - D [17:0] CY7C1394BV18 ...

  • Cypress CY7C1393BV18 - page 7

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 7 of 31 CQ Echo Clock CQ is Referenced with Respect to C . This is a free-running clock and is synchronized to th e input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timi ngs for the echo clocks is s ...

  • Cypress CY7C1393BV18 - page 8

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 8 of 31 Functional Overview The CY7C1392BV18, CY7C1992BV18, CY7C1393 BV18, and CY7C1394BV18 are synchronous pipelined Burst SRAMs equipped with a DDR-II Separate IO interface . Accesses are initiated on the ri sing edge of the positive input clock (K). All sync ...

  • Cypress CY7C1393BV18 - page 9

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 9 of 31 DLL These chips use a Delay Lock Loop (DLL) that is design ed to function between 120 MHz a nd the specified maximum clock frequency . During power up, when the DOF F is tied HIGH, the DLL is locked after 1024 cycles of st able clock. The DLL can also b ...

  • Cypress CY7C1393BV18 - page 10

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 10 of 31 T ruth T able The truth table for CY7C1392BV18, CY7C1992BV 18, CY7C1393BV18, and CY7C1394BV18 follo ws. [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ DQ Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. L-H L L ...

  • Cypress CY7C1393BV18 - page 11

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 1 1 of 31 Write Cycle Descriptions The write cycle description tabl e for CY7C1992BV18 follows. [2, 8] BWS 0 K K L L–H – During the data portion of a write sequence, the single b yte (D [8:0] ) is written into the device. L – L –H During the data portio ...

  • Cypress CY7C1393BV18 - page 12

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 12 of 31 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.1-2001. The T AP operates usin g JEDEC standard 1.8V IO log ...

  • Cypress CY7C1393BV18 - page 13

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 13 of 31 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also place s the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the Shift ...

  • Cypress CY7C1393BV18 - page 14

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 14 of 31 T AP Controller St ate Diagram The state diagram for the T AP controller follows. [9] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 ...

  • Cypress CY7C1393BV18 - page 15

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 15 of 31 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 μ A1 ...

  • Cypress CY7C1393BV18 - page 16

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 16 of 31 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Setup to ...

  • Cypress CY7C1393BV18 - page 17

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 17 of 31 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1392BV18 CY7C1992BV18 CY7 C1393BV18 CY7C1394BV18 Revision Numb er (31:29) 000 000 000 000 V ersion number . Cypress Device ID (28:12) 1 10 10100010000101 1 1010100010001 1 ...

  • Cypress CY7C1393BV18 - page 18

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 18 of 31 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 27 1 1H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26 N 2 9 9 G 5 6 6 A 8 3 1 J 3 7P 30 1 1F 57 5B 84 2J 4 7N 31 1 1G 58 5A 85 3K 57 R 3 2 9 F 5 9 4 A 8 6 3 J 6 8R 33 10F 60 5C ...

  • Cypress CY7C1393BV18 - page 19

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 19 of 31 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW). ❐ A ...

  • Cypress CY7C1393BV18 - page 20

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 20 of 31 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ........................ ......... –65°C to +150°C Ambient T empe r at ur e with Power Appl i ed. . ? ...

  • Cypress CY7C1393BV18 - page 21

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 21 of 31 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 575 mA (x9) 575 (x18) 600 (x36) 630 167 MHz (x8) 485 mA (x9) 490 (x18) 500 (x36) 540 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ? ...

  • Cypress CY7C1393BV18 - page 22

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 22 of 31 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Condition s Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V , V DDQ = 1.5V 5 pF C CLK Clock Input ...

  • Cypress CY7C1393BV18 - page 23

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 23 of 31 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parameter Description 300 MHz 278 MHz 250 MHz 20 0 MHz 167 MHz Unit Min Max Min Max Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [22] 11111 ...

  • Cypress CY7C1393BV18 - page 24

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 24 of 31 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.45 – – 0.45 – –0.45 – – ...

  • Cypress CY7C1393BV18 - page 25

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 25 of 31 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 6, 27, 28 ] K 123 4 5 6 7 8 K LD R/W A Q D C C# READ (burst of 2) READ (burst of 2) READ (burst of 2) WRITE (burst of 2) WRITE (burst of 2) t KHCH t KHCH NOP NOP CQ CQ# t KH t KHKH t CO t K ...

  • Cypress CY7C1393BV18 - page 26

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 26 of 31 Ordering Information Not all of the speed, package, and temper ature ranges are available. Please cont act your local sale s representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Package T ype ...

  • Cypress CY7C1393BV18 - page 27

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 27 of 31 250 CY7C1392BV18-250BZC 51-85180 165-Ball F ine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1992BV18-250BZC CY7C1393BV18-250BZC CY7C1394BV18-250BZC CY7C1392BV18-250BZXC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Fre ...

  • Cypress CY7C1393BV18 - page 28

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 28 of 31 167 CY7C1392BV18-167BZC 51-85180 165-Ball F ine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1992BV18-167BZC CY7C1393BV18-167BZC CY7C1394BV18-167BZC CY7C1392BV18-167BZXC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Fre ...

  • Cypress CY7C1393BV18 - page 29

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 29 of 31 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BOTTOM ...

  • Cypress CY7C1393BV18 - page 30

    CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev . *D Page 30 of 31 Document History Page Document Title: CY7C1392BV18/CY7C1992BV18/CY7C13 93BV18/C Y7C139 4BV18 , 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number: 38-05623 Rev . ECN No. Submission Date Orig, of Change Description of Change ** 252474 See ...

  • Cypress CY7C1393BV18 - page 31

    Document #: 38-05623 Rev . *D Revised June 2, 2008 Page 31 of 31 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s developed by Cypress, I DT , NEC, Rene sas, and Samsung . All pr od uct and comp any names ment ioned in th is document are the tr ad emarks of their respe ctive hold ers. CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY ...

Manufacturer Cypress Category Computer Hardware

Documents that we receive from a manufacturer of a Cypress CY7C1393BV18 can be divided into several groups. They are, among others:
- Cypress technical drawings
- CY7C1393BV18 manuals
- Cypress product data sheets
- information booklets
- or energy labels Cypress CY7C1393BV18
All of them are important, but the most important information from the point of view of use of the device are in the user manual Cypress CY7C1393BV18.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Cypress CY7C1393BV18, service manual, brief instructions and user manuals Cypress CY7C1393BV18. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Cypress CY7C1393BV18.

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A complete manual for the device Cypress CY7C1393BV18, how should it look like?
A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Cypress CY7C1393BV18 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Cypress CY7C1393BV18.

A complete Cypress manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

1. Preface and tips on how to use the manual Cypress CY7C1393BV18 - At the beginning of each manual we should find clues about how to use the guidelines. It should include information about the location of the Contents of the Cypress CY7C1393BV18, FAQ or common problems, i.e. places that are most often searched by users in each manual
2. Contents - index of all tips concerning the Cypress CY7C1393BV18, that we can find in the current document
3. Tips how to use the basic functions of the device Cypress CY7C1393BV18 - which should help us in our first steps of using Cypress CY7C1393BV18
4. Troubleshooting - systematic sequence of activities that will help us diagnose and subsequently solve the most important problems with Cypress CY7C1393BV18
5. FAQ - Frequently Asked Questions
6. Contact detailsInformation about where to look for contact to the manufacturer/service of Cypress CY7C1393BV18 in a specific country, if it was not possible to solve the problem on our own.

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