English dropdown-ico

Manual Xilinx ML310

70 pages 1.02 mb
Download

Go to site of 70

Summary
  • Xilinx ML310 - page 1

    R ML310 User Guide V irtex-II Pro Embedded Development Platform UG068 ( v1.01) A ugust 2 5, 2004 ...

  • Xilinx ML310 - page 2

    ML310 U ser Guide www .xilinx .com UG068 ( v1. 01) Augu st 25, 200 4 1-800-255-7 778 "Xilinx" and t he Xili nx log o shown above a re re gister ed trad emarks of Xilinx , Inc. Any rig hts not ex press ly gra nted her ein ar e reserved. CoolRunn er , R ocketChip s, Rock et IP , Spartan, StateBENC H, StateC AD, Virtex, XAC T , XC2064, XC309 ...

  • Xilinx ML310 - page 3

    UG068 (v 1.01) August 25, 2 004 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 ML310 User Guide UG068 (v1.01) August 25, 2004 The following table shows th e revision history for this docu ment.. V ersion Revision 08/15/ 04 1.0 Initi al Xi linx r eleas e. 08/25/ 04 1.01 Added Sys ACE CFGADDR detail s. ...

  • Xilinx ML310 - page 4

    ML310 U ser Guide www .xilinx .com UG068 ( v1. 01) Augu st 25, 200 4 1-800-255-7 778 ...

  • Xilinx ML310 - page 5

    ML310 U ser Guide www .xilinx .com 5 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Preface: About This Manu al Chapter 1: Introd uction to Vi rtex-II Pro, ISE, an d EDK Virtex-II Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 Summary of Virtex-II Pro Features ...

  • Xilinx ML310 - page 6

    6 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 R PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ALi South Bridge Interfac e, M1535D+, U1 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Parall ...

  • Xilinx ML310 - page 7

    ML310 U ser Guide www .xilinx .com 7 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 R Pr efac e About This Manual This manual acco mpanies the ML310 Embedded Development System and con t ains informat ion about the ML 310 Hardwar e Platfo rm and softw ar e tools. Manual Conten ts This manu al co ntains th e follow ing chap ters: • Chapter 1, “ ...

  • Xilinx ML310 - page 8

    8 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter : R Conventions This document uses the following conventions. An example illustrates each convention. T ypographical The following typographical conventions are used in this document: Problem Solvers Interactive to ols that allo w you to troubleshoot y our ...

  • Xilinx ML310 - page 9

    ML310 U ser Guide www .xilinx .com 9 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 R Online Docu ment The following conventions ar e us ed in this document: V ert ical ellips is . . . Repetitive material tha t has been omitted IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ . . . Horizontal ellipsis . . . Repetitive material tha t has been omitted ...

  • Xilinx ML310 - page 10

    10 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter : R ...

  • Xilinx ML310 - page 11

    ML310 U ser Guide www .xilinx .com 11 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 R Chapter 1 Intr oduction to V irtex-II Pr o, ISE, and EDK V irtex-II Pro The V irtex-II Pro Platform FPGA sol ution is the mos t technically sophi sticated silicon a nd software pr oduct development in the history of the programmable logic industry . The goal was ...

  • Xilinx ML310 - page 12

    12 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 1: Introduction to V irtex-II Pro, ISE, and EDK R PowerPC™ 405 Core • Embedded 300+ MHz Harvard ar chitecture cor e • Low power cons u mption: 0.9 mW/MHz • Five-stage data path pipeline • Hardware multiply/divide uni t • Thirty-two 32 -bit gene ...

  • Xilinx ML310 - page 13

    ML310 U ser Guide www .xilinx .com 13 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Vir te x -I I Pr o R • Four levels of selectable pre-emphasis • Five levels of outp ut differ en tial voltage • Per-channel internal loopba ck modes • 2.5V transceiver supply vo ltage V irtex-II FPGA Fabr ic Description of the V irtex-II Family fabric foll ...

  • Xilinx ML310 - page 14

    14 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 1: Introduction to V irtex-II Pro, ISE, and EDK R - 840 Mb/s Low-V oltage Dif f eren t ial Signaling I/O (L VDS) with current mode drivers - Bus L VD S I/O - HyperT ransport ™ (LDT) I/O wi t h curr ent driver buffer s - Built-in DD R input and output reg ...

  • Xilinx ML310 - page 15

    ML310 U ser Guide www .xilinx .com 15 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Foundation ISE R IP . ISE even includes technology called IP Builder , which allows you to capture your own IP and r eus e it in other designs. ISE ’ s Architecture W izards allow easy access to device features like the Digital Clo ck Manager and M ulti-Gig abit ...

  • Xilinx ML310 - page 16

    16 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 1: Introduction to V irtex-II Pro, ISE, and EDK R Board Level Integration Xilinx understa nds the critical iss ues such as complex board layout, sign al integrity , high- speed bus interface, high-perf o rmance I/O bandwidth, and electr omagnetic interfere ...

  • Xilinx ML310 - page 17

    ML310 U ser Guide www .xilinx .com 17 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 R Chapter 2 ML310 Embedded Development Platform Overview The ML310 Embed ded Development P latform offers designers a versatile V irtex-II Pro XC2VP30-FF89 6 based platform for rapid pro t otyping and system verifi cation. In addition to the more than 30,00 0 logi ...

  • Xilinx ML310 - page 18

    18 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R Figure 2- 1: M L310 Board ...

  • Xilinx ML310 - page 19

    ML310 U ser Guide www .xilinx .com 19 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Overview R Figure 2-2 show s a high -lev el block diag ram of the ML31 0 and it s pe ripher als. Features In addition to the V i rtex-II Pro ™ FPGA with the embe dded PPC 405, the ML310 boar d featur es the following: • AT X M o t h e r b o a r d f o r m f a c ...

  • Xilinx ML310 - page 20

    20 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R ♦ 2 USB ports ♦ 2 IDE conne ctors ♦ GPIO ♦ SMBus Int erface ♦ AC97 Audio CODEC ♦ PS/2 keyboard and mou se ports • A TX power supply Board Hardware The ML310 V irtex-II Pro FPGA is connected to severa ...

  • Xilinx ML310 - page 21

    ML310 U ser Guide www .xilinx .com 21 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R II Pro FPGA I/O ca n be configured to use different IO standards such as SSTL2 a s required on the DDR DIMM interface. Pleas e review the ML3 10 V irtex-II Pro data sheet for mor e informatio n regarding I/O stan dards. Figure 2-3 shows the top-le ...

  • Xilinx ML310 - page 22

    22 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R DDR Signaling The FPGA DDR DIM M interface sup ports SSTL2 signa ling. All DDR sign als are controlled impedance and ar e SSTL2 terminated. DDR Memory Expansion The FPGA is ca pable of replicating up to three diff ...

  • Xilinx ML310 - page 23

    ML310 U ser Guide www .xilinx .com 23 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R ddr_ ad[2] AG 20 DDR_A 2 41 ddr_ ad[3] AF23 DDR_A 3 130 ddr_ad[ 4] AH22 DDR_A4 37 ddr_ ad[5] AF22 DDR_A 5 32 ddr_ ad[6] AF21 DDR_A 6 125 ddr_ad[ 7] AH21 DDR_A7 29 ddr_ ad[8] AG 21 DDR_A 8 122 ddr_ ad[9] AJ21 DDR_A 9 27 ddr_ ad[10] AK2 1 DDR_A 10 1 ...

  • Xilinx ML310 - page 24

    24 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R ddr_ dqs[5] M29 DDR_DQ S02 25 ddr_ dqs[6] H 29 DDR_DQ S01 14 ddr_ dqs[7] F29 DDR_DQ S00 5 ddr_ dq[0] AG 28 DDR_DQ 63 179 ddr_ dq[1] AG 26 DDR_DQ 62 178 ddr_ dq[2] AE 26 DDR_DQ 61 175 ddr_ dq[3] AD 26 DDR_DQ 60 174 ...

  • Xilinx ML310 - page 25

    ML310 U ser Guide www .xilinx .com 25 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R The connections fr om the FP GA to the DDR DIMM support either a r egistered or an unbuffer ed DIMM. The only differ ence from a connectivity perspective is that the ddr_ dq[32] N27 DD R_DQ31 133 ddr_ dq[33] P26 DD R_DQ30 131 ddr_ dq[34] R25 DDR_D ...

  • Xilinx ML310 - page 26

    26 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R unbuffer ed DIMM requir es more than one clock input pair versus a single clock input pair for a regi stere d D IMM . Ta b l e 2 - 2 shows optiona l clocking con nections that a re r equired for interf acing the F ...

  • Xilinx ML310 - page 27

    ML310 U ser Guide www .xilinx .com 27 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R a U A RT us a b l e w i t h a n y m em b e r of th e Vir t e x - I I P ro d e v i c e f a m il y . P l e a s e r e v i e w t h e E D K Pr ocessor IP Re fer ence Gui de for more details. The RS-232 port directly conn ected to the XC2VP30 is accessi ...

  • Xilinx ML310 - page 28

    28 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R Non-V olatile Storage In addition to programming the FPGA and s toring bitstreams, System A CE can be us ed for general use non-vola tile storage. System ACE provides an MPU interface for allowi ng a microprocesso ...

  • Xilinx ML310 - page 29

    ML310 U ser Guide www .xilinx .com 29 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R JT AG JT AG is a simple i n terface that provides fo r many uses. On the ML31 0 Har dware Platfo rm, the primary uses includ e configuratio n of the XC2VP30, de bugging sof tware (similar to the CPU debug interface) , and debuggin g hardware using ...

  • Xilinx ML310 - page 30

    30 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R Parallel Cable IV Interface The Parallel Cable IV (PC IV) download ca ble can also be used to pr ogram the XC2VP30. The pinout provided in Figur e 2 -7 is compatible with the PC IV JT AG programming solution. Figu ...

  • Xilinx ML310 - page 31

    ML310 U ser Guide www .xilinx .com 31 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R Figure 2 -8: LEDs and LCD Connectivity VCC3V3 SN74LVC244A 2Y1 2OE 2A2 2A3 2A4 2Y4 2Y3 2Y2 2A1 1Y1 VCCA 1OE 1A2 1A3 1A4 GND 1Y4 1Y3 1Y2 1A1 BUFFER NON-INVERTING LCD_RS LCD_E LCD_RW LED_DONE_BUF 9 19 13 15 17 3 5 7 11 18 20 1 4 6 8 10 12 14 16 2 U33 ...

  • Xilinx ML310 - page 32

    32 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R GPIO LED Interface All LEDs con nected to the GPIO lines ill uminate Green when dri ven with a lo gic zero and extinguish wi th a logic on e. Ta b l e 2 - 6 sh ows the conn ections for the GPIO LEDs from the FPGA ...

  • Xilinx ML310 - page 33

    ML310 U ser Guide www .xilinx .com 33 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R The three GPIO signals conf igured as outpu ts only are used as control signa ls that allow s the user to read/write the LCD character displa y in conjunctio n with the eight LCD data signals defined e arlier in Ta b l e 2 - 7 . Pl ease r eview th ...

  • Xilinx ML310 - page 34

    34 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R The PPC405 JT AG (Joint T est Action Group) Debug port complies with IEEE standard 1 149.1-19 9 0, IEEE Standa rd T est Access Port a n d Boundary Scan Ar chitecture. This standard describes a meth od for accessin ...

  • Xilinx ML310 - page 35

    ML310 U ser Guide www .xilinx .com 35 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R CPU Debug Connector Pinout Figure 2-10 shows J12, the 16 pin header used to debug the operation o f software in t he CPU. This is done usin g debug tools such as Paral lel Cable IV or third party tools. Refer to the PPC405 Pr ocessor Block Manual ...

  • Xilinx ML310 - page 36

    36 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R Arbiter IP . Please s ee the EDK Processor IP Ref erence Guide for mor e information about the EDK IP mention ed in this secti on. The FPGA is responsible generating the PC I RST signal a s well as the PCI CLK sig ...

  • Xilinx ML310 - page 37

    ML310 U ser Guide www .xilinx .com 37 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R Ta b l e 2 - 1 0 shows the con nections for the PCI controller . Figure 2 -1 1: PCI Bus and Device Co nnectivi ty T able 2-10: PCI Controller Connections UCF Signal Na me XC2VP30 Pin (U3 7) Descriptio n PCI_CL K0 T2 PCI_P_CLK0 PCI_CL K1 R2 PCI_P_C ...

  • Xilinx ML310 - page 38

    38 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R PCI_ IN T A L5 PCI Int errupt Sig nals PCI_ IN TB N2 PCI_ IN TC M2 PCI_ IN TD R9 PCI_ IN TE P9 PCI_ IN TF M3 PCI _REQ0_ N P1 PCI Request Signals PCI _REQ1_ N N1 PCI _REQ2_ N P7 PCI _REQ3_ N P8 PCI _REQ4_ N N3 PCI_ ...

  • Xilinx ML310 - page 39

    ML310 U ser Guide www .xilinx .com 39 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R PCI _AD[0] G 5 PCI Address/Data Lines PCI _AD[1] G 6 PCI _AD[2] D 5 PCI _AD[3] C5 PCI _AD[4] C1 PCI _AD[5] C2 PCI _AD[6] J 7 PCI _AD[7] J 8 PCI _AD[8] D 3 PCI _AD[9] C4 PCI _AD[10 ] D1 PCI _AD[1 1] D 2 PCI _AD[12 ] H5 PCI _AD[13 ] H6 PCI _AD[14 ] ...

  • Xilinx ML310 - page 40

    40 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R Ta b l e 2 - 1 1 describes how the Primary PCI Bus interrupts ar e connected on the ML310 boar d along with each devices IDSEL, REQ/GNT , PCI Clocks and DeviceID/V endor ID informatio n. Ta b l e 2 - 1 2 describes ...

  • Xilinx ML310 - page 41

    ML310 U ser Guide www .xilinx .com 41 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R ALi M1535D + supports the following featur es: ♦ 1 para llel and 2 seri al po rts ♦ 2 USB ports ♦ 2 IDE conne ctors ♦ GPIO ♦ SMBus Int erface ♦ AC97 Audio CODEC ♦ PS/2 keyboard and mouse Parallel Port Interface , connector assembly P ...

  • Xilinx ML310 - page 42

    42 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R Ta b l e 2 - 1 3 shows the ALi Parallel Port connection s to P1, DB25. Serial Port Interfa c e, connector assembly P1 In addition to the serial port accessible via the XC2VP3 0 FPGA, the ALi M1535D + provides acce ...

  • Xilinx ML310 - page 43

    ML310 U ser Guide www .xilinx .com 43 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R Ta b l e 2 - 1 4 shows the RS -232 signals con nected to the two DB9 connectors , P1 A/B. USB, connector assembly J3 The M1535D+ USB is an implementation of the Universal Serial Bus (US B) 1.0a specification th at contains tw o (2) PCI Host Co ntr ...

  • Xilinx ML310 - page 44

    44 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R IDE, connectors J15 and J16 Supports a 2-channel UltraDM A-133 IDE Master contr oller independently connected to a Primar y 40 Pin IDC conne ctor (J16) and a Secon dar y 40 Pi n IDC c onne ctor ( J15) . Ple ase re ...

  • Xilinx ML310 - page 45

    ML310 U ser Guide www .xilinx .com 45 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R GPIO, connector J5 There ar e 15 GPIO pins connecting the ALi M1535D+ to the J5 24 pin header . These ma y be accessed via the ALi M15 35D+ via the PCI Bus. Please re vi ew the ALi M1535 D+ Data she ets for more detail ed info rmatio n. Ta b l e 2 ...

  • Xilinx ML310 - page 46

    46 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R send byte/r eceive byte/ write byte/write word/r ead word/block read/block write command w ith clock synch ronization functi on as wel l as 10-b it addressing abilit y . Please see Section “ IIC/SMBus Interface ...

  • Xilinx ML310 - page 47

    ML310 U ser Guide www .xilinx .com 47 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R PS/2 Keyboard/Mouse Inter face, connector P2 The ALi M1535D + has a built-in PS2/A T Keyboard an d PS/2 Mouse cont roller . The PS/2 Keyboard a nd Mouse ports are co n nected to the ALi M1535D+ vi a standard D IN connectors contained in the P2 con ...

  • Xilinx ML310 - page 48

    48 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R Intel G D82559, U1 1, 10/1 00 Ethernet Controll er Intel GD82559 Ethernet Controller The GD82559 10 / 100 Mbps Fast Ethernet contr oller with an integrated 10/100 Mbps physical layer device for PCI boa rd LAN desi ...

  • Xilinx ML310 - page 49

    ML310 U ser Guide www .xilinx .com 49 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R review the G D 82559 Data s heet, located on the ML31 0 CDROM, for more detailed informatio n. IIC/SMBus Int erface Introduction to IIC/SMBus The Inter Integrated Circuit (IIC) bus provides the connectio n from the CPU to peripherals. It is a seri ...

  • Xilinx ML310 - page 50

    50 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R Ta b l e 2 - 2 2 shows th e FPGA conn ections to all SMBu s and IIC devices. T able 2-22: SMBus and IIC Controller Connections UCF Signal Name X C2VP30 Pin Schem S ignal Name iic_scl C13 fpga_scl iic_s da J15 fpga ...

  • Xilinx ML310 - page 51

    ML310 U ser Guide www .xilinx .com 51 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R Ta b l e 2 - 1 4 shows a block diagram of the FPGA in relation to the SMBus a ccelerator and the IIC bus. Note: Either the XC 2VP30 or the ALi M 1535D+ can m aster the I IC bus but not simultaneousl y Figu re 2-14 : SMBus and IIC Block Diagra m U3 ...

  • Xilinx ML310 - page 52

    52 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R Ta b l e 2 - 2 3 lists the IIC d evices and their a ssociated ad dresses. Serial Peripheral I nterface (SPI) In tr oduc tio n to SP I Serial Peripheral In terface ™ (SPI), is a serial interface much like the IIC ...

  • Xilinx ML310 - page 53

    ML310 U ser Guide www .xilinx .com 53 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R SPI Addressing The SPI does not use an addr essed based system like the IIC Bus Interface uses. Instead, devices are selected by dedicated Slave Select signals, compara ble to a Chip Select si gnal. Each SPI Slave device needs its own Slave Select ...

  • Xilinx ML310 - page 54

    54 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R CPU Reset, SW2 SW2 provides a way to manua lly reset the powerpc system implem ented in the XC2V P30. The user is responsible for connecting this signal to th e PPC405 system implem ented in the FPGA fabric. The E ...

  • Xilinx ML310 - page 55

    ML310 U ser Guide www .xilinx .com 55 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R SW3 = 0 0 0 (d efault ) Front Panel Interface Conne ctor , J23 The Fron t pan el Int erfa ce co nnec tor ( J23) is a 24 -pi n head er tha t acc epts a stan dard IDC 24 pin connector (0.1inch pitch). J23 pr ovides an optional means to contr o l and ...

  • Xilinx ML310 - page 56

    56 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R The front panel interface provides the followin g status info rmation avail able at the J23 heade r . ♦ FPGA Confi guration DO NE - Output intended for driving an LED ♦ IDE Disk access - Output intended for dr ...

  • Xilinx ML310 - page 57

    ML310 U ser Guide www .xilinx .com 57 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R Jumpers MGT VTRX T erminat ion V oltage Jumper s, J10 and J1 1 The MGT rece i ve termination voltage, VTRX, on the top a nd bottom MGT s ar e jumper selectabl e via jumpers J10 (top) and J1 1 (bottom). The on board r egulated VTRX termination volt ...

  • Xilinx ML310 - page 58

    58 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R MGT BREF Clock Sel ection Jumpers, J20 an d J21 One of two onboar d L VDS BREF clock sources, X7 o r X9, can be selected via jumpers, J20 and J21. The selected clock source drives both top an d bottom L VDS BREF C ...

  • Xilinx ML310 - page 59

    ML310 U ser Guide www .xilinx .com 59 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 Board Hardware R Note: An Antec, model SL250 S, A TX Power Supply is delivered wi th your ML310. The Antec Us er ’ s Manual is provided in the Data sheets section on the ML310 CDROM. Prior to installation please read the Inst allation sectio n of the Antec User ...

  • Xilinx ML310 - page 60

    60 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R In addition to the MC34161D vo ltage monitors, th e ML310 employs a SMBus dev ice, LM87, whi ch samp les several of the same supply volta ges when acce ssed ove r the Syst em Managemen t Bus or SMBus. More informa ...

  • Xilinx ML310 - page 61

    ML310 U ser Guide www .xilinx .com 61 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 High-Speed I/O R Ta b l e 2 - 2 8 Shows the various V oltage monitor inform ation. High-Speed I/O Xilinx V irtex-II Pro FPGAs offer a variety of high-speed I/O solutions. The ML3 10 Embedded Development Pl atform ’ s h igh-speed I/O is based on the XC2V P30-FF8 ...

  • Xilinx ML310 - page 62

    62 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R ML310 PM Connect ors The ML310 PM connectors ar e T yco Z-Dok+ connectors, part number 1367550-5. The "-5" suffix indicates a 40 pai r connector . Each connector ha s 40 differential pairs and severa l p ...

  • Xilinx ML310 - page 63

    ML310 U ser Guide www .xilinx .com 63 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 High-Speed I/O R Figure 2-20 shows an edge view of the PM host boar d connectors on the ML310 board . Each s ignal pair on t he PM1 a nd PM2 ho st bo ard conn ect ors has a wide ground pin on t he opposite s ide of the plastic divider , as shown in Figure 2-21 . T ...

  • Xilinx ML310 - page 64

    64 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R • 1 single-en ded clock at 2.5V • 1 pin no t connec ted Adapter Board P M Connectors T yco Z-Dok+ ad apter boar d connectors, par t number 136755 5-1 ar e the rec ept acle connectors on the perso nality module ...

  • Xilinx ML310 - page 65

    ML310 U ser Guide www .xilinx .com 65 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 High-Speed I/O R PM1 Power and Grou nd Ta b l e 2 - 2 9 shows the power and gro und pins for the PM1 connector on the ML310. PM2 Power and Grou nd Ta b l e 2 - 3 0 shows the power and gro und pins for the PM2 connector on the ML310. ML310 PM User I /O Pins PM1 Use ...

  • Xilinx ML310 - page 66

    66 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R A1 1 H16 IO_L69P_0 PM_IO_82 2.5V A12 J16 IO_L69N_0 PM_IO_ 83 2. 5V A13 A25 RXPP AD4 RX PP AD4_A 25 A14 A24 RXNP AD4 RXNP AD4_A24 A15 A12 RXPP AD7 RX PP AD7_A 12 A16 A 1 1 RXNP AD7 RXNP AD7_ A1 1 A17 AK 6 TXPP AD16 ...

  • Xilinx ML310 - page 67

    ML310 U ser Guide www .xilinx .com 67 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 High-Speed I/O R D4 G25 IO_L02N _7 PM_IO_85 2.5V D5 A8 IO_L 44N_1 P M_IO_3 V_21 3V D6 B8 IO_L4 4P_1 PM_ IO_3V_2 0 3V D7 D7 IO_L08P_1 P M_IO_3V_8 3V D8 F9 IO_L07P_1 P M_IO_3V_6 3V D9 E8 IO_L 03P_1 P M_IO_3V_2 3V D10 D8 IO_L38 P_1 PM _IO_ 3V_14 3V D1 1 D17 IO_L6 7P_ ...

  • Xilinx ML310 - page 68

    68 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R ML310 PM2 User I/O The PM2 connector makes most of the L VDS pairs available to the user , along with single- ended signal s. Ta b l e 2 - 3 2 shows th e pinout for the PM2 connecto r on the ML310. F17 AK1 1 RXNP ...

  • Xilinx ML310 - page 69

    ML310 U ser Guide www .xilinx .com 69 UG068 (v 1.01) August 25, 2 004 1-800-255-7 778 High-Speed I/O R C1 W1 IO_L57N_3 PM_IO_53 2.5 V C2 Y1 IO_L57P_3 PM_IO_52 2.5 V C3 U4 IO_L85N_3 PM_IO_61 2.5 V C4 U5 IO_L85P_3 PM_IO_60 2.5 V C5 W5 IO_L50N_3 PM_IO_39 2.5 V C6 W6 IO_L50P_3 PM_IO_38 2.5 V C7 V5 IO_L55N_3 PM_IO_49 2.5 V C8 V6 IO_L55P_3 PM_IO_48 2.5 V ...

  • Xilinx ML310 - page 70

    70 www .xilinx .com ML310 U ser Guid e 1-800-255-7 778 UG068 (v1.01) Augu st 25, 2004 Chapter 2: ML310 Embedded De v elopment Platform R D14 AA5 IO_L44N_ 3 PM_I O_27 2.5 V D15 AC4 IO_L43P_ 3 PM_I O_24 2.5 V D16 AC3 IO_L43N_ 3 PM_I O_25 2.5 V D17 AE4 IO_L3 3P_3 PM_IO _10 2.5V D18 AE3 IO_L3 3N_3 PM_IO _1 1 2.5V D19 AF4 IO_L3 4P_3 PM_IO_ 12 2.5V D20 A ...

Manufacturer Xilinx Category Computer Hardware

Documents that we receive from a manufacturer of a Xilinx ML310 can be divided into several groups. They are, among others:
- Xilinx technical drawings
- ML310 manuals
- Xilinx product data sheets
- information booklets
- or energy labels Xilinx ML310
All of them are important, but the most important information from the point of view of use of the device are in the user manual Xilinx ML310.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Xilinx ML310, service manual, brief instructions and user manuals Xilinx ML310. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Xilinx ML310.

Similar manuals

A complete manual for the device Xilinx ML310, how should it look like?
A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Xilinx ML310 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Xilinx ML310.

A complete Xilinx manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

1. Preface and tips on how to use the manual Xilinx ML310 - At the beginning of each manual we should find clues about how to use the guidelines. It should include information about the location of the Contents of the Xilinx ML310, FAQ or common problems, i.e. places that are most often searched by users in each manual
2. Contents - index of all tips concerning the Xilinx ML310, that we can find in the current document
3. Tips how to use the basic functions of the device Xilinx ML310 - which should help us in our first steps of using Xilinx ML310
4. Troubleshooting - systematic sequence of activities that will help us diagnose and subsequently solve the most important problems with Xilinx ML310
5. FAQ - Frequently Asked Questions
6. Contact detailsInformation about where to look for contact to the manufacturer/service of Xilinx ML310 in a specific country, if it was not possible to solve the problem on our own.

Do you have a question concerning Xilinx ML310?

Use the form below

If you did not solve your problem by using a manual Xilinx ML310, ask a question using the form below. If a user had a similar problem with Xilinx ML310 it is likely that he will want to share the way to solve it.

Copy the text from the picture

Captcha
New picture

Comments (0)