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Manual Intel UPI-C42

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  • Intel UPI-C42 - page 1

    * Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. ...

  • Intel UPI-C42 - page 2

    UPI-C42/UPI-L42 Table 1. Pin Description DIP PLCC QFP Symbol Pin Pin Pin Type Name and Function No. No. No. TEST 0, 1 2 18 I TEST INPUTS: Input pins which can be directly tested using conditional branch instructions. TEST 1 39 43 16 FREQUENCY REFERENCE: TEST 1 (T 1 ) functions as the event timer input (under software control). TEST 0 (T 0 ) is a mu ...

  • Intel UPI-C42 - page 3

    UPI-C42/UPI-L42 Table 1. Pin Description (Continued) DIP PLCC QFP Symbol Pin Pin Pin Type Name and Function No. No. No. P 20 –P 27 2 1–2 4 2 4–2 7 3 9–4 2 I / O PORT 2: 8-bit, PORT 2 quasi-bidirectional I/O lines. The lower 4 bits (P 20 –P 23 ) interface directly to the 8243 I/O expander device and 3 5–3 8 3 9–4 2 1 1 , 1 3–1 5 cont ...

  • Intel UPI-C42 - page 4

    UPI-C42/UPI-L42 UPI-C42/L42 PRODUCT SELECTION GUIDE UPI-C42: Low power CHMOS version of the UPI-42. Device Package ROM OTP Comments 80C42 N, P S 4K ROM Device 82C42PC N, P, S Phoenix MultiKey/42 firmware, PS/2 style mouse support 82C42PD N, P, S Phoenix MultiKey/42L firmware, KBC and SCC for portable apps. 82C42PE N, P, S Phoenix MultiKey/42G firmw ...

  • Intel UPI-C42 - page 5

    UPI-C42/UPI-L42 UPI-42 COMPATIBLE FEATURES 1. Two Data Bus Buffers, one for input and one for output. This allows a much cleaner Master/Slave protocol. 290414 – 5 2. 8 Bits of Status ST 7 ST 6 ST 5 ST 4 F 1 F 0 IBF OBF D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 ST 4 –S T 7 are user definable status bits. These bits are defined by the ‘‘MOV STS, A’? ...

  • Intel UPI-C42 - page 6

    UPI-C42/UPI-L42 If ‘‘EN DMA’’ has been executed, P 27 becomes the DACK (DMA ACKnowledge) pin. This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers. EN DMA Op Code: 0E5H 1 110010 1 D 7 D 0 6. When EA is enabled on the UPI, the program counter is placed on Port 1 and the lower four bits of Port 2 (MSB e ...

  • Intel UPI-C42 - page 7

    UPI-C42/UPI-L42 thereby providing additional user programmable memory space. This feature is enabled by the A20EN instruction and remains enabled until the de- vice is reset. It is important to note that the execu- tion of the A20EN instruction redefines Port 2, bit 1 as a pure output pin with read only characteristics. The state of this pin can be ...

  • Intel UPI-C42 - page 8

    UPI-C42/UPI-L42 Table 2 covers all suspend mode pin states. In addi- tion to the suspend power down mode, the UPI-C42 will also support the NMOS power down mode as outlined in Chapter 4 of the UPI-42AH users manual. Table 2. Suspend Mode Pin States Pins Suspend Ports 1 and 2 Outputs Tristate Inputs Weak Pull-Up Disabled DBB (1) Outputs Normal Input ...

  • Intel UPI-C42 - page 9

    UPI-C42/UPI-L42 This circuitry gives the host direct control of port 2 bit 1 (P2.1) without intervention by the internal CPU. When this opcode is executed, P2.1 becomes a ded- icated output pin. The status of this pin is read-able but can only be altered through a valid ‘‘D1’’ com- mand sequence (see Table 1). SUSPEND Invoke Suspend Power D ...

  • Intel UPI-C42 - page 10

    UPI-C42/UPI-L42 290414 – 14 Figure 6. Quick-Pulse Programming Algorithm Quick-Pulse Programming Algorithm As previously stated, the UPI-C42 will be pro- grammed using the Quick-Pulse Programming Algo- rithm, developed by Intel to substantially reduce the thorughput time in production programming. The Quick-Pulse Programming Algorithm uses initial ...

  • Intel UPI-C42 - page 11

    UPI-C42/UPI-L42 b. Apply access code to appropriate inputs to put the device into security mode. c. Apply high voltage to EA and V DD pins. d. Follow the programming procedure as per the Quick-Pulse Programming Algorithm with known data on the databus. Not only the security bit, but also the security byte of the signature row is pro- grammed. e. Ve ...

  • Intel UPI-C42 - page 12

    UPI-C42/UPI-L42 Table 3. Signature Mode Table Address Device No. of Type Bytes Test Code/Checksum 0 0FH ROM/OTP 25 16H 1EH Intel Signature 10H 11H ROM/OTP 2 User Signature 12H 13H OTP 2 Test Signature 14H 15H ROM/OTP 2 Security Byte 1FH or 3FH ROM/OTP 2 UPI-C42 Intel Signature 20H 21H ROM/OTP 2 User Defined UPI-C42 OTP EPROM Space 22H 3EH ROM/OTP 3 ...

  • Intel UPI-C42 - page 13

    UPI-C42/UPI-L42 SYNC MODE TIMING DIAGRAMS 290414 – 15 Minimum Specifications SYNC Operation Time, t SYNC e 3.5 XTAL 2 Clock cycles. Reset Time, t RS e 4t CY . NOTE: The rising and falling edges of T0 should occur during low state of XTAL 2 clock. APPLICATIONS 290414 – 12 Figure 7. UPI-C42 Keyboard Controller 290414 – 9 Figure 8. 8088-UPI-C42 ...

  • Intel UPI-C42 - page 14

    UPI-C42/UPI-L42 APPLICATIONS (Continued) 290414 – 10 Figure 9. 8048H-UPI-C42 Interface 290414 – 11 Figure 10. UPI-C42-8243 Keyboard Scanner 290414 – 13 Figure 11. UPI-C42 80-Column Matrix Printer Interface 14 ...

  • Intel UPI-C42 - page 15

    UPI-C42/UPI-L42 ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias ÀÀÀÀ0 § Ct o a 70 § C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65 § Ct o a 150 § C Voltage on Any Pin with Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 7V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5 W NOTICE: This is a produ ...

  • Intel UPI-C42 - page 16

    UPI-C42/UPI-L42 DC CHARACTERISTICS T A e 0 § Ct o a 70 § C, V CC e V DD ea 5V g 10%; a 3.3V g 10% UPI-L42 (Continued) Symbol Parameter UPI-C42 UPI-L42 Units Notes Min Max Min Max I CC a I DD Total Supply Current: Active Mode @ 12.5 MHz 30 20 mA Typical 14 mA UPI-C42, 9 mA UPI-L42 Suspend Mode 40 26 m A Osc. Off (1, 4) I DD Standby Power Down 5 3. ...

  • Intel UPI-C42 - page 17

    UPI-C42/UPI-L42 AC CHARACTERISTICS T A e 0 § Ct o a 70 § C, V SS e 0V, V CC e V DD ea 5V g 10%; a 3.3V g 10% for the UPI-L42 NOTE: All AC Characteristics apply to both the UPI-C42 and UPI-L42 DBB READ Symbol Parameter Min Max Units t AR CS, A 0 Setup to RD v 0n s t RA CS, A 0 Hold After RD u 0n s t RR RD Pulse Width 160 ns t AD CS, A 0 to Data Ou ...

  • Intel UPI-C42 - page 18

    UPI-C42/UPI-L42 AC CHARACTERISTICS T A e 0 § Ct o a 70 § C, V SS e 0V, V CC e V DD ea 5V g 10%; a 3.3V g 10% for the UPI-L42 (Continued) CLOCK Symbol Parameter Min Max Units t CY UPI-C42/UPI-L42 Cycle Time 1.2 9.20 m s (1) t CYC UPI-C42/UPI-L42 Clock Period 80 613 ns t PWH Clock High Time 30 ns t PWL Clock Low Time 30 ns t R Clock Rise Time 10 ns ...

  • Intel UPI-C42 - page 19

    UPI-C42/UPI-L42 AC CHARACTERISTICSÐPROGRAMMING (UPI-C42 AND UPI-L42) T A e 25 § C g 5 § C, V CC e 6.25V g 0.25V, V DDL ea 5V g 0.25V, V DDH e 12.75V g 0.25V (87C42/87L42 ONLY) Symbol Parameter Min Max Units t AW Address Setup Time to RESET u 4t CY t WA Address Hold Time after RESET u 4t CY t DW Data in Setup Time to PROG v 4t CY t WD Data in Hol ...

  • Intel UPI-C42 - page 20

    UPI-C42/UPI-L42 DRIVING FROM AN EXTERNAL SOURCE 290414 – 18 NOTE: See XTAL1 Configuration Table. 290414 – 19 Rise and Fall Times Should Not Exceed 10 ns. Resistors to V CC are Needed to Ensure V IH e 3.5V if TTL Circuitry is Used. LC OSCILLATOR MODE L C NOMINAL f e 1 2 q 0 LC Ê 45 H 20 pF 5.2 MHz 120 H 20 pF 3.2 MHz C Ê e C a 3Cpp 2 Cpp j 5? ...

  • Intel UPI-C42 - page 21

    UPI-C42/UPI-L42 WAVEFORMS READ OPERATIONÐDATA BUS BUFFER REGISTER 290414 – 22 WRITE OPERATIONÐDATA BUS BUFFER REGISTER 290414 – 23 CLOCK TIMING 290414 – 24 21 ...

  • Intel UPI-C42 - page 22

    UPI-C42/UPI-L42 WAVEFORMS (Continued) COMBINATION PROGRAM/VERIFY MODE 290414 – 25 NOTES: 1. A 0 must be held low (0V) during program/verify modes. 2. For V IH ,V IH1 ,V IL ,V IL1 ,V DDH , and V DDL , please consult the D.C. Characteristics Table. 3. When programming the 87C42, a 0.1 m F capacitor is required across V DD and ground to suppress spu ...

  • Intel UPI-C42 - page 23

    UPI-C42/UPI-L42 WAVEFORMS (Continued) DMA 290414 – 27 PORT 2 290414 – 28 PORT TIMING DURING EXTERNAL ACCESS (EA) 290414 – 29 On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed. On the Trailing Edge of Sync the Program Counter Contents are Available. 23 ...

  • Intel UPI-C42 - page 24

    UPI-C42/UPI-L42 Table 4. UPI Instruction Set Mnemonic Description Bytes Cycles ACCUMULATOR ADD A, Rr Add register to A 1 1 ADD A, @ Rr Add data memory 1 1 to A ADD A, Ý data Add immediate to A 2 2 ADDC A, Rr Add register to A 1 1 with carry ADDC A, @ Rr Add data memory 1 1 to A with carry ADDC A, Ý data Add immediate 2 2 to A with carry ANL A, Rr ...

  • Intel UPI-C42 - page 25

    UPI-C42/UPI-L42 Table 4. UPI Instruction Set (Continued) Mnemonic Description Bytes Cycles CONTROL (Continued) * SUSPEND Invoke Suspend Power- 1 2 down mode NOP No Operation 1 1 REGISTERS INC Rr Increment register 1 1 INC @ Rr Increment data 1 1 memory DEC Rr Decrement register 1 1 SUBROUTINE CALL addr Jump to subroutine 2 2 RET Return 1 2 RETR Ret ...

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