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Manual Intel 324632-003

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  • Intel 324632-003 - page 1

    324632-003 Revision: 2.1 January 2011 Intel ® 82575EB Gigabit Ethernet Controller Software Developer’s Manual and EEPROM Guide LAN Access Division ...

  • Intel 324632-003 - page 2

    Intel ® 82575EB Gigabit Ethernet Controller — Legal Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 2 January 2011 Legal INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL P ...

  • Intel 324632-003 - page 3

    Revisions — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 3 Revisions Revision Date Description .25 2/2006 Initial release (Intel Secret). 1.1 1/2008 • Updated Section 13.4.8.15 (bit 15 description). • Updated Table ...

  • Intel 324632-003 - page 4

    Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 4 January 2011 Content 1.0 Introduction ........................................................................................................................... 19 1.1 Regis ...

  • Intel 324632-003 - page 5

    Content — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 5 4.2 Flash Interface Operation ................................................................................................... ........ 49 4.2.1 Flash Write C ...

  • Intel 324632-003 - page 6

    Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 6 January 2011 4.6.1.4 SMBus Slave Addresses - (0ffset 03h).............................................................................. 81 4.6.1.5 SMBus Fail-Over Register (L ...

  • Intel 324632-003 - page 7

    Content — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 7 4.6.7.30 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 47h) .................................................................. 97 4.6.7.31 LAN0 IPv6 Address 0 MSB; MIPA ...

  • Intel 324632-003 - page 8

    Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 8 January 2011 5.5 Header Splitting and Replication ................................................................................................ 127 5.5.1 Receive Packet Ch ...

  • Intel 324632-003 - page 9

    Content — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 9 5.13.8 Extended Interrupt Mask Set and Read Register (EIMS)/Extended Interrupt Mask Clear Register (EIMC) 164 5.13.9 Extended Interrupt Auto Clear Enable Registe ...

  • Intel 324632-003 - page 10

    Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 10 January 2011 6.6.5.3.2 Advanced Error Reporting Capability ............................................................................ 211 6.6.5.3.3 Device Serial Number .. ...

  • Intel 324632-003 - page 11

    Content — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 11 9.0 Ethernet Interface ................................................................................................................ 241 9.1 Internal MAC/PHY ...

  • Intel 324632-003 - page 12

    Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 12 January 2011 11.3 Link Criteria ............................................................................................................................ 267 11.3.1 1000B ...

  • Intel 324632-003 - page 13

    Content — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 13 14.1.1 Memory and I/O Address Decoding .......................................................................................289 14.1.1.1 Memory-Mapped Access ...

  • Intel 324632-003 - page 14

    Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 14 January 2011 14.3.26 Manageability Flash Control Register - FLMNGCTL (1018h; R/W) .............................................. 336 14.3.27 Manageability Flash Read Data - ...

  • Intel 324632-003 - page 15

    Content — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 15 14.4.2 Tx DCA Control Registers - TXCTL (03814h + 100h *n [n=0..3]; R/W) ......................................378 14.5 Filter Registers ....................... ...

  • Intel 324632-003 - page 16

    Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 16 January 2011 14.8.23 MSI-X PBA Clear - PBACL (05B68h; R/W1C).......................................................................... 415 14.8.24 DCA Requester ID Informati ...

  • Intel 324632-003 - page 17

    Content — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 17 14.9.57 SerDes/SGMII Code Violation Packet Count - SCVPC (04228h; R/WS) ....................................... 432 14.10 Diagnostics Registers ................ ...

  • Intel 324632-003 - page 18

    Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 18 January 2011 NOTE: This page intentionally left blank. ...

  • Intel 324632-003 - page 19

    Introduction — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 19 1.0 Introduction This document describes the external architecture (including device operation, register definitions, etc.) for the 82575, a Gigabit Ethern ...

  • Intel 324632-003 - page 20

    Intel ® 82575EB Gigabit Ethernet Controller — Memory Alignment Terminology Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 20 January 2011 • PCI Express* Card Electromechanical Specification, Rev 1.1RD, November 2004 • PICMG3.1 Ethernet/Fiber Channel Over PICMG 3.0 Draft Sp ...

  • Intel 324632-003 - page 21

    Architectural Overview — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 21 2.0 Architectural Overview This section provides an overview of the 82575 . The following sections give detailed information about the 82575’s ...

  • Intel 324632-003 - page 22

    Intel ® 82575EB Gigabit Ethernet Controller — Integrated 10/100/1000 Mb/s PHY Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 22 January 2011 Figure 1. 82575 External Interfaces 2.1.1 Integrated 10/100/1000 Mb/s PHY The 82575 contains integrated 10/100/1000 Mb/s-capable Copper ...

  • Intel 324632-003 - page 23

    Flash Memory Interface — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 23 2.1.4 Flash Memory Interface The 82575 provides an external serial interface to a FLASH device. Accesses to the FLASH are controlled by the 82575 ...

  • Intel 324632-003 - page 24

    Intel ® 82575EB Gigabit Ethernet Controller — LEDs Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 24 January 2011 the four pins is configurable via EEPROM as well as the default value of any pins configured as outputs. To avoid signal contention, all four pins are set as input ...

  • Intel 324632-003 - page 25

    Ethernet Addressing — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 25 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e Example 1. Byte Ordering There are no alignment restrictio ...

  • Intel 324632-003 - page 26

    Intel ® 82575EB Gigabit Ethernet Controller — Interrupt Control and Tuning Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 26 January 2011 Table 2. Intel® Architecture Byte Ordering Note: The notation in this manual follows the convention shown in Table 2 . For example, the ad ...

  • Intel 324632-003 - page 27

    Jumbo Frame Support — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 27 2.5.1 Jumbo Frame Support The 82575 supports jumbo frames to increase performance and decrease CPU utilization. By default, the 82575 might receive ...

  • Intel 324632-003 - page 28

    Intel ® 82575EB Gigabit Ethernet Controller — Multiple Transmit Queues Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 28 January 2011 The software gives the hardware ownership of a queue of buffers for receives. These receive buffers store data that the software then owns once ...

  • Intel 324632-003 - page 29

    General Initialization and Reset Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 29 3.0 General Initialization and Reset Operation This section lists all necessary initializations and describes the reset comma ...

  • Intel 324632-003 - page 30

    Intel ® 82575EB Gigabit Ethernet Controller — Global Reset and General Configuration Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 30 January 2011 After the initialization completes, a typical driver enables the desired interrupts by writing to the IMS and EIMS registers. 3.4 ...

  • Intel 324632-003 - page 31

    Initialize the Receive Control Register — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 31 • Enable the queue by setting RXDCTL.ENABLE. In the case of queue zero, the enable bit is set by default, as such, the ring pa ...

  • Intel 324632-003 - page 32

    Intel ® 82575EB Gigabit Ethernet Controller — Dynamic Queue Enabling and Disabling Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 32 January 2011 • Set the length register to the size of the descriptor ring. • Program the TXDCTL register with the desired TX descriptor writ ...

  • Intel 324632-003 - page 33

    MAC/PHY Link Setup (CTRL_EXT.LINK_MODE = 00b) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 33 CTRL.FD - Don't care; duplex setting is established from PHY's internal indication to the MAC (FDX) after PHY ha ...

  • Intel 324632-003 - page 34

    Intel ® 82575EB Gigabit Ethernet Controller — MAC/SerDes Link Setup (CTRL_EXT.LINK_MODE = 11b) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 34 January 2011 STATUS.FD - Reflects the MAC duplex setting written by software to CTRL.FD STATUS.LU - Reflects 1b. (positive link indi ...

  • Intel 324632-003 - page 35

    MAC/SGMII Link Setup (CTRL_EXT.LINK_MODE = 10b) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 35 STATUS.FD - Reflects the value written by software to CTRL.FD STATUS.LU - Reflects whether loss-of-signal (LOS) from Ser ...

  • Intel 324632-003 - page 36

    Intel ® 82575EB Gigabit Ethernet Controller — MAC/SGMII Link Setup (CTRL_EXT.LINK_MODE = 10b) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 36 January 2011 • Hardware Auto-Negotiation Enabled (PCS_LCTL. AN ENABLE = 1b, CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b) CTRL.FD - Ignored; ...

  • Intel 324632-003 - page 37

    Reset Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 37 PCS_LCTL.FDV - Should be set by software to the duplex value established via software priority resolution PCS_LCTL.FLV - Should be set by software to 1b ...

  • Intel 324632-003 - page 38

    Intel ® 82575EB Gigabit Ethernet Controller — Reset Operation Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 38 January 2011 D3hot to D0 Transition: This is also known as ACPI Reset. The 82575 generates an internal reset on the transition from D3hot power state to D0 (caused a ...

  • Intel 324632-003 - page 39

    Reset Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 39 Table 3. 82575 Reset Effects Notes: 1. If AUX_POWER = 0b the Wakeup Context is reset (PME_Status and PME_En bits should be 0b at reset if the 82575 does ...

  • Intel 324632-003 - page 40

    Intel ® 82575EB Gigabit Ethernet Controller — Reset Operation Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 40 January 2011 a. SDP0_IODIR, SDP1_IODIR, SDP2_IODIR, SDP3_IODIR - reset on Internal_Power_On_Reset only. Any EEPROM auto-load resets these fields to the values in the ...

  • Intel 324632-003 - page 41

    PHY Behavior During a Manageability Session: — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 41 b. IP Address Valid. c. IPv4 Address Table d. IPv6 Address Table e. Flexible Filter Length Table f. Flexible Filter Mask Ta ...

  • Intel 324632-003 - page 42

    Intel ® 82575EB Gigabit Ethernet Controller — Initialization of Statistics Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 42 January 2011 The Keep_PHY_Link_Up bit is set by the BMC through a command on the sideband interface. It is cleared by the external BMC (again, through a ...

  • Intel 324632-003 - page 43

    EEPROM and Flash Interface — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 43 4.0 EEPROM and Flash Interface This section describes the EEPROM and Flash interfaces supported by 82575. 4.1 EEPROM Device The 82575 uses an ...

  • Intel 324632-003 - page 44

    Intel ® 82575EB Gigabit Ethernet Controller — Signature and CRC Fields Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 44 January 2011 Software can use the EEPROM Read register (EERD) to cause the 82575 to read a word from the EEPROM that the software can then use. To do this, ...

  • Intel 324632-003 - page 45

    Protected EEPROM Space — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 45 This mechanism uses an SMBus message that the firmware is able to receive in all modes, no matter what the content of the EEPROM is (even in diag ...

  • Intel 324632-003 - page 46

    Intel ® 82575EB Gigabit Ethernet Controller — Activating the Protection Mechanism Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 46 January 2011 sequence, the 82575 reads the hardware initialization words in the EEPROM. If the signature in word 12h does not equal 01b the EEPRO ...

  • Intel 324632-003 - page 47

    EEPROM-Less Support — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 47 s32 is signed 32 bit value, u8 is unsigned 8 bit value. #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ #define E1000_GIOCTL 0x05B44 /* GIO ...

  • Intel 324632-003 - page 48

    Intel ® 82575EB Gigabit Ethernet Controller — EEPROM-Less Support Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 48 January 2011 e1000_write_8bit_ctrl_reg(E1000_GIOCTL, 0x2F, 0x81); /* PCIe PLL Configuration */ e1000_write_8bit_ctrl_reg(E1000_SCCTL, 0x02, 0x47); e1000_write_8b ...

  • Intel 324632-003 - page 49

    Flash Interface Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 49 /* Poll the ready bit to see if the MDI read completed */ for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { usec_delay(5); regvalue = E1000_RE ...

  • Intel 324632-003 - page 50

    Intel ® 82575EB Gigabit Ethernet Controller — Flash Write Control Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 50 January 2011 To directly access the Flash, software needs to: 1. Write a 1b to the Flash Request bit (FLA.FL_REQ) 2. Read the Flash Grant bit (FLA.FL_GNT) until ...

  • Intel 324632-003 - page 51

    EEPROM Map Shared Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 51 • Hardware auto read. • Accesses of port 0 LAN driver. • Accesses of port 1 LAN driver. • Firmware accesses. All clients can access the ...

  • Intel 324632-003 - page 52

    Intel ® 82575EB Gigabit Ethernet Controller — Flash Access Contention Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 52 January 2011 4.4.1 Flash Access Contention The 82575 implements internal arbitration between Flash accesses initiated through the LAN 0 device and those init ...

  • Intel 324632-003 - page 53

    EEPROM Map — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 53 09h SW PBA Byte 3 PBA Byte 4 0Ah HW Initialization Control 1 All 0Bh HW Subsystem ID Both 0Ch HW Subsystem Vendor ID All 0Dh HW Device ID LAN 0 0Eh HW Reserv ...

  • Intel 324632-003 - page 54

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 54 January 2011 4.5.1 Hardware Accessed Words This section describes the EEPROM words that are loaded by the 82575 hardware. Most of these bits are located in c ...

  • Intel 324632-003 - page 55

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 55 Table 5. EEPROM Auto-Load Sequence Full Reset Reset of LAN0 Only Reset of LAN1 Only Comments 012 012 012 00A 00A 00A 018 019 01A 01B 026 027 028 ...

  • Intel 324632-003 - page 56

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 56 January 2011 4.5.1.1 Ethernet Address (Words 00h – 02h) The Ethernet Individual Address (IA) is a 6-byte field that must be unique for each Ethernet port a ...

  • Intel 324632-003 - page 57

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 57 4.5.1.3 Subsystem ID (Word 0Bh) If the Load Subsystem IDs bit in the Initialization Control Word 1 (0Ah) is set, this word is used to initialize ...

  • Intel 324632-003 - page 58

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 58 January 2011 • Set defaults for some internal registers. • Enable and disable specific features. Table 7. Initialization Control 2 (Word 0Fh) Bit(s) Name ...

  • Intel 324632-003 - page 59

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 59 4.5.1.8 Software Defined Pins Control (Word 10h) This word configures initial settings for the Software Definable Pins. Note: Word 10h is for LA ...

  • Intel 324632-003 - page 60

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 60 January 2011 4.5.1.9 EEPROM Sizing & Protected Fields (Word 12h) Provides common power consumption and other indications about EEPROM size and protection ...

  • Intel 324632-003 - page 61

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 61 4.5.1.10 Initialization Control 3 (Word 14h, 24h) This word controls general initialization values. Word 14h is used for LAN1. Word 24 is used f ...

  • Intel 324632-003 - page 62

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 62 January 2011 Table 10. Initialization Control 3 (Word 14h and 24h High Byte) Bit(s) Name Default Description 15 SerDes Energy Source 0b SerDes Energy Source ...

  • Intel 324632-003 - page 63

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 63 The description of bits 13 and 11 in various combinations are as follows: 4.5.1.11 NC-SI and PCIe* Completion Timeout Configuration (Word 15h) F ...

  • Intel 324632-003 - page 64

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 64 January 2011 4.5.1.12 MSI-X Configuration (Word 16h) 4.5.1.13 PLL/Lane/PHY Initialization Pointer (Word 17h) 4.5.1.14 PCIe* Initialization Configuration 1 (W ...

  • Intel 324632-003 - page 65

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 65 4.5.1.16 Software Defined Pins Control (Word 20h) This configures initial settings for the Software Definable Pins. Note: Word 20h is for LAN0. ...

  • Intel 324632-003 - page 66

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 66 January 2011 4.5.1.17 PCIe* Initialization Configuration 3 (Word 1Ah) This word sets default values for some internal registers. 8 SDPDIR[0] 0b SDP0 Pin - In ...

  • Intel 324632-003 - page 67

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 67 Table 16. PCIe* Initialization Configuration 3 (Word 1Ah) Bit(s) Name Default Description 15 Master Enable 1b When this bit is set to 1b, the PH ...

  • Intel 324632-003 - page 68

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 68 January 2011 4.5.1.18 PCIe* Control (Word 1Bh) This word configures initial settings for the PCIe* default functionality. 3:2 Active State PM Support 11b Thi ...

  • Intel 324632-003 - page 69

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 69 4.5.1.19 LED 1, 3 Configuration Defaults (Word 1Ch) This EEPROM word specifies the hardware defaults for the LEDCTL register fields controlling ...

  • Intel 324632-003 - page 70

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 70 January 2011 Table 19. LED Mode 4.5.1.20 Device Revision ID (Word 1Eh) 4.5.1.21 LED 0, 2 Configuration Defaults (Word 1Fh) This EEPROM word specifies the har ...

  • Intel 324632-003 - page 71

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 71 (LINK_UP) and LED2 (LINK_100) output behaviors Note: A value of 0602h is used to configure default hardware LED behavior equivalent to 82544- ba ...

  • Intel 324632-003 - page 72

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 72 January 2011 4.5.1.22 Functions Control (Word 21h) 4.5.1.23 LAN Power Consumption (Word 22h) This word is meaningful only if the EEPROM signature in word 0Ah ...

  • Intel 324632-003 - page 73

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 73 6 CRC_DIS PHY / SERDES / PCIe* CRC disable. 0b = Enable. 1b = Disable. 5 LAN1_ROM_DIS LAN1 ROM Disable Disables PHY and SerDes ROM configuration ...

  • Intel 324632-003 - page 74

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 74 January 2011 4.5.1.25 End of RO Area (Word 2Ch 4.5.1.26 Start of RO Area (Word 2Dh) 4.5.1.27 Watchdog Configuration (Word 2Eh) 4.5.1.28 VPD Pointer (Word 2Fh ...

  • Intel 324632-003 - page 75

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 75 The main setup options are stored in word 30h. These options are those that can be changed by the user via the Control-S setup menu. Word 30h ha ...

  • Intel 324632-003 - page 76

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 76 January 2011 4.5.1.29.2 Configuration Customization Options PCI Function 0 (Word 31h) Word 31h of the EEPROM contains settings that can be programmed by an O ...

  • Intel 324632-003 - page 77

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 77 4.5.1.29.3 PXE Version (Word 32h) Word 32h of the EEPROM is used to store the version of the boot agent that is stored in the flash image. When ...

  • Intel 324632-003 - page 78

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 78 January 2011 4.5.1.29.6 Configuration Customization Options PCI Function 1 (Word 35h) This word is the same as word 31h, but for function 1 of the device. 4. ...

  • Intel 324632-003 - page 79

    Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 79 Reserved 34 Reserved for future use. BELOW FIELDS ARE PER PORT. Flags 2 Bit 00h  Enable DHCP 0 – Use static configurations from this struct ...

  • Intel 324632-003 - page 80

    Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 80 January 2011 The maximum amount of boot configuration information that is stored is 834 bytes (417 words); however, the iSCSI boot implementation can limit t ...

  • Intel 324632-003 - page 81

    Manageability Control Sections — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 81 4.6 Manageability Control Sections 4.6.1 Sideband Configuration Structure 4.6.1.1 Section Header - (0ffset 0h) 4.6.1.2 SMBus Max Fragment ...

  • Intel 324632-003 - page 82

    Intel ® 82575EB Gigabit Ethernet Controller — Sideband Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 82 January 2011 15:9 SMBus 1 Slave Address Dual-address mode only. 8 Reserved 7:1 SMBus 0 Slave Address 0 Reserved ...

  • Intel 324632-003 - page 83

    Flex TCO Filter Configuration Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 83 4.6.1.5 SMBus Fail-Over Register (Low Word) - (0ffset 04h) 4.6.1.6 SMBus Fail-Over Register (High Word) - (0ffset 05h) 4.6.1.7 N ...

  • Intel 324632-003 - page 84

    Intel ® 82575EB Gigabit Ethernet Controller — Flex TCO Filter Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 84 January 2011 15:8 Block CRC8 7:0 Block Length ...

  • Intel 324632-003 - page 85

    NC-SI Microcode Download Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 85 4.6.2.2 Flex Filter Length and Control - (0ffset 01h) 4.6.2.3 Flex Filter Enable Mask - (0ffset 02 - 09h) 4.6.2.4 Flex Filter Data - ...

  • Intel 324632-003 - page 86

    Intel ® 82575EB Gigabit Ethernet Controller — NC-SI Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 86 January 2011 4.6.4 NC-SI Configuration Structure 4.6.4.1 Section Header - (0ffset 0h) 4.6.4.2 Rx Mode Control1 (RR_CTRL[15:0]) (Offset 01h) 4.6.4.3 Rx ...

  • Intel 324632-003 - page 87

    Common Firmware Pointer — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 87 4.6.4.5 Tx Mode Control2 (RT_CTRL[31:16]) (Offset 04h) 4.6.4.6 MAC Tx Control Reg1 (TxCntrlReg1 (15:0]) (Offset 05h) 4.6.4.7 MAC Tx Control Reg2 ...

  • Intel 324632-003 - page 88

    Intel ® 82575EB Gigabit Ethernet Controller — Pass Through Pointers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 88 January 2011 4.6.5.1 Manageability Capability/Manageability Enable (Word 54h) 4.6.6 Pass Through Pointers 4.6.6.1 PT LAN0 Configuration Pointer (Word 56h) 4.6. ...

  • Intel 324632-003 - page 89

    Pass Through Pointers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 89 15:0 Pointer Pointer to the flex TCO configuration pointer structure. ...

  • Intel 324632-003 - page 90

    Intel ® 82575EB Gigabit Ethernet Controller — PT LAN Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 90 January 2011 4.6.6.4 PT LAN1 Configuration Pointer (Word 59h) 4.6.6.5 NC-SI Microcode Download Pointer (Word 5Ah) 4.6.6.6 NC-SI Configuration Pointer ...

  • Intel 324632-003 - page 91

    PT LAN Configuration Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 91 Same structure as LAN0 IPv4 Address 0. 4.6.7.5 LAN0 IPv4 Address 2; MIPAF2 (Offset 05h:06h) Same structure as LAN0 IPv4 Address 0. 4.6.7. ...

  • Intel 324632-003 - page 92

    Intel ® 82575EB Gigabit Ethernet Controller — PT LAN Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 92 January 2011 4.6.7.13 LAN0 UDP Flex Filter Ports 0:15; MFUTP Registers (Offset 15h:24h) 4.6.7.14 LAN0 VLAN Filter 0:7; MAVTV Registers (Offset 25h:2Ch ...

  • Intel 324632-003 - page 93

    PT LAN Configuration Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 93 4.6.7.17 LAN0 MAC Value MSB (Offset 2Fh) 4.6.7.18 LAN0 MANC Value LSB (Offset 30h) 4.6.7.19 LAN0 Receive Enable 1(Offset 31h) 4.6.7.20 LA ...

  • Intel 324632-003 - page 94

    Intel ® 82575EB Gigabit Ethernet Controller — PT LAN Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 94 January 2011 7:0 Receive Enable Byte 13 Interface value. ...

  • Intel 324632-003 - page 95

    PT LAN Configuration Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 95 4.6.7.21 LAN0 MANC2H Value LSB (Offset 33h) 4.6.7.22 LAN0 MANC2H Value MSB (Offset 34h) 4.6.7.23 Manageability Decision Filters; MDEF0,1 ...

  • Intel 324632-003 - page 96

    Intel ® 82575EB Gigabit Ethernet Controller — PT LAN Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 96 January 2011 4.6.7.24 Manageability Decision Filters; MDEF0, 2 (Offset 36h) 4.6.7.25 Manageability Decision Filters; MDEF1:6, 1:2 (Offset 37h:42h) Sam ...

  • Intel 324632-003 - page 97

    PT LAN Configuration Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 97 4.6.7.26 ARP Response IPv4 Address 0 LSB (Offset 43h) 4.6.7.27 ARP Response IPv4 Address 0 MSB (Offset 44h) 4.6.7.28 LAN0 IPv6 Address 0 ...

  • Intel 324632-003 - page 98

    Intel ® 82575EB Gigabit Ethernet Controller — Software Owned EEPROM Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 98 January 2011 4.6.7.32 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 49h) 4.6.7.33 LAN0 IPv6 Address 0 MSB; MIPAF (Offset 4Ah) 4.6.7.34 LAN0 IPv6 Address 0 LSB; ...

  • Intel 324632-003 - page 99

    Compatibility Fields (Word 03h:07h) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 99 4.7.1 Compatibility Fields (Word 03h:07h) Five words in the EEPROM image are reserved for compatibility information. New bits within ...

  • Intel 324632-003 - page 100

    Intel ® 82575EB Gigabit Ethernet Controller — PBA Number (Words 08h, 09h) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 100 January 2011 The following example shows a PBA number stored in the PBA Number Module field (in the old style): § § PBA Number Byte 1 Byte 2 Byte 3 By ...

  • Intel 324632-003 - page 101

    Receive and Transmit Description — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 101 5.0 Receive and Transmit Description This section describes the data flows, packet reception, packet transmission, transmit descriptor ...

  • Intel 324632-003 - page 102

    Intel ® 82575EB Gigabit Ethernet Controller — Receive Data Flow Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 102 January 2011 5.2 Receive Data Flow Receive Data Flow provides a high level description of all data/control transformations steps needed for receiving Ethernet pac ...

  • Intel 324632-003 - page 103

    Packet Address Filtering — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 103 5.3.1 Packet Address Filtering Hardware stores incoming packets in host memory subject to the following filter modes. If there is insufficient ...

  • Intel 324632-003 - page 104

    Intel ® 82575EB Gigabit Ethernet Controller — Legacy Receive Descriptor Format Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 104 January 2011 If for any queue SRRCTL[n].BSIZEPACKET equals 0b, the buffer size defined by RCTL.BSIZE is used; otherwise, the buffer size defined by ...

  • Intel 324632-003 - page 105

    Legacy Receive Descriptor Format — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 105 For packets with a VLAN header, the packet checksum includes the header (if VLAN striping is not enabled by the CTRL.VME). If a VLAN h ...

  • Intel 324632-003 - page 106

    Intel ® 82575EB Gigabit Ethernet Controller — Legacy Receive Descriptor Format Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 106 January 2011 Table 28. Receive Status (RDESC.STATUS) Layout Note: See Table 34 for a description of supported packet types for receive checksum off ...

  • Intel 324632-003 - page 107

    Legacy Receive Descriptor Format — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 107 5.3.3.4 Receive Descriptor Errors Field Most error information appears only when the Store Bad Packets bit (RCTL.SBP) is set and a bad ...

  • Intel 324632-003 - page 108

    Intel ® 82575EB Gigabit Ethernet Controller — Legacy Receive Descriptor Format Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 108 January 2011 Table 29. Receive Errors (RDESC.ERRORS) Layout The IP and TCP checksum error bits are valid only when the IPv4 or TCP/UDP checksum(s) ...

  • Intel 324632-003 - page 109

    Advanced Receive Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 109 If receive checksum offloading is disabled (RXCSUM.IPOFL & RXCSUM.TUOFL), the IPE and TCPE bits are 0b. In 1000BASE-T or 10/100BASE-T ...

  • Intel 324632-003 - page 110

    Intel ® 82575EB Gigabit Ethernet Controller — Advanced Receive Descriptors Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 110 January 2011 When software sets the NSE bit, the 82575 places the received packet associated with this descriptor in memory at the Packet Buffer Addres ...

  • Intel 324632-003 - page 111

    Advanced Receive Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 111 5.3.4.3 Packet Type 5.3.4.4 RSS Type The 82575 must identify the packet type and then choose the appropriate RSS Hash Function to be used ...

  • Intel 324632-003 - page 112

    Intel ® 82575EB Gigabit Ethernet Controller — Advanced Receive Descriptors Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 112 January 2011 Table 31. Supported Packets Note: The header of the fragmented IPv6 packet is defined until the fragmented extension header. 5.3.4.6 Packe ...

  • Intel 324632-003 - page 113

    Advanced Receive Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 113 This field is mutually exclusive with the RSS Hash Value. It is enabled when the RXCSUM.PCSD bit is cleared. 5.3.4.7 RSS Hash Value This f ...

  • Intel 324632-003 - page 114

    Intel ® 82575EB Gigabit Ethernet Controller — Advanced Receive Descriptors Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 114 January 2011 Note: Unsupported packet types will either have the IXSM bit set, or do not have the IPCS or TCPCS bits set. Ipv6 packets do not have the ...

  • Intel 324632-003 - page 115

    Advanced Receive Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 115 5.3.4.10 Packet Buffer (Number of Bytes Exists in the Host Packet Buffer) The length covers the data written to a receive buffer including ...

  • Intel 324632-003 - page 116

    Intel ® 82575EB Gigabit Ethernet Controller — Receive UDP Fragmentation Checksum Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 116 January 2011 5.3.4.11 VLAN Tag Field Hardware stores additional information in the receive descriptor for 802.1q packets. If the packet type is 8 ...

  • Intel 324632-003 - page 117

    Receive Descriptor Write-Back — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 117 When the number of descriptors in host memory is greater than the available on-chip descriptor storage, the 82575 might elect to perform ...

  • Intel 324632-003 - page 118

    Intel ® 82575EB Gigabit Ethernet Controller — Receive Descriptor Ring Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 118 January 2011 Software inserts receive descriptors by advancing the tail pointer(s) to refer to the address of the entry just beyond the last valid ...

  • Intel 324632-003 - page 119

    Multiple Receive Queues — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 119 These registers hold a value that is an offset from the base and indicates the in-progress descriptor. There can be up to 8 KB descriptors in t ...

  • Intel 324632-003 - page 120

    Intel ® 82575EB Gigabit Ethernet Controller — Queuing for Virtual Machine Devices (VMDq) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 120 January 2011 When receiving an incoming packet, its header is analyzed, according to the protocol used (IPv4, IPv6, etc.). The connection ...

  • Intel 324632-003 - page 121

    Queuing for Virtual Machine Devices (VMDq) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 121 Software can program different values to the MAC filters (any bits in RAH or RAL) at any time. The 82575 responds to the cha ...

  • Intel 324632-003 - page 122

    Intel ® 82575EB Gigabit Ethernet Controller — Multiple Receive Queues & Receive-Side Scaling (RSS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 122 January 2011 5.4.2 Multiple Receive Queues & Receive-Side Scaling (RSS) The 82575 provides four hardware receive queues ...

  • Intel 324632-003 - page 123

    Multiple Receive Queues & Receive-Side Scaling (RSS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 123 • IPv6Ex. The 82575 parses the packet to identify an IPv6 packet. Extension headers should be parsed for a H ...

  • Intel 324632-003 - page 124

    Intel ® 82575EB Gigabit Ethernet Controller — Multiple Receive Queues & Receive-Side Scaling (RSS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 124 January 2011 The 32-bit result of the hash computation is written into the packet descriptor and also provides an index int ...

  • Intel 324632-003 - page 125

    Multiple Receive Queues & Receive-Side Scaling (RSS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 125 5.4.2.1.2 Hash for IPv4 with UDP Concatenate SourceAddress, DestinationAddress, SourcePort, DestinationPort in ...

  • Intel 324632-003 - page 126

    Intel ® 82575EB Gigabit Ethernet Controller — RSS Verification Suite Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 126 January 2011 5.4.2.3 Support for Multiple Processors It is assumed that each queue is associated with a specific processor, even when there are more processo ...

  • Intel 324632-003 - page 127

    Header Splitting and Replication — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 127 5.5 Header Splitting and Replication This feature consists of splitting or replicating a packet’s header to a different memory space ...

  • Intel 324632-003 - page 128

    Intel ® 82575EB Gigabit Ethernet Controller — Header Splitting and Replication Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 128 January 2011 The Header Buffer Address includes the address of the buffer that contains the header information. The Receive DMA module stores the h ...

  • Intel 324632-003 - page 129

    Header Splitting and Replication — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 129 Table 33. Header Splitting and Header Replication Mode Note: If SRRCTL#.NSE is set, all buffers' addresses in a packet descriptor ...

  • Intel 324632-003 - page 130

    Intel ® 82575EB Gigabit Ethernet Controller — Receive Packet Checksum Offloading Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 130 January 2011 5.5.1 Receive Packet Checksum Offloading The 82575 supports the offloading of three receive checksum calculations: the Packet Checks ...

  • Intel 324632-003 - page 131

    Receive Packet Checksum Offloading — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 131 Table 34 lists the general details about what packets are processed. In more detail, the packets are passed through a series of filt ...

  • Intel 324632-003 - page 132

    Intel ® 82575EB Gigabit Ethernet Controller — Receive Packet Checksum Offloading Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 132 January 2011 5.5.1.5 IPv6 Extension Headers IPv4 and TCP provide header lengths that allow hardware to easily navigate through these headers on p ...

  • Intel 324632-003 - page 133

    Packet Transmission — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 133 Table 35. Next Header Type Encodings Note: The 82575 hardware acceleration does not support all IPv6 Extension header types. Also, the RFCTL.Ipv6_D ...

  • Intel 324632-003 - page 134

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Data Storage Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 134 January 2011 Output packets are made up of pointer–length pairs constituting a descriptor chain (so called descriptor based transmission). Software forms tr ...

  • Intel 324632-003 - page 135

    Transmit Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 135 Each context defines information about the packet sent including the total size of the MAC header (TDESC.MACHDR), the amount of payload data that ...

  • Intel 324632-003 - page 136

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Write Back Format Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 136 January 2011 Table 36. Transmit Descriptor (TDESC) Layout – Legacy Mode 5.6.5 Transmit Descriptor Write Back Format 5.6.5.1 Length Length (T ...

  • Intel 324632-003 - page 137

    Transmit Descriptor Write Back Format — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 137 Because the CSO field is eight bits wide, it puts a limit the location of the checksum to 255 bytes from the beginning of the pac ...

  • Intel 324632-003 - page 138

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Write Back Format Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 138 January 2011 Table 37. Transmit Command (TDESC.CMD) Layout Note: When tail write-back is enabled, the descriptor write-back is not executed. 7 ...

  • Intel 324632-003 - page 139

    Transmit Descriptor Special Field Format — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 139 5.6.5.4 Transmit Descriptor Status Field Format Table 38. Transmit Status Layout 5.6.6 Transmit Descriptor Special Field Forma ...

  • Intel 324632-003 - page 140

    Intel ® 82575EB Gigabit Ethernet Controller — Advanced Transmit Context Descriptor Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 140 January 2011 Table 39. Special Field (TDESC.SPECIAL) Layout 5.6.7 Advanced Transmit Context Descriptor Table 40. Transmit Context Descriptor (T ...

  • Intel 324632-003 - page 141

    Advanced Transmit Context Descriptor — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 141 5.6.7.1 Maximum Segment Size (MSS) Control This field specifies the maximum TCP payload segment sent per frame, less any header. T ...

  • Intel 324632-003 - page 142

    Intel ® 82575EB Gigabit Ethernet Controller — Advanced Transmit Data Descriptor Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 142 January 2011 Table 42. Advanced Transmit Context Descriptor Required Valid Fields 5.6.8 Advanced Transmit Data Descriptor Table 43 and Table 44 li ...

  • Intel 324632-003 - page 143

    Advanced Transmit Data Descriptor — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 143 5.6.8.4 DCMD DCMD Layout Field Description TSE TCP Segmentation Enable Indicates a TCP segmentation request. When TSE is set in the f ...

  • Intel 324632-003 - page 144

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Ring Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 144 January 2011 5.6.8.5 STA Table 45. STA Layout 5.6.8.6 IDX Index into the hardware context table to indicate which context should be used for this ...

  • Intel 324632-003 - page 145

    Transmit Descriptor Ring Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 145 Descriptors passed to hardware should not be manipulated by software until the head pointer has advanced past them. Figure 6. Transm ...

  • Intel 324632-003 - page 146

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Fetching Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 146 January 2011 address = base + (ptr * 16) , where ptr is the value in the hardware head or tail register. The size chosen for the head and tail register ...

  • Intel 324632-003 - page 147

    TCP Segmentation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 147 write-back descriptors. Secondly, to preserve backward compatibility, if the TXDCTL[n].WTHRESH value is 0b, the 82575 writes back a single byte of the ...

  • Intel 324632-003 - page 148

    Intel ® 82575EB Gigabit Ethernet Controller — Assumptions Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 148 January 2011 5.8.1 Assumptions The following assumption applies to the TCP Segmentation implementation in the 82575: The RS bit operation is not changed. Interrupts are ...

  • Intel 324632-003 - page 149

    Packet Format — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 149 • The stack does not need to partition the block to fit the MTU size (saves CPU cycles). • The stack only computes one Ethernet, IP, and TCP header p ...

  • Intel 324632-003 - page 150

    Intel ® 82575EB Gigabit Ethernet Controller — TCP Segmentation Indication Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 150 January 2011 Setting the TSE bit in the TUCMD field to 1b indicates that this descriptor refers to the TCP Segmentation context (as opposed to the norma ...

  • Intel 324632-003 - page 151

    IP and TCP/UDP Headers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 151 • UDP Header: — The 82575’s DMA function fetches the Ethernet, IP, and TCP/UDP prototype header information from the initial descriptor(s) ...

  • Intel 324632-003 - page 152

    Intel ® 82575EB Gigabit Ethernet Controller — IP and TCP/UDP Headers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 152 January 2011 Figure 11. IPv4 Header (Little-Endian Order) Note: Identification is incremented on each packet. Flags Field Definition: The Flags field is defi ...

  • Intel 324632-003 - page 153

    IP and TCP/UDP Headers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 153 The TCP header is first shown in the traditional (RFC 793) representation. Because byte and bit ordering is confusing in that representation, th ...

  • Intel 324632-003 - page 154

    Intel ® 82575EB Gigabit Ethernet Controller — IP and TCP/UDP Headers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 154 January 2011 TCP Length = min(PAYLOADLEN) + L5_LEN The two flags that might be modified are defined as: • PSH: Receiver should pass this data to the applic ...

  • Intel 324632-003 - page 155

    IP and TCP/UDP Headers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 155 A type 0 routing header contains the following format: Figure 18. IPv6 Routing Header (Traditional Representation) • Next Header - 8-bit selec ...

  • Intel 324632-003 - page 156

    Intel ® 82575EB Gigabit Ethernet Controller — IP/TCP/UDP Header Updating Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 156 January 2011 All checksum calculations use a 16-bit wide one’s complement checksum. The checksum word is calculated on the outgoing data. The checksum ...

  • Intel 324632-003 - page 157

    IP/TCP/UDP Header Updating — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 157 5.8.7.1 TCP/IP/UDP Header for the First Frame The hardware makes the following changes to the headers of the first packet that is derived fr ...

  • Intel 324632-003 - page 158

    Intel ® 82575EB Gigabit Ethernet Controller — IP/TCP/UDP Transmit Checksum Offloading Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 158 January 2011 — UDP Checksum 5.8.7.3 TCP/IP/UDP Header for the Last Frame Hardware makes the following changes to the headers for the last ...

  • Intel 324632-003 - page 159

    IP/TCP/UDP Transmit Checksum Offloading in Non-Segmentation Mode — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 159 5.10 IP/TCP/UDP Transmit Checksum Offloading in Non-Segmentation Mode The previous section on TCP Segm ...

  • Intel 324632-003 - page 160

    Intel ® 82575EB Gigabit Ethernet Controller — TCP Checksum Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 160 January 2011 As mentioned in Section 5.6.2 , it is not necessary to set a new context for each new packet. In many cases, the same checksum context can be used for a m ...

  • Intel 324632-003 - page 161

    Tx Completions Head Write-Back — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 161 • Round robin arbitration is performed among the LP queues. Note: In order to prevent starvation, HP queues should not be used for TSO ...

  • Intel 324632-003 - page 162

    Intel ® 82575EB Gigabit Ethernet Controller — Interrupts Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 162 January 2011 Head write-back occurs if TDWBAL#.Head_WB_En is set for this queue and the RS bit is set in the Tx descriptor, following corresponding data upload into pack ...

  • Intel 324632-003 - page 163

    Interrupt Cause Set Register (ICS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 163 Note: When EICR is used in MSI-X mode, the Rx / Tx related bits in ICR should be masked. 5.13.2 Interrupt Cause Set Register (ICS) T ...

  • Intel 324632-003 - page 164

    Intel ® 82575EB Gigabit Ethernet Controller — Extended Interrupt Cause Set Register (EICS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 164 January 2011 5.13.7 Extended Interrupt Cause Set Register (EICS) This registers enables the setting of bits in EICR, by software, by wr ...

  • Intel 324632-003 - page 165

    Interrupt Modes Setting Bits — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 165 5.13.11 Interrupt Modes Setting Bits There are bits in the CTRL_EXT register that define the behavior of the interrupt mechanism. Setting ...

  • Intel 324632-003 - page 166

    Intel ® 82575EB Gigabit Ethernet Controller — Interrupt Moderation Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 166 January 2011 Inversely, inter-interrupt interval value can be calculated as: inter-interrupt interval = (256 10 -9 sec interrupts/sec) -1 The optimal performan ...

  • Intel 324632-003 - page 167

    Interrupt Moderation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 167 Figure 20. Interrupt Throttle Flow Diagram For cases where the 82575 is connected to a small number of clients, it is desirable to initiate the in ...

  • Intel 324632-003 - page 168

    Intel ® 82575EB Gigabit Ethernet Controller — Clearing Interrupt Causes Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 168 January 2011 Figure 21. Case A: Heavy Load, Interrupts Moderated Figure 22. Case B: Light Load, Interrupts Immediately on Packet Receive 5.15 Clearing Int ...

  • Intel 324632-003 - page 169

    Write to Clear — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 169 5.15.2 Write to Clear In the case where the software device driver wants to configure itself in MSI-X mode to not use the auto-clear feature, it might c ...

  • Intel 324632-003 - page 170

    Intel ® 82575EB Gigabit Ethernet Controller — TCP Timer Interrupt Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 170 January 2011 5.16.1 TCP Timer Interrupt In order to implement TCP timers for I/OAT 2, software needs to take action periodically (every 10 milliseconds). The so ...

  • Intel 324632-003 - page 171

    PCIe* Local Bus Interface — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 173 6.0 PCIe* Local Bus Interface This section describes the software interface and some related hardware aspects of PCIe* in regard to the 82575 ...

  • Intel 324632-003 - page 172

    Intel ® 82575EB Gigabit Ethernet Controller — Data Alignment Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 174 January 2011 6.1.3 Data Alignment 6.1.3.1 4 KB Boundary Requests must not specify an address/length combination causing memory space access to cross a 4 KB boundary. ...

  • Intel 324632-003 - page 173

    Transaction Attributes — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 175 6.1.4.2 Relaxed Ordering The 82575 takes advantage of the relaxed ordering rules of the PCIe* Specification. Relaxed ordering can be used in con ...

  • Intel 324632-003 - page 174

    Intel ® 82575EB Gigabit Ethernet Controller — Flow Control Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 176 January 2011 Under certain conditions that occur when I/OAT is enabled, software knows that it is safe to transfer a new packet into a certain buffer without snooping ...

  • Intel 324632-003 - page 175

    Flow Control Update Frequency — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 177 6.2.3 Flow Control Update Frequency In any case, UpdateFC packets are scheduled immediately after a resource is available. When the Link ...

  • Intel 324632-003 - page 176

    Intel ® 82575EB Gigabit Ethernet Controller — Tag IDs Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 178 January 2011 Table 54 lists the tag IDs in read transactions. Since DCA is implemented differently in data movement engine 1 and in data movement engine 2 platforms, the ta ...

  • Intel 324632-003 - page 177

    Tag IDs — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 179 Tag ID Description DCA 0Eh Reserved Disabled 0Fh Descriptors, data, WB tail for CPU ID 7 Enabled 1Bh:10h Reserved - 1Ch Reserved Disabled 1Dh Reserved Enabled ...

  • Intel 324632-003 - page 178

    Intel ® 82575EB Gigabit Ethernet Controller — Tag IDs Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 180 January 2011 Table 56. Tag IDs in Write Transactions (Data Movement Engine 2) Note: While in data movement engine 2 mode, if DCA is not enabled in the platform then the Tag ...

  • Intel 324632-003 - page 179

    Completion Timeout Mechanism — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 181 IDs are as in data movement engine 1 mode. When in data movement engine 2 mode, messages and MSI/MSI-X write requests are sent with a hint ...

  • Intel 324632-003 - page 180

    Intel ® 82575EB Gigabit Ethernet Controller — Error Events and Error Reporting Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 182 January 2011 • Version = 2h - Programmed through PCI configuration. Visible through the Completion_Timeout_Value bits in the PCIe* Control regist ...

  • Intel 324632-003 - page 181

    Error Events — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 183 Bad TLP • Bad CRC. • Illegal EDB. • Wrong sequence number. Correctable. Send ERR_CORR. TLP  Initiate Nak; drop data. Bad DLLP Bad CRC. Correctabl ...

  • Intel 324632-003 - page 182

    Intel ® 82575EB Gigabit Ethernet Controller — Error Pollution Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 184 January 2011 6.4.2 Error Pollution Error pollution can occur if error conditions for a given transaction are not isolated to the error’s first occurrence. If the ...

  • Intel 324632-003 - page 183

    Link Layer — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 185 2. Changes in the response to some Uncorrectable Non-Fatal errors detected in non-posted requests to the 82575 called Advisory Non-fatal Error cases. For ea ...

  • Intel 324632-003 - page 184

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit EDB Nullifying Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 186 January 2011 The following DLLPs are supported by the 82575 as a transmitter. 6.5.3 Transmit EDB Nullifying In case of a retrain, there is a need to guarant ...

  • Intel 324632-003 - page 185

    Link Width — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 187 The max link width is loaded into the Maximum Link Width field of the PCIe* Capability register (LCAP[11:6]). The hardware default is the x4 link. During li ...

  • Intel 324632-003 - page 186

    Intel ® 82575EB Gigabit Ethernet Controller — Performance Monitoring Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 188 January 2011 6.6.1.5 Reset The PCIe* Physical layer can supply a core reset to the 82575. The reset can be caused by the following: 1. Upstream move to Hot r ...

  • Intel 324632-003 - page 187

    Mandatory PCI Configuration Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 189 The LAN0 and LAN1 are shown in PCI functions 0 and PCI functions 1, respectively. The LAN Function Select field in EEPROM word 21 ...

  • Intel 324632-003 - page 188

    Intel ® 82575EB Gigabit Ethernet Controller — Mandatory PCI Configuration Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 190 January 2011 Note: The following color notation is used for reference: Interpretation of the various 82575 registers is provided as follows. V ...

  • Intel 324632-003 - page 189

    Mandatory PCI Configuration Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 191 Status Register Shaded bits are not used by this implementation and are hardwired to 0b. Each function has its own status registe ...

  • Intel 324632-003 - page 190

    Intel ® 82575EB Gigabit Ethernet Controller — Mandatory PCI Configuration Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 192 January 2011 Revision The default revision ID of this device is 02h. Note: LAN 0 and LAN 1 functions have the same revision ID. Class Code The ...

  • Intel 324632-003 - page 191

    Mandatory PCI Configuration Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 193 All base registers have the following fields: Expansion ROM Base Address This register is used to define the address and size inf ...

  • Intel 324632-003 - page 192

    Intel ® 82575EB Gigabit Ethernet Controller — Mandatory PCI Configuration Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 194 January 2011 Subsystem ID This value can be loaded automatically from the EEPROM at power up with a default value of 0000h. Subsystem Vendor I ...

  • Intel 324632-003 - page 193

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 195 Read and write registers programmed by software indicate the type of system interrupt request lines the device interrupt pin is bound to ...

  • Intel 324632-003 - page 194

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 196 January 2011 Power Management Control/Status Register (PMCSR) The PMCSR is 2 bytes at offset 44h and is read/write. This register is used to control ...

  • Intel 324632-003 - page 195

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 197 PMCSR_BSE Bridge Support Extensions: 1 Byte, Offset 46h, (RO) This field is 1 byte at offset 46h and is read only. This register is not ...

  • Intel 324632-003 - page 196

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 198 January 2011 Capability ID: 1 Byte, Offset 50h, (RO) This field equals 05h indicating the linked list item as being the Message Signaled Interrupt re ...

  • Intel 324632-003 - page 197

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 199 In contrast to the MSI capability structure, which directly contains all of the control/status information for the function's vecto ...

  • Intel 324632-003 - page 198

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 200 January 2011 Table 69. MSI-X Message Control Field Table 70. MSI-X Table Offset Bits Default RD/WR Description 10:0 009h 1 1. Default is read from th ...

  • Intel 324632-003 - page 199

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 201 Table 71. MSI-X PBA Table Offset To request service using a given MSI-X Table entry, a function performs a DWORD memory write transactio ...

  • Intel 324632-003 - page 200

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 202 January 2011 Note: The following color notation is used for reference: Capability ID The Capability ID is 1 byte at offset A0h and is read only. This ...

  • Intel 324632-003 - page 201

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 203 Device CAP This field is 4 bytes at offset A4h and is read only. It identifies the PCIe* device specific capabilities. It is a read only ...

  • Intel 324632-003 - page 202

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 204 January 2011 Device Status The Device Status field is 2 bytes at offset AAh and is read only. This register provides information about PCIe* device s ...

  • Intel 324632-003 - page 203

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 205 Link CAP The Link CAP is 4 bytes at offset ACh and is read only. This register identifies the PCIe* Link specific capabilities. This is ...

  • Intel 324632-003 - page 204

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 206 January 2011 Link Control The Link Control field is 2 bytes at offset B0h and is read only. This register controls PCIe* link specific parameters. Th ...

  • Intel 324632-003 - page 205

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 207 Link Status The Link Status field is 2 bytes at offset B2h and is read only. This register provides information about PCIe* link specifi ...

  • Intel 324632-003 - page 206

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 208 January 2011 Reserved Reserved. 2 bytes at offset B4h and is read only. Un-implemented reserved registers not relevant to PCIe* endpoint. The followi ...

  • Intel 324632-003 - page 207

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 209 Device Control 2 Device Control 2 is 2 bytes at offset C8h. This register controls PCIe* specific parameters. It has the same value for ...

  • Intel 324632-003 - page 208

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 210 January 2011 6.6.5.3.1 PCIe* Extended Configuration Space PCIe* Configuration Space is located in a flat memory mapped address space. PCIe* extends t ...

  • Intel 324632-003 - page 209

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 211 PCIe* Extended Configuration Space is allocated using a linked list of optional or required PCIe* extended capabilities following a form ...

  • Intel 324632-003 - page 210

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 212 January 2011 Serial Number Register (Offset 148h:144h) The Serial Number register is a 64-bit field that contains the IEEE defined 64-bit extended un ...

  • Intel 324632-003 - page 211

    PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 213 • Serial number ADDR + 2, 5 = EEPROM word 1 • Serial number ADDR + 3, 4 = FF FF • Serial number ADDR + 6, 7 = EEPROM word 2 The of ...

  • Intel 324632-003 - page 212

    Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 214 January 2011 NOTE: This page intentionally left blank. ...

  • Intel 324632-003 - page 213

    Power Management — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 215 7.0 Power Management The 82575 supports the Advanced Configuration and Power Interface (ACPI) Specification as well as Advanced Power Management (APM) ...

  • Intel 324632-003 - page 214

    Intel ® 82575EB Gigabit Ethernet Controller — Auxiliary Power Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 216 January 2011 Figure 23. Power States and Transitions 7.2 Auxiliary Power If DisableD3Cold equals 0b, the 82575 uses the AUX_PWR indication that auxiliary power is a ...

  • Intel 324632-003 - page 215

    Power Management Interconnects — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 217 Note: This auxiliary current limit only applies when the primary 3.3V voltage source is not available. For example, the NIC is in a low ...

  • Intel 324632-003 - page 216

    Intel ® 82575EB Gigabit Ethernet Controller — Power Management Interconnects Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 218 January 2011 82575 support for Active State Link Power Management is reported via the PCIe* Active State Link PM Support register loaded from the EEP ...

  • Intel 324632-003 - page 217

    Power Management Interconnects — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 219 Figure 24. Link Power Management 7.4.0.2 NC-SI Clock Control The 82575 can be configured to provide a 50 MHz output clock to its NC-SI i ...

  • Intel 324632-003 - page 218

    Intel ® 82575EB Gigabit Ethernet Controller — Power Management Interconnects Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 220 January 2011 This avoids negotiating through the LPLU procedure a link speed that is not advertised by the user. The following table lists the link s ...

  • Intel 324632-003 - page 219

    Power Management Interconnects — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 221 7.4.0.3.3 Non-D0a State The PHY can negotiate to a low speed while in a non-D0a states (Dr, D0u, or D3). This applies only when the link ...

  • Intel 324632-003 - page 220

    Intel ® 82575EB Gigabit Ethernet Controller — Power States Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 222 January 2011 7.4.0.3.6 SerDes/SGMII Power-Down State Each of the 82575’s SerDes enters a power-down state when none of its clients are enabled. This case does not re ...

  • Intel 324632-003 - page 221

    Power States — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 223 • Pass through manageability is disabled • ACPI PME is disabled for all PCI functions • The 82575 Disable Power Down En EEPROM bit is set (default h ...

  • Intel 324632-003 - page 222

    Intel ® 82575EB Gigabit Ethernet Controller — Power States Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 224 January 2011 On a transition from D3 to D0u, the 82575 PCI Configuration space is not reset. However, the 82575 requires that software perform a full re-initialization ...

  • Intel 324632-003 - page 223

    Power States — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 225 As a response to being programmed into the D3 state, the 82575 brings its PCIe* link into the L1 link state. As part of the transition into the L1 state, ...

  • Intel 324632-003 - page 224

    Intel ® 82575EB Gigabit Ethernet Controller — Power-State Transitions Timing Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 226 January 2011 7.4.2 Power-State Transitions Timing The following sections give detailed timing for the state transitions. The timing diagrams are not ...

  • Intel 324632-003 - page 225

    Power-State Transitions Timing — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 227 7.4.2.2 Transition from D0a to D3 and Back without PE_RST_N 13 A first PCIe* configuration access might arrive after t pgcfg from PE_RST ...

  • Intel 324632-003 - page 226

    Intel ® 82575EB Gigabit Ethernet Controller — Power-State Transitions Timing Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 228 January 2011 7.4.2.3 Transition from D0a to D3 and Back with PE_RST_N Notes 1 Writing 11b to the Power State field of the Power Management Control/St ...

  • Intel 324632-003 - page 227

    Power-State Transitions Timing — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 229 7.4.2.4 D0a to Dr and Back without Transition to D3 7.4.2.5 Timing Requirements The 82575 requires the following start up and power stat ...

  • Intel 324632-003 - page 228

    Intel ® 82575EB Gigabit Ethernet Controller — 82575 and SerDes Power-Down State Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 230 January 2011 7.4.2.6 Timing Guarantees The 82575 guarantees the following start up and power state transition related timing parameters. 7.4.3 825 ...

  • Intel 324632-003 - page 229

    Wake Up — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 231 The SerDes also enters a power-down state in the following cases: • When the 82575 is configured for PHY operation only. • When the LAN0_DIS_N (or LAN1_DIS ...

  • Intel 324632-003 - page 230

    Intel ® 82575EB Gigabit Ethernet Controller — PCIe Power Management Wakeup Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 232 January 2011 • Sets the Magic Packet Received bit in the Wake Up Status Register (WUS). • Sets the packet length in the Wake Up Packet Length Regis ...

  • Intel 324632-003 - page 231

    Wake-Up Packets — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 233 PE_WAKE_N remains asserted until the operating system either writes a 1b to the PME_Status bit of the PMCSR or writes a 0b to the PME_EN bit. After rec ...

  • Intel 324632-003 - page 232

    Intel ® 82575EB Gigabit Ethernet Controller — Wake-Up Packets Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 234 January 2011 For multicast packets, the upper bits of the destination address in the incoming packet index a bit vector. This is the Multicast Table Array that indi ...

  • Intel 324632-003 - page 233

    Wake-Up Packets — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 235 Note: Accepting broadcast magic packets for wake up purposes when Broadcast Accept bit of the Receive Control Register (RCTL.BAM) is 0b differs from ol ...

  • Intel 324632-003 - page 234

    Intel ® 82575EB Gigabit Ethernet Controller — Wake-Up Packets Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 236 January 2011 7.5.3.1.7 Directed IPv6 Packet The 82575 supports reception of Directed IPv6 packets for wake up if the IPv6 bit is set in the Wake Up Filter Control R ...

  • Intel 324632-003 - page 235

    Wake-Up Packets — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 237 Filter Value Table (FFVT). These contain separate values for each filter. The software must also enable the filter in the Wake Up Filter Control Regist ...

  • Intel 324632-003 - page 236

    Intel ® 82575EB Gigabit Ethernet Controller — Wake-Up Packets Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 238 January 2011 7.5.3.2.3 IPv6 Neighbor Discovery Filter In Ipv6, a Neighbor Discovery packet is used for address resolution. A flexible filter can be used to check fo ...

  • Intel 324632-003 - page 237

    DCA — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 239 8.0 DCA This section describes the Direct Cache Access (DCA) functionality for the 82575. Direct Cache Access (DCA) is a method to improve network I/O performance ...

  • Intel 324632-003 - page 238

    Intel ® 82575EB Gigabit Ethernet Controller — PCIe* Message Format for DCA (MWr Mode) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 240 January 2011 Figure 25. PCIe* Message Format for DCA The DCA preferences field has the following formats data movement engine 1 systems: For ...

  • Intel 324632-003 - page 239

    Ethernet Interface — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 241 9.0 Ethernet Interface The 82575 provides a complete CSMA/CD function supporting IEEE 802.3 (10 Mb/s), 802.3u (100 Mb/ s), 802.3z and 802.3ab (1000 ...

  • Intel 324632-003 - page 240

    Intel ® 82575EB Gigabit Ethernet Controller — Internal MAC/PHY 10/100/1000Base-T Interface Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 242 January 2011 The internal copper PHY features 10/100/1000BASE-T signaling and is capable of performing intelligent power-management bas ...

  • Intel 324632-003 - page 241

    Duplex Operation for Copper PHY Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 243 Software can use MDIO accesses to read or write registers in either 1000Base-T or 10/100Base-T mode by accessing the 82575’ ...

  • Intel 324632-003 - page 242

    Intel ® 82575EB Gigabit Ethernet Controller — Half Duplex Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 244 January 2011 9.2.2 Half Duplex In half duplex mode, the 82575 attempts to avoid contention with other traffic on the wire, by monitoring the carrier sense signal provid ...

  • Intel 324632-003 - page 243

    SGMII Encoding in 10/100 Mb/s — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 245 9.2.3.2 Code Groups and Ordered Sets Code group and ordered set definitions are defined in clause 36 of the IEEE 802.3z standard. These r ...

  • Intel 324632-003 - page 244

    Intel ® 82575EB Gigabit Ethernet Controller — Auto-Negotiation and Link Setup Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 246 January 2011 9.3 Auto-Negotiation and Link Setup The method for configuring the link between two link partners is highly dependent on the mode of op ...

  • Intel 324632-003 - page 245

    SerDes Link Configuration — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 247 A set of registers is provided to facilitate hardware Auto-Negotiation. Note: Hardware Auto-Negotiation can be initiated at power up or asser ...

  • Intel 324632-003 - page 246

    Intel ® 82575EB Gigabit Ethernet Controller — SerDes Link Configuration Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 248 January 2011 there is a valid signal being received by the optics or the SerDes. The source of the signal detect is a fixed bit (ENRGSRC) in register CONN ...

  • Intel 324632-003 - page 247

    Copper PHY Link Configuration — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 249 9.3.2 Copper PHY Link Configuration When operating with the internal PHY, link configuration is generally determined by PHY Auto- Negotia ...

  • Intel 324632-003 - page 248

    Intel ® 82575EB Gigabit Ethernet Controller — Copper PHY Link Configuration Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 250 January 2011 There might be circumstances when the software device driver must forcibly set the link speed of the MAC. This occurs when the link is ma ...

  • Intel 324632-003 - page 249

    Loss of Signal/Link Status Indication — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 251 • Resetting the PHY • Setting preferred link configuration for advertisement during the Auto-Negotiation process • Restarti ...

  • Intel 324632-003 - page 250

    Intel ® 82575EB Gigabit Ethernet Controller — Flow Control Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 252 January 2011 Flow control is implemented as a means of reducing the possibility of receive buffer overflows which result in the dropping of received packets, and allow ...

  • Intel 324632-003 - page 251

    Flow Control — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 253 Note: “S” is the Start-of-Packet delimiter and “T” is the first part of the End-of-Packet delimiters for 802.3z encapsulation. Figure 27. 802.3x M ...

  • Intel 324632-003 - page 252

    Intel ® 82575EB Gigabit Ethernet Controller — Discard PAUSE Frames and Pass MAC Control Frames Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 254 January 2011 Resumption of transmission can occur under the following conditions: • Expiration of the PAUSE timer • Reception o ...

  • Intel 324632-003 - page 253

    Software Initiated PAUSE Frame Transmission — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 255 Hardware sends a PAUSE frame if it has previously sent one and the FIFO overflows even if the refresh timer did not expire. ...

  • Intel 324632-003 - page 254

    Intel ® 82575EB Gigabit Ethernet Controller — MAC Loopback Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 256 January 2011 Figure 28. 82575 Loopback Modes 9.4.1 MAC Loopback In MAC loopback, the PHY and SerDes blocks are not functional and data is looped back before these bloc ...

  • Intel 324632-003 - page 255

    Internal SerDes Loopback — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 257 — Clear the Loopback bit (bit 14) — Set the Auto Neg Enable bit (bit 12) — Register values should be: a. For 10 Mb/s 4100h. b. For 100 M ...

  • Intel 324632-003 - page 256

    Intel ® 82575EB Gigabit Ethernet Controller — External PHY Loopback Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 258 January 2011 9.4.4.1 Setting External PHY Loopback Mode The following procedure should be used to put the 82575 in external PHY loopback mode: • Set Link mo ...

  • Intel 324632-003 - page 257

    802.1q VLAN Support — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 259 10.0 802.1q VLAN Support The 82575 provides several specific mechanisms to support 802.1q VLANs: • Optional adding (for transmits) and stripping ...

  • Intel 324632-003 - page 258

    Intel ® 82575EB Gigabit Ethernet Controller — Transmitting and Receiving 802.1q Packets Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 260 January 2011 Table 82. 802.1q Tagged Frames 10.2 Transmitting and Receiving 802.1q Packets Since the 802.1q tag is only four bytes, adding ...

  • Intel 324632-003 - page 259

    Stripping 802.1q Tags on Receives — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 261 10.2.2 Stripping 802.1q Tags on Receives Software can instruct the 82575 to strip 802.1q VLAN tags from received packets. If the CTRL ...

  • Intel 324632-003 - page 260

    Intel ® 82575EB Gigabit Ethernet Controller — Double VLAN Support Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 262 January 2011 Table 84. Packet Reception Decision Table 10.4 Double VLAN Support The 82575 supports a mode where all received and sent packet have at least one V ...

  • Intel 324632-003 - page 261

    PHY Functionality and Features — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 263 11.0 PHY Functionality and Features The PHY default configuration is determined by data from the EEPROM, read right after power-on reset ...

  • Intel 324632-003 - page 262

    Intel ® 82575EB Gigabit Ethernet Controller — Determining Link State Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 264 January 2011 11.2 Determining Link State The PHY and its link partner determine the type of link established through one of three methods: • Auto-Negotiati ...

  • Intel 324632-003 - page 263

    Forced Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 265 When the PHY is first powered on, reset, or encounters a link down state, it must determine the line speed and operating conditions to use for the net ...

  • Intel 324632-003 - page 264

    Intel ® 82575EB Gigabit Ethernet Controller — Parallel Detection Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 266 January 2011 11.2.4 Parallel Detection Parallel detection can only be used to establish 10 and 100 links. It occurs when the PHY tries to negotiate (transmit FLP ...

  • Intel 324632-003 - page 265

    Link Criteria — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 267 11.3 Link Criteria Once the link state is determined—via Auto-Negotiation, parallel detection or forced operation— the PHY and its link partner bring ...

  • Intel 324632-003 - page 266

    Intel ® 82575EB Gigabit Ethernet Controller — Flow Control Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 268 January 2011 lower speed: from 1000 to 100 to 10. Once a link is established, and if it is later broken, the PHY automatically upgrades the capabilities advertised to ...

  • Intel 324632-003 - page 267

    Management Data Interface — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 269 11.5 Management Data Interface The PHY supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) ...

  • Intel 324632-003 - page 268

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Functions Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 270 January 2011 Figure 30. 1000 Base-T PHY Functions Overview 11.8.1 Transmit Functions This section describes functions used when the Media Access Controller (MAC) ...

  • Intel 324632-003 - page 269

    Transmit FIFO — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 271 2. Each channel (A, B, C, D) gets a unique signature that the receiver uses for identification. The scrambler is driven by a Linear Feedback Shift Regist ...

  • Intel 324632-003 - page 270

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit FIFO Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 272 January 2011 11.8.2.5 Low-Pass Filter To aid with EMI, this filter attenuates signal components more than 180 Mhz. In 1000BASE-T, the fundamental symbol rate is 125 M ...

  • Intel 324632-003 - page 271

    Receive Functions — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 273 11.8.3 Receive Functions This section describes function blocks that are used when the PHY receives data from the twisted pair interface and passes i ...

  • Intel 324632-003 - page 272

    Intel ® 82575EB Gigabit Ethernet Controller — 100 Mb/s Operation Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 274 January 2011 The descrambler requires approximately 15  s. to lock, normally accomplished during the training phase. 11.8.3.7 Viterbi Decoder/Decision Feedbac ...

  • Intel 324632-003 - page 273

    10Base-T Link Failure Criteria and Override — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 275 11.10.2 10Base-T Link Failure Criteria and Override Link failure occurs if Link Test is enabled and link pulses stop being ...

  • Intel 324632-003 - page 274

    Intel ® 82575EB Gigabit Ethernet Controller — Dribble Bits Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 276 January 2011 NOTE: This page intentionally left blank. ...

  • Intel 324632-003 - page 275

    Configurable LED Outputs — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 277 12.0 Configurable LED Outputs The 82575 implements four output drivers intended for driving external LED circuits per port. Each LAN device pr ...

  • Intel 324632-003 - page 276

    Intel ® 82575EB Gigabit Ethernet Controller — Configurable LED Outputs Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 278 January 2011 NOTE: This page intentionally left blank. ...

  • Intel 324632-003 - page 277

    Dual Port Characteristics — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 279 13.0 Dual Port Characteristics The 82575 architecture includes two instances both the MAC and PHY. With both MAC/PHY pairs operating, the 825 ...

  • Intel 324632-003 - page 278

    Intel ® 82575EB Gigabit Ethernet Controller — PCIe* Interface Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 280 January 2011 Many of the fields of the PCIe* header space contain hardware default values that are either fixed or can be overridden using EEPROM, but cannot be ind ...

  • Intel 324632-003 - page 279

    MAC Configuration Register Space — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 281 13.1.2 MAC Configuration Register Space All device control/status registers detailed in Section 14.3 , Main Register Descriptions, are ...

  • Intel 324632-003 - page 280

    Intel ® 82575EB Gigabit Ethernet Controller — Link Mode/Configuration Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 282 January 2011 To avoid this contention, accesses from both LAN devices MUST be synchronized using external software synchronization of the memory or I/O tran ...

  • Intel 324632-003 - page 281

    Multi-Function Advertisement — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 283 code of this function changes to other values 10A6h and FF00h, respectively. In addition the function does not require any memory or I/O s ...

  • Intel 324632-003 - page 282

    Intel ® 82575EB Gigabit Ethernet Controller — BIOS Handling of Device Disable Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 284 January 2011 While in device disable mode, the PCIe* link is in L3 state. The PHY is in power down mode. Output buffers are tri-stated. Asserting or ...

  • Intel 324632-003 - page 283

    Copper/Fiber Switch — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 285 Software can then enable the OMED interrupt in ICR in order to get an indication on any detection of energy in the non active connection. The follo ...

  • Intel 324632-003 - page 284

    Intel ® 82575EB Gigabit Ethernet Controller — Copper/Fiber Switch Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 286 January 2011 CTRL_EXT (00018h) bits 23:22. The default value for the LINK_MODE setting is directly mapped from the EEPROM's initialization Control Word 3 ( ...

  • Intel 324632-003 - page 285

    Copper/Fiber Switch — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 287 NOTE: This page intentionally left blank. ...

  • Intel 324632-003 - page 286

    Intel ® 82575EB Gigabit Ethernet Controller — Copper/Fiber Switch Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 288 January 2011 ...

  • Intel 324632-003 - page 287

    Register Descriptions — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 287 14.0 Register Descriptions This section details the state inside the 82575 that are visible to the programmer. In some cases, it describes hardwa ...

  • Intel 324632-003 - page 288

    Intel ® 82575EB Gigabit Ethernet Controller — Register Conventions Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 288 January 2011 • Register pairs where two 32-bit registers make up a larger logical size. • Accesses to Flash memory (through the Expansion ROM space, second ...

  • Intel 324632-003 - page 289

    Memory and I/O Address Decoding — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 289 Table 87. Field Attributes 14.1.1 Memory and I/O Address Decoding 14.1.1.1 Memory-Mapped Access to Internal Registers and Memories The ...

  • Intel 324632-003 - page 290

    Intel ® 82575EB Gigabit Ethernet Controller — I/O-Mapped Internal Register, Internal Memory, and Flash Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 290 January 2011 14.1.1.4 Memory-Mapped Access to Expansion ROM The external Flash can also be accessed as a memory-mapped expa ...

  • Intel 324632-003 - page 291

    I/O-Mapped Internal Register, Internal Memory, and Flash — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 291 14.1.2.2 IODATA The IODATA register must always be written as a DWORD access when the IOADDR register contains ...

  • Intel 324632-003 - page 292

    Intel ® 82575EB Gigabit Ethernet Controller — Register Summary Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 292 January 2011 case, the 82575 delays the results through normal bus methods. For example, a split transaction or transaction retry. Because a register/memory/flash ...

  • Intel 324632-003 - page 293

    Register Summary — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 293 General 01014h EEMNGDATA Manageability EEPROM Read/Write Data RO 336 General 01018h FLMNGCTL Manageability Flash Control Register R/W 336 General 0101 ...

  • Intel 324632-003 - page 294

    Intel ® 82575EB Gigabit Ethernet Controller — Register Summary Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 294 January 2011 Receive 02814h: 02B28h RXDCTL Receive Descriptor Control Queue 3:0 R/W 360 Receive 02814h: 02B14h RXCTL Rx DCA Control Queue 3:0 R/W 376 Receive 05000 ...

  • Intel 324632-003 - page 295

    Register Summary — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 295 Statistics 04014h SCC Single Collision Count RC 418 Statistics 04018h ECOL Excessive Collisions Count RC 418 Statistics 0401Ch MCC Multiple Collision ...

  • Intel 324632-003 - page 296

    Intel ® 82575EB Gigabit Ethernet Controller — Register Summary Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 296 January 2011 Statistics 040E8h PTC1023 Packets Transmitted (512-1023 Bytes) Count RC 429 Statistics 040ECh PTC1522 Packets Transmitted (1024-1522) Count RC 429 Sta ...

  • Intel 324632-003 - page 297

    Register Summary — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 297 PCIe* 05B18h GSCL_3 PCIe* statistics Control #3 R/W 407 PCIe* 05B1Ch GSCL_4 PCIe* statistics Control #4 R/W 407 PCIe* 05B20h GSCN_0 PCIe* Counter #0 R ...

  • Intel 324632-003 - page 298

    Intel ® 82575EB Gigabit Ethernet Controller — Main Register Descriptions Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 298 January 2011 Note: The PHY registers are accessed through the MDI/O interface. 14.3 Main Register Descriptions This section contains detailed register de ...

  • Intel 324632-003 - page 299

    Device Control Register - CTRL (00000h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 299 14.3.1 Device Control Register - CTRL (00000h; R/W) This register, as well as the Extended Device Control register (CTRL_E ...

  • Intel 324632-003 - page 300

    Intel ® 82575EB Gigabit Ethernet Controller — Device Control Register - CTRL (00000h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 300 January 2011 Field Bit(s) Initial Value Description FD 0 1b Full-Duplex Controls the MAC duplex setting when explicitly set by software ...

  • Intel 324632-003 - page 301

    Device Control Register - CTRL (00000h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 301 SDP0_GPIEN 16 0b General Purpose Interrupt Detection Enable for SDP0 If software-controlled IO pin SDP0 is configured as a ...

  • Intel 324632-003 - page 302

    Intel ® 82575EB Gigabit Ethernet Controller — Device Status Register - STATUS (00008h; R) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 302 January 2011 14.3.2 Device Status Register - STATUS (00008h; R) This register provides software status for the 82575’s settings and mo ...

  • Intel 324632-003 - page 303

    EEPROM/Flash Control Register - EEC (00010h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 303 14.3.3 EEPROM/Flash Control Register - EEC (00010h; R/W) This register provides software direct access to the EEPROM. ...

  • Intel 324632-003 - page 304

    Intel ® 82575EB Gigabit Ethernet Controller — EEPROM/Flash Control Register - EEC (00010h; R/ W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 304 January 2011 Field Bit Initial Value Description EE_SK 0 0b Clock input to the EEPROM When EE_GNT = 1b, the EE_SK output signal i ...

  • Intel 324632-003 - page 305

    EEPROM Read Register - EERD (00014h; RW) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 305 14.3.4 EEPROM Read Register - EERD (00014h; RW) This register is used by software to cause the 82575 to read individual words ...

  • Intel 324632-003 - page 306

    Intel ® 82575EB Gigabit Ethernet Controller — Extended Device Control Register - CTRL_EXT (00018h, R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 306 January 2011 14.3.5 Extended Device Control Register - CTRL_EXT (00018h, R/W) This register provides extended control of t ...

  • Intel 324632-003 - page 307

    Extended Device Control Register - CTRL_EXT (00018h, R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 307 Field Bit(s) Initial Value Description NSICR 0 0b Non Selective Interrupt clear on read When set, every read ...

  • Intel 324632-003 - page 308

    Intel ® 82575EB Gigabit Ethernet Controller — Extended Device Control Register - CTRL_EXT (00018h, R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 308 January 2011 RO-DIS 17 0b Relaxed Ordering Disabled When set to 1b, the 82575 does not request any relaxed ordering transa ...

  • Intel 324632-003 - page 309

    Flash Access - FLA (0001Ch; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 309 14.3.6 Flash Access - FLA (0001Ch; R/W) This register provides software direct access to the Flash. Software can control the Flash by ...

  • Intel 324632-003 - page 310

    Intel ® 82575EB Gigabit Ethernet Controller — MDI Control Register - MDIC (00020h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 310 January 2011 14.3.7 MDI Control Register - MDIC (00020h; R/W) Software uses this register to read or write Management Data Interface (MDI) ...

  • Intel 324632-003 - page 311

    PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 311 Note: After a PHY reset, access through the MDIC register should not be attempted for 300  s. 14.3.8 PHY Registers This document uses a special nomenc ...

  • Intel 324632-003 - page 312

    Intel ® 82575EB Gigabit Ethernet Controller — PHY Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 312 January 2011 Table 89. PHY Register Bit Mode Definitions 14.3.8.1 PHY Control Register - PCTRL (00d; R/W) Register Mode Description LH Latched High. Event is latched ...

  • Intel 324632-003 - page 313

    PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 313 14.3.8.2 PHY Status Register - PSTATUS (01d; R) Speed Selection (LSB) 13 See Speed Selection (MSB), bit 6. Note: If auto-negotiation is enabled, this bit ...

  • Intel 324632-003 - page 314

    Intel ® 82575EB Gigabit Ethernet Controller — PHY Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 314 January 2011 14.3.8.3 PHY Identifier Register 1 (LSB) - PHY ID 1 (02d; R) 14.3.8.4 PHY Identifier Register 2 (MSB) - PHY ID 2 (03d; R) 14.3.8.5 Auto-Negotiation Adver ...

  • Intel 324632-003 - page 315

    PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 315 14.3.8.6 Auto-Negotiation Base Page Ability Register - (05d; R) PAUSE 10 Advertise to Partner that Pause operation (as defined in 802.3x) is desired. R/W ...

  • Intel 324632-003 - page 316

    Intel ® 82575EB Gigabit Ethernet Controller — PHY Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 316 January 2011 14.3.8.7 Auto-Negotiation Expansion Register - ANE (06d; R) 14.3.8.8 Auto-Negotiation Next Page Transmit Register - NPT (07d; R/W) Field Bit(s) Descripti ...

  • Intel 324632-003 - page 317

    PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 317 14.3.8.9 Auto-Negotiation Next Page Ability Register - LPN (08d; R) 14.3.8.10 1000BASE-T/100BASE-T2 Control Register - GCON (09d; R/W) Bit(s) Field Descr ...

  • Intel 324632-003 - page 318

    Intel ® 82575EB Gigabit Ethernet Controller — PHY Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 318 January 2011 14.3.8.11 1000BASE-T/100BASE-T2 Status Register - GSTATUS (10d; R) 1. The default of this bit is affected by the EEPROM bit configuration of the 82575. I ...

  • Intel 324632-003 - page 319

    PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 319 14.3.8.12 Extended Status Register - ESTATUS (15d; R) 14.3.8.13 Port Configuration Register - PCONF (16d; R/W) Field Bit(s) Description Mode Default Rese ...

  • Intel 324632-003 - page 320

    Intel ® 82575EB Gigabit Ethernet Controller — PHY Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 320 January 2011 14.3.8.14 Port Status 1 Register - PSTAT (17d; RO) Transmit Disable 13 1b = Disable twisted-pair transmitter. 0b = Normal operation. R/W 0b Link Disable ...

  • Intel 324632-003 - page 321

    PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 321 14.3.8.15 Port Control Register - PCONT (18d; R/W) Receive Status 12 1b = PHY currently receiving a packet. 0b = PHY receiver is IDLE. When in internal l ...

  • Intel 324632-003 - page 322

    Intel ® 82575EB Gigabit Ethernet Controller — PHY Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 322 January 2011 14.3.8.16 Link Health Register - LINK (19d; RO) MDI-X Mode 13 Force MDI-X mode. Valid only when operating in manual mode. (PHY register 18d, bit 12 = 0b. ...

  • Intel 324632-003 - page 323

    PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 323 14.3.8.17 1000Base-T FIFO Register - PFIFO (20d; R/W) Gigabit Master Resolution 12 Gig has resolved to master. This is a duplicate of PHY register 10d, b ...

  • Intel 324632-003 - page 324

    Intel ® 82575EB Gigabit Ethernet Controller — PHY Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 324 January 2011 14.3.8.18 Channel Quality Register - CHAN (21d; RO) 14.3.8.19 PHY Power Management - (25d; R/W) 14.3.8.20 Special Gigabit Disable Register - (26d; R/W) F ...

  • Intel 324632-003 - page 325

    PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 325 14.3.8.21 Misc Cntrl Register 1 - (27d; R/W) 14.3.8.22 Misc Cntrl Register 2 - (28d; RO) Note: Bits 13:8 might differ from the corresponding bits in PHY ...

  • Intel 324632-003 - page 326

    Intel ® 82575EB Gigabit Ethernet Controller — SERDES ANA - SERDESCTL (00024h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 326 January 2011 14.3.8.23 Page Select Core Register - (31d; WO) 14.3.9 SERDES ANA - SERDESCTL (00024h; R/W) 14.3.10 Copper/Fiber Switch Control - ...

  • Intel 324632-003 - page 327

    VLAN Ether Type - VET (00038h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 327 14.3.11 VLAN Ether Type - VET (00038h; R/W) This register contains the type field hardware matches against to recognize an 802.1Q ( ...

  • Intel 324632-003 - page 328

    Intel ® 82575EB Gigabit Ethernet Controller — Flow Control Address Low - FCAL (00028h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 328 January 2011 Table 90. PCIe* Performance 14.3.13 Flow Control Address Low - FCAL (00028h; R/ W) Flow control packets are defined by 80 ...

  • Intel 324632-003 - page 329

    Flow Control Type - FCT (00030h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 329 14.3.15 Flow Control Type - FCT (00030h; R/W) This register contains the type field that hardware matches to recognize a flow con ...

  • Intel 324632-003 - page 330

    Intel ® 82575EB Gigabit Ethernet Controller — LED Control - LEDCTL (00E00h; RW) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 330 January 2011 14.3.17.1 MODE Encodings for LED Outputs Table 91 lists the MODE encodings used to select the desired LED signal source for each LED ...

  • Intel 324632-003 - page 331

    Packet Buffer Allocation - PBA (01000h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 331 Table 91. Mode Encodings 14.3.18 Packet Buffer Allocation - PBA (01000h; R/W) This register sets the on-chip receive and t ...

  • Intel 324632-003 - page 332

    Intel ® 82575EB Gigabit Ethernet Controller — Packet Buffer Size - PBS (01008h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 332 January 2011 14.3.19 Packet Buffer Size - PBS (01008h; R/W) This register sets the on-chip receive and transmit storage allocation size, The ...

  • Intel 324632-003 - page 333

    SFP 12C Parameters - I2CPARAMS (0102Ch; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 333 14.3.21 SFP 12C Parameters - I2CPARAMS (0102Ch; R/ W) This register is used to set the parameters for the I 2 C access to ...

  • Intel 324632-003 - page 334

    Intel ® 82575EB Gigabit Ethernet Controller — Flash Opcode - FLASHOP (0103Ch; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 334 January 2011 14.3.22 Flash Opcode - FLASHOP (0103Ch; R/W) This register enables the host or the firmware to define the op-code used in order to ...

  • Intel 324632-003 - page 335

    Manageability EEPROM Control Register - EEMNGCTL (01010h; RO) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 335 14.3.24 Manageability EEPROM Control Register - EEMNGCTL (01010h; RO) This register is reserved for firmw ...

  • Intel 324632-003 - page 336

    Intel ® 82575EB Gigabit Ethernet Controller — Manageability EEPROM Read/Write Data - EEMNGDATA (1014h; RO) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 336 January 2011 14.3.25 Manageability EEPROM Read/Write Data - EEMNGDATA (1014h; RO) 14.3.26 Manageability Flash Control R ...

  • Intel 324632-003 - page 337

    Manageability Flash Read Counter - FLMNGCNT (1020h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 337 (101Ch; R/W) 14.3.28 Manageability Flash Read Counter - FLMNGCNT (1020h; R/W) 14.3.29 EEPROM Auto Read Bus Con ...

  • Intel 324632-003 - page 338

    Intel ® 82575EB Gigabit Ethernet Controller — Watchdog Setup - WDSTP (01040h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 338 January 2011 Note: • More than one valid bit can be set for write accesses. This results in writing the specific address to more than one des ...

  • Intel 324632-003 - page 339

    Free Running Timer - FRTIMER (01048h; RWS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 339 14.3.32 Free Running Timer - FRTIMER (01048h; RWS) This register reflects the value of a free running timer that can be used ...

  • Intel 324632-003 - page 340

    Intel ® 82575EB Gigabit Ethernet Controller — Interrupt Cause Read Register - ICR (000C0H; R) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 340 January 2011 14.3.34 Interrupt Cause Read Register - ICR (000C0H; R) This register contains the interrupt conditions for the 82575 t ...

  • Intel 324632-003 - page 341

    Interrupt Cause Set Register - ICS (000C8h; WO) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 341 14.3.35 Interrupt Cause Set Register - ICS (000C8h; WO) Software uses this register to set an interrupt condition. Any ...

  • Intel 324632-003 - page 342

    Intel ® 82575EB Gigabit Ethernet Controller — Interrupt Mask Set/Read Register - IMS (000D0h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 342 January 2011 14.3.36 Interrupt Mask Set/Read Register - IMS (000D0h; R/W) Reading this register returns bits have an interrupt ...

  • Intel 324632-003 - page 343

    Interrupt Mask Clear Register - IMC (000D8h; W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 343 14.3.37 Interrupt Mask Clear Register - IMC (000D8h; W) Software uses this register to disable an interrupt. Interrupts ...

  • Intel 324632-003 - page 344

    Intel ® 82575EB Gigabit Ethernet Controller — Interrupt Acknowledge Auto Mask Register - IAM (000E0h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 344 January 2011 On interrupt handling, the software device driver should set all the bits in this register related to the ...

  • Intel 324632-003 - page 345

    Extended Interrupt Cause - EICR (01580h; RC/W1C) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 345 14.3.39 Extended Interrupt Cause - EICR (01580h; RC/ W1C) This register contains the frequent interrupt conditions for ...

  • Intel 324632-003 - page 346

    Intel ® 82575EB Gigabit Ethernet Controller — Extended Interrupt Mask Set/Read - EIMS (01524h; RWS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 346 January 2011 14.3.41 Extended Interrupt Mask Set/Read - EIMS (01524h; RWS) Reading of this register returns which bits have an ...

  • Intel 324632-003 - page 347

    Extended Interrupt Auto Clear - EIAC (0152Ch; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 347 Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b to the corre ...

  • Intel 324632-003 - page 348

    Intel ® 82575EB Gigabit Ethernet Controller — Interrupt Throttle - EITR (01680h + 4*n [n = 0..9]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 348 January 2011 14.3.45 Interrupt Throttle - EITR (01680h + 4*n [n = 0..9]; R/W) • Interrupt Throttle Register Queue 0 EITR0 ...

  • Intel 324632-003 - page 349

    Immediate Interrupt Rx - IMIR (05A80h + 4*n [n = 0..7]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 349 14.3.46 Immediate Interrupt Rx - IMIR (05A80h + 4*n [n = 0..7]; R/W) This register defines the filtering t ...

  • Intel 324632-003 - page 350

    Intel ® 82575EB Gigabit Ethernet Controller — Immediate Interrupt Rx Extended - IMIREXT (05AA0h + 4*n [n = 0..7]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 350 January 2011 14.3.47 Immediate Interrupt Rx Extended - IMIREXT (05AA0h + 4*n [n = 0..7]; R/W) Note: The siz ...

  • Intel 324632-003 - page 351

    MSI-X Allocation - MSIXBM (01600h + 4*n [n = 0..9]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 351 14.3.49 MSI-X Allocation - MSIXBM (01600h + 4*n [n = 0..9]; R/W) • MSI-X Allocation Register - MSIXBM0 (0160 ...

  • Intel 324632-003 - page 352

    Intel ® 82575EB Gigabit Ethernet Controller — Receive Control Register - RCTL (00100h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 352 January 2011 Field Bit(s) Initial Value Description Reserved 0 0b Reserved Write to 0b for future compatibility. RXEN 1 0b Receiver En ...

  • Intel 324632-003 - page 353

    Receive Control Register - RCTL (00100h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 353 RDMTS 9:8 00b Receive Descriptor Minimum Threshold Size The corresponding interrupt is set each time the fractional numbe ...

  • Intel 324632-003 - page 354

    Intel ® 82575EB Gigabit Ethernet Controller — Split and Replication Receive Control - SRRCTL (0280Ch + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 354 January 2011 14.3.51 Split and Replication Receive Control - SRRCTL (0280Ch + 100*n [n=0..3]; R/W) • ...

  • Intel 324632-003 - page 355

    Packet Split Receive Type - PSRTYPE (05480h + 4*n [n=0..3]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 355 14.3.52 Packet Split Receive Type - PSRTYPE (05480h + 4*n [n=0..3]; R/W) This register enables or disa ...

  • Intel 324632-003 - page 356

    Intel ® 82575EB Gigabit Ethernet Controller — Flow Control Receive Threshold Low - FCRTL (02160h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 356 January 2011 14.3.53 Flow Control Receive Threshold Low - FCRTL (02160h; R/W) This register contains the receive threshold ...

  • Intel 324632-003 - page 357

    Flow Control Receive Threshold High - FCRTH (02168h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 357 14.3.54 Flow Control Receive Threshold High - FCRTH (02168h; R/W) This register contains the receive threshol ...

  • Intel 324632-003 - page 358

    Intel ® 82575EB Gigabit Ethernet Controller — Receive Descriptor Base Address High - RDBAH (02804h + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 358 January 2011 14.3.55.1 Receive Descriptor Base Address Low - RDBAL (02800h + 100*n [n=0..3]; R/W) This r ...

  • Intel 324632-003 - page 359

    Receive Descriptor Head - RDH (02810h + 100*n [n=0..3]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 359 14.3.58 Receive Descriptor Head - RDH (02810h + 100*n [n=0..3]; R/W) The value in this register might poin ...

  • Intel 324632-003 - page 360

    Intel ® 82575EB Gigabit Ethernet Controller — Receive Descriptor Control - RXDCTL (02828h + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 360 January 2011 14.3.60 Receive Descriptor Control - RXDCTL (02828h + 100*n [n=0..3]; R/W) This register controls th ...

  • Intel 324632-003 - page 361

    Receive Checksum Control - RXCSUM (05000h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 361 14.3.61 Receive Checksum Control - RXCSUM (05000h; R/W) The Receive Checksum Control register controls the receive chec ...

  • Intel 324632-003 - page 362

    Intel ® 82575EB Gigabit Ethernet Controller — Receive Long Packet Maximum Length - RLPML (05004; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 362 January 2011 14.3.62 Receive Long Packet Maximum Length - RLPML (05004; R/W) 14.3.63 Receive Filter Control Register - RFCTL ...

  • Intel 324632-003 - page 363

    Transmit Control Register - TCTL (00400h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 363 14.3.64 Transmit Control Register - TCTL (00400h; R/ W) This register controls all transmit functions for the 82575. Sof ...

  • Intel 324632-003 - page 364

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Control Extended - TCTL_EXT (00404;R/ W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 364 January 2011 14.3.65 Transmit Control Extended - TCTL_EXT (00404;R/W) This register controls late collision detection. COLD is use ...

  • Intel 324632-003 - page 365

    Transmit IPG Register - TIPG (00410;R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 365 14.3.66 Transmit IPG Register - TIPG (00410;R/W) This register controls the Inter Packet Gap (IPG) timer. The recommended TIPG ...

  • Intel 324632-003 - page 366

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Base Address Low - TDBAL (03800h + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 366 January 2011 14.3.68 Transmit Descriptor Base Address Low - TDBAL (03800h + 100*n [n=0..3]; R/W) These r ...

  • Intel 324632-003 - page 367

    Transmit Descriptor Length - TDLEN (03808h + 100*n [n=0..3]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 367 14.3.70 Transmit Descriptor Length - TDLEN (03808h + 100*n [n=0..3]; R/W) These registers contain the ...

  • Intel 324632-003 - page 368

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Control - TXDCTL (03828h + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 368 January 2011 • Queue1 - TDT1 (03918h) • Queue2 - TDT2 (03A18h) • Queue3 - TDT3 (03B18h) 14.3.73 Transmit D ...

  • Intel 324632-003 - page 369

    Tx Descriptor Completion Write-Back Address Low - TDWBAL (03838h + 100*n [n=0..3]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 369 14.3.74 Tx Descriptor Completion Write-Back Address Low - TDWBAL (03838h + 100* ...

  • Intel 324632-003 - page 370

    Intel ® 82575EB Gigabit Ethernet Controller — Tx Descriptor Completion Write-Back Address High - TDWBAH (0383Ch + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 370 January 2011 14.3.75 Tx Descriptor Completion Write-Back Address High - TDWBAH (0383Ch + 10 ...

  • Intel 324632-003 - page 371

    PCS Link Control - PCS_LCTL (04208h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 371 14.3.77 PCS Link Control - PCS_LCTL (04208h; R/W) Field Bit(s) Initial Value Description FLV 0 0b Forced Link Value This bit ...

  • Intel 324632-003 - page 372

    Intel ® 82575EB Gigabit Ethernet Controller — PCS Link Status - PCS_LSTS (0420Ch; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 372 January 2011 14.3.78 PCS Link Status - PCS_LSTS (0420Ch; R/W) Reserved 23:21 000b Reserved FAST LINK TIMER 24 0b Fast Link Timer AN timer i ...

  • Intel 324632-003 - page 373

    AN Advertisement - PCS_ANADV (04218h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 373 14.3.79 AN Advertisement - PCS_ANADV (04218h; R/ W) AN REMOTE FAULT 19 0b AN Remote Fault This bit indicates that an AN page ...

  • Intel 324632-003 - page 374

    Intel ® 82575EB Gigabit Ethernet Controller — Link Partner Ability - PCS_LPAB (0421Ch; RO) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 374 January 2011 14.3.80 Link Partner Ability - PCS_LPAB (0421Ch; RO) Reserved 14 - Reserved NEXTP 15 0b Next Page Capable The 82575 assert ...

  • Intel 324632-003 - page 375

    Next Page Transmit - PCS_NPTX (04220h; RO) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 375 14.3.81 Next Page Transmit - PCS_NPTX (04220h; RO) ACK 14 0b Acknowledge (SerDes) The link partner has acknowledge page rece ...

  • Intel 324632-003 - page 376

    Intel ® 82575EB Gigabit Ethernet Controller — Link Partner Ability Next Page - PCS_LPABNP (04224h; RO) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 376 January 2011 14.3.82 Link Partner Ability Next Page - PCS_LPABNP (04224h; RO) 14.4 DCA Registers This section contains deta ...

  • Intel 324632-003 - page 377

    Rx DCA Control Registers - RXCTL (02814h 100h *n [n=0..3]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 377 • Queue3 - RXCTL3 (02B14h) Field Bit(s) Initial Value Description CPUID 4:0 0h Physical ID In a data ...

  • Intel 324632-003 - page 378

    Intel ® 82575EB Gigabit Ethernet Controller — Tx DCA Control Registers - TXCTL (03814h + 100h *n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 378 January 2011 14.4.2 Tx DCA Control Registers - TXCTL (03814h + 100h *n [n=0..3]; R/W) • Queue0 - TXCTL0 (03814h) ...

  • Intel 324632-003 - page 379

    Multicast Table Array - MTA (05200h + 4*n [n..127]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 379 14.5.1 Multicast Table Array - MTA (05200h + 4*n [n..127]; R/W) There is one register per 32 bits of the Multi ...

  • Intel 324632-003 - page 380

    Intel ® 82575EB Gigabit Ethernet Controller — Receive Address Low - RAL (05400h + 8*n [n=0..15]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 380 January 2011 14.5.2 Receive Address Low - RAL (05400h + 8*n [n=0..15]; R/W) Note: "n" is the exact unicast/multica ...

  • Intel 324632-003 - page 381

    VLAN Filter Table Array - VFTA (05600h + 4*n [n=0..127]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 381 14.5.4 VLAN Filter Table Array - VFTA (05600h + 4*n [n=0..127]; R/W) There is one register per 32 bits of ...

  • Intel 324632-003 - page 382

    Intel ® 82575EB Gigabit Ethernet Controller — Multiple Receive Queues Command Register - MRQC (05818h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 382 January 2011 14.5.5 Multiple Receive Queues Command Register - MRQC (05818h; R/W) Notes: 1. MRQC_EN is used for enable ...

  • Intel 324632-003 - page 383

    Redirection Table - RETA (05C00h + 4*n [n=0..31]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 383 14.5.6 Redirection Table - RETA (05C00h + 4*n [n=0..31]; R/W) The redirection table is a 128-entry table with ea ...

  • Intel 324632-003 - page 384

    Intel ® 82575EB Gigabit Ethernet Controller — RSS Random Key Register - RSSRK (05C80h + 4*n [n=0..9]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 384 January 2011 14.5.7 RSS Random Key Register - RSSRK (05C80h + 4*n [n=0..9]; R/W) The RSS Random Key register stores a 4 ...

  • Intel 324632-003 - page 385

    VLAN Filter Queue Array 0 - VFQA0 (0B100h + 4*n [n=0…127]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 385 14.5.9 VLAN Filter Queue Array 0 - VFQA0 (0B100h + 4*n [n=0…127]; R/W) This register set classifies ...

  • Intel 324632-003 - page 386

    Intel ® 82575EB Gigabit Ethernet Controller — Wakeup Filter Control Register - WUFC (05808h; R/ W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 386 January 2011 14.6.2 Wakeup Filter Control Register - WUFC (05808h; R/W) This register is used to enable each of the pre-defined ...

  • Intel 324632-003 - page 387

    Wakeup Status Register - WUS (05810h; R/W1C) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 387 14.6.3 Wakeup Status Register - WUS (05810h; R/ W1C) This register is used to record statistics about all wakeup packets r ...

  • Intel 324632-003 - page 388

    Intel ® 82575EB Gigabit Ethernet Controller — IPv4 Address Table - IP4AT (05840h + 8*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 388 January 2011 14.6.5 IPv4 Address Table - IP4AT (05840h + 8*n [n=0..3]; R/W) The IPv4 Address Table is used to store the four ...

  • Intel 324632-003 - page 389

    Wakeup Packet Length - WUPL (05900h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 389 14.6.7 Wakeup Packet Length - WUPL (05900h; RC) This register indicates the length of the first wakeup packet received. It is ...

  • Intel 324632-003 - page 390

    Intel ® 82575EB Gigabit Ethernet Controller — Flexible Filter Value Table - FFVT (09800h + 8*n [n=0..127]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 390 January 2011 14.6.10 Flexible Filter Value Table - FFVT (09800h + 8*n [n=0..127]; R/W) The Flexible Filter Value a ...

  • Intel 324632-003 - page 391

    Manageability Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 391 All reserved fields read as 0's and ignore writes. Note: Before writing to the flexible filter length table the software device driver mus ...

  • Intel 324632-003 - page 392

    Intel ® 82575EB Gigabit Ethernet Controller — Management Flex UDP/TCP Ports - MFUTP (5030h + 4*n [n=0..7]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 392 January 2011 14.7.2 Management Flex UDP/TCP Ports - MFUTP (5030h + 4*n [n=0..7]; R/W) Where each 32-bit register ( ...

  • Intel 324632-003 - page 393

    Manageability Filters Valid - MFVAL (5824h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 393 14.7.4 Manageability Filters Valid - MFVAL (5824h; R/ W) The manageability filters valid registers indicate which filt ...

  • Intel 324632-003 - page 394

    Intel ® 82575EB Gigabit Ethernet Controller — Management Control to Host Register - MANC2H (5860h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 394 January 2011 14.7.5 Management Control to Host Register - MANC2H (5860h; R/W) The MANC2H register enables the routing of m ...

  • Intel 324632-003 - page 395

    Manageability IP Address Filter - MIPAF (0x58B0-0x58EC; RW) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 395 14.7.7 Manageability IP Address Filter - MIPAF (0x58B0-0x58EC; RW) The Manageability IP Address Filter regi ...

  • Intel 324632-003 - page 396

    Intel ® 82575EB Gigabit Ethernet Controller — Manageability IP Address Filter - MIPAF (0x58B0- 0x58EC; RW) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 396 January 2011 EN_IPv4_FILTER = 1b: 4 58C0h IPV6ADDR1 5 58C4h 6 58C8h 7 58CCh 8 58D0h IPV6ADDR2 9 58D4h 10 58D8h 11 58DCh ...

  • Intel 324632-003 - page 397

    Manageability IP Address Filter - MIPAF (0x58B0-0x58EC; RW) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 397 7 58CCh 8 58D0h 9 58D4h IPV6ADDR2 10 58D8h 11 58DCh 12 58E0h IPV4ADDR0 13 58E4h IPV4ADDR1 14 58E8h IPV4ADDR ...

  • Intel 324632-003 - page 398

    Intel ® 82575EB Gigabit Ethernet Controller — Manageability MAC Address Low - MMAL (5910h + 8*n[n=0..3]; RW) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 398 January 2011 14.7.8 Manageability MAC Address Low - MMAL (5910h + 8*n[n=0..3]; RW) These registers contain the lower ...

  • Intel 324632-003 - page 399

    Flexible TCO Filter Table Registers - FTFT (09400h-097FCh; RW) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 399 Each 128-byte filter is composed of 32 Dword entries, where each two Dwords are accompanied by an 8-bit ...

  • Intel 324632-003 - page 400

    Intel ® 82575EB Gigabit Ethernet Controller — Legacy Sensor Polling Mask 1...8 Register (F8h:FFh) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 400 January 2011 14.7.11 Legacy Sensor Polling Mask 1...8 Register (F8h:FFh) This register provides software an interface for the 8 ...

  • Intel 324632-003 - page 401

    PCIe* Control - GCR (05B00h; R) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 401 L0s_Entry_Lat 24 0b L0s Entry Latency Set to 0b to indicate L0s entry latency is the same as L0s exit latency. Set to 1b to indicate L0 ...

  • Intel 324632-003 - page 402

    Intel ® 82575EB Gigabit Ethernet Controller — PCIe* Control - GCR (05B00h; R) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 402 January 2011 Completion_ Timeout_Value (RO or RW1) 15:12 0h Indicates the selected value for completion timeout (after an Internal_Power_On_Reset). ...

  • Intel 324632-003 - page 403

    Function Tag - FUNCTAG (05B08h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 403 14.8.2 Function Tag - FUNCTAG (05B08h; R/W) 14.8.3 PCIe* Statistics Control #1 - GSCL_1 (05B10h; R) 14.8.4 PCIe* Statistics Contro ...

  • Intel 324632-003 - page 404

    Intel ® 82575EB Gigabit Ethernet Controller — PCIe* Statistics Control #2 - GSCL_2 (05B14h; R) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 404 January 2011 Table 92 lists the encoding of the events. Table 92. Event Encodings Field Bit(s) Initial Value Description GIO_EVENT_ ...

  • Intel 324632-003 - page 405

    PCIe* Statistics Control #2 - GSCL_2 (05B14h; R) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 405 Clock counter 20 Counts GIO cycles. Bad TLP from LL 21 Each cycle, the counter increases by one, if bad TLP is receive ...

  • Intel 324632-003 - page 406

    Intel ® 82575EB Gigabit Ethernet Controller — PCIe* Statistics Control #2 - GSCL_2 (05B14h; R) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 406 January 2011 Average latency of read request – from initialization until end of completions. Estimated latency is ~5  s. 40 + ...

  • Intel 324632-003 - page 407

    PCIe* Statistics Control #3 - GSCL_3 (05B18h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 407 14.8.5 PCIe* Statistics Control #3 - GSCL_3 (05B18h; R/W) This counter holds the threshold values needed for some of ...

  • Intel 324632-003 - page 408

    Intel ® 82575EB Gigabit Ethernet Controller — PCIe* Counter #2 - GSCN_2 (05B28h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 408 January 2011 14.8.9 PCIe* Counter #2 - GSCN_2 (05B28h; R/W) 14.8.10 PCIe* Counter #3 - GSCN_3 (05B2Ch; R/W) 14.8.11 Function Active and Powe ...

  • Intel 324632-003 - page 409

    SerDes/CCM/PCIe* CSR - GIOANACTL0 (05B34h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 409 14.8.12 SerDes/CCM/PCIe* CSR - GIOANACTL0 (05B34h; R/W) Firmware uses this register for analog circuit configuration. 1 ...

  • Intel 324632-003 - page 410

    Intel ® 82575EB Gigabit Ethernet Controller — GIOANACTL3 (05B40h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 410 January 2011 14.8.15 GIOANACTL3 (05B40h; R/W) Firmware uses this register for analog circuit configuration. 14.8.16 SerDes/CCM/PCIe* CSR - GIOANACTLALL (05 ...

  • Intel 324632-003 - page 411

    Software Semaphore - SWSM (05B50h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 411 14.8.19 Software Semaphore - SWSM (05B50h; R/W) 14.8.20 Firmware Semaphore - FWSM (05B58h; R/WS) Field Bit(s) Initial Value Des ...

  • Intel 324632-003 - page 412

    Intel ® 82575EB Gigabit Ethernet Controller — Firmware Semaphore - FWSM (05B58h; R/WS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 412 January 2011 PHY_SERDES1_ Config_Err_Ind 27 0h PHY/SerDes1 configuration error indication Set to 1b by firmware when it fails to configure ...

  • Intel 324632-003 - page 413

    Software-Firmware Synchronization - SW_FW_SYNC (05B5Ch; R/WS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 413 Notes: 1. This register should be written only by the manageability firmware. The device driver should on ...

  • Intel 324632-003 - page 414

    Intel ® 82575EB Gigabit Ethernet Controller — Software-Firmware Synchronization - SW_FW_SYNC (05B5Ch; R/WS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 414 January 2011 Software and firmware synchronize accesses to shared resources in the 82575 through a semaphore mechanism ...

  • Intel 324632-003 - page 415

    Mirrored Revision ID - MREVID (05B64h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 415 14.8.22 Mirrored Revision ID - MREVID (05B64h; R/W) 14.8.23 MSI-X PBA Clear - PBACL (05B68h; R/W1C) 14.8.24 DCA Requester I ...

  • Intel 324632-003 - page 416

    Intel ® 82575EB Gigabit Ethernet Controller — DCA Control - DCA_CTRL (05B74h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 416 January 2011 14.8.25 DCA Control - DCA_CTRL (05B74h; R/W) Note: The DCA tag disabled value in data movement engine 2 mode in the 82575 A0 is 11 ...

  • Intel 324632-003 - page 417

    Alignment Error Count - ALGNERRC (04004h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 417 14.9.2 Alignment Error Count - ALGNERRC (04004h; RC) Counts the number of receive packets with alignment errors (the pack ...

  • Intel 324632-003 - page 418

    Intel ® 82575EB Gigabit Ethernet Controller — Single Collision Count - SCC (04014h; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 418 January 2011 14.9.6 Single Collision Count - SCC (04014h; RC) This register counts the number of times that a successfully transmitted pac ...

  • Intel 324632-003 - page 419

    Defer Count - DC (04030h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 419 14.9.11 Defer Count - DC (04030h; RC) This register counts defer events. A defer event occurs when the transmitter cannot immediately sen ...

  • Intel 324632-003 - page 420

    Intel ® 82575EB Gigabit Ethernet Controller — XON Transmitted Count - XONTXC (0404Ch; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 420 January 2011 14.9.15 XON Transmitted Count - XONTXC (0404Ch; RC) This register counts the number of XON packets transmitted. These can b ...

  • Intel 324632-003 - page 421

    Packets Received (64 Bytes) Count - PRC64 (0405Ch; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 421 14.9.19 Packets Received (64 Bytes) Count - PRC64 (0405Ch; RC) This register counts the number of good packets r ...

  • Intel 324632-003 - page 422

    Intel ® 82575EB Gigabit Ethernet Controller — Packets Received (512-1023 Bytes) Count - PRC1023 (0406Ch; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 422 January 2011 14.9.23 Packets Received (512-1023 Bytes) Count - PRC1023 (0406Ch; RC) This register counts the number o ...

  • Intel 324632-003 - page 423

    Broadcast Packets Received Count - BPRC (04078h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 423 14.9.26 Broadcast Packets Received Count - BPRC (04078h; RC) This register counts the number of good (no errors) b ...

  • Intel 324632-003 - page 424

    Intel ® 82575EB Gigabit Ethernet Controller — Good Octets Received Count - GORCL (04088h; RC)/GORCH (0408Ch; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 424 January 2011 14.9.29 Good Octets Received Count - GORCL (04088h; RC)/GORCH (0408Ch; RC) These registers make up a ...

  • Intel 324632-003 - page 425

    Receive Undersize Count - RUC (040A4h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 425 14.9.32 Receive Undersize Count - RUC (040A4h; RC) This register counts the number of received frames that passed address fi ...

  • Intel 324632-003 - page 426

    Intel ® 82575EB Gigabit Ethernet Controller — Management Packets Received Count - MNGPRC (040B4h; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 426 January 2011 Packets over 1518/1522/1526 bytes are oversized if LPE is 0b. If LPE is 1b, then an incoming packet is consider ...

  • Intel 324632-003 - page 427

    Total Octets Received - TORL (040C0h; RC) / TORH (040C4h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 427 14.9.39 Total Octets Received - TORL (040C0h; RC) / TORH (040C4h; RC) These registers make up a logical 6 ...

  • Intel 324632-003 - page 428

    Intel ® 82575EB Gigabit Ethernet Controller — Total Packets Transmitted - TPT (040D4h; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 428 January 2011 14.9.42 Total Packets Transmitted - TPT (040D4h; RC) This register counts the total number of all packets transmitted. All ...

  • Intel 324632-003 - page 429

    Packets Transmitted (128-255 Bytes) Count - PTC255 (040E0h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 429 14.9.45 Packets Transmitted (128-255 Bytes) Count - PTC255 (040E0h; RC) This register counts the number ...

  • Intel 324632-003 - page 430

    Intel ® 82575EB Gigabit Ethernet Controller — Multicast Packets Transmitted Count - MPTC (040F0h; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 430 January 2011 Due to changes in the standard for maximum frame size for VLAN tagged frames in 802.3, the 82575 transmits pack ...

  • Intel 324632-003 - page 431

    Interrupt Assertion Count - IAC (04100h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 431 14.9.52 Interrupt Assertion Count - IAC (04100h; RC) This counter counts the total number of LAN interrupts generated in t ...

  • Intel 324632-003 - page 432

    Intel ® 82575EB Gigabit Ethernet Controller — SerDes/SGMII Code Violation Packet Count - SCVPC (04228h; R/WS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 432 January 2011 14.9.57 SerDes/SGMII Code Violation Packet Count - SCVPC (04228h; R/WS) This register contains the numb ...

  • Intel 324632-003 - page 433

    Receive Data FIFO Head Saved Register - RDFHS (02420h; RO) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 433 14.10.3 Receive Data FIFO Head Saved Register - RDFHS (02420h; RO) This register stores a copy of the Receiv ...

  • Intel 324632-003 - page 434

    Intel ® 82575EB Gigabit Ethernet Controller — PB Descriptor Read Pointers - PBDESCRP (02454h; RO) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 434 January 2011 14.10.6 PB Descriptor Read Pointers - PBDESCRP (02454h; RO) 14.10.7 Packet Buffer Diagnostic - PBDIAG (02458h; R/ W ...

  • Intel 324632-003 - page 435

    Transmit Data FIFO Tail Register - TDFT (03418h; R/WS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 435 14.10.9 Transmit Data FIFO Tail Register - TDFT (03418h; R/WS) This register stores the head of the on–chip tr ...

  • Intel 324632-003 - page 436

    Intel ® 82575EB Gigabit Ethernet Controller — Transmit Data FIFO Packet Count - TDFPC (03430h; RO) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 436 January 2011 14.10.12 Transmit Data FIFO Packet Count - TDFPC (03430h; RO) This register reflects the number of packets to be t ...

  • Intel 324632-003 - page 437

    Tx Descriptor Handler ECC Error Inject - TDHEEI (035F8h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 437 14.10.14 Tx Descriptor Handler ECC Error Inject - TDHEEI (035F8h; R/W) 14.10.15 Rx Descriptor Handler ECC ...

  • Intel 324632-003 - page 438

    Intel ® 82575EB Gigabit Ethernet Controller — Packet Buffer Memory - PBM (10000h - 10FFCh; R/ W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 438 January 2011 14.10.16 Packet Buffer Memory - PBM (10000h - 10FFCh; R/W) All PBM (FIFO) data is available to diagnostics. Location ...

  • Intel 324632-003 - page 439

    Tx Descriptor Handler Memory Page Number - TDHMP (035FCh; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 439 Note: The queue depth field must be updated before the receive queues are enabled (before writing to any ...

  • Intel 324632-003 - page 440

    Intel ® 82575EB Gigabit Ethernet Controller — Packet Buffer ECC Status - PBECCSTS (0245Ch; R/ W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 440 January 2011 14.10.20 Packet Buffer ECC Status - PBECCSTS (0245Ch; R/W) 14.10.21 Rx Descriptor Handler ECC Status - RDHESTS (0246 ...

  • Intel 324632-003 - page 441

    Tx Descriptor Handler ECC Status - TDHESTS (0246Ch; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 441 14.10.22 Tx Descriptor Handler ECC Status - TDHESTS (0246Ch; R/W) 14.11 Packet Generator Registers This sectio ...

  • Intel 324632-003 - page 442

    Intel ® 82575EB Gigabit Ethernet Controller — Packet Generator Source Address Low - PGSAL (04288h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 442 January 2011 14.11.3 Packet Generator Source Address Low - PGSAL (04288h; R/W) 14.11.4 Packet Generator Source Address Hig ...

  • Intel 324632-003 - page 443

    Packet Generator Packet Length - PGPL (04294h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 443 14.11.6 Packet Generator Packet Length - PGPL (04294h; R/W) The actual boundaries for the packet size are the sizes ...

  • Intel 324632-003 - page 444

    Intel ® 82575EB Gigabit Ethernet Controller — Packet Generator StaPGSTS Bit Description Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 444 January 2011 14.11.8 Packet Generator StaPGSTS Bit Description 14.11.9 Packet Generator ContPGCTL Bit Description Field Bit(s) Initial Val ...

  • Intel 324632-003 - page 445

    MSI-X Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 445 14.12 MSI-X Registers These registers are used to configure the MSI-X mechanism. The address and upper address registers sets the address for each of t ...

  • Intel 324632-003 - page 446

    Intel ® 82575EB Gigabit Ethernet Controller — MSI-X Table Entry Lower Address - MSIXTADD (00000h - 00090h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 446 January 2011 14.12.1 MSI-X Table Entry Lower Address - MSIXTADD (00000h - 00090h; R/W) 14.12.2 MSI-X Table Entry U ...

  • Intel 324632-003 - page 447

    MSI-X Pending Bit Array - MSIXPBA Bit Description — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 447 14.12.5 MSI-X Pending Bit Array - MSIXPBA Bit Description § § Field Bit(s) Initial Value Description Pending Bits 9 ...

  • Intel 324632-003 - page 448

    Intel ® 82575EB Gigabit Ethernet Controller — MSI-X Pending Bit Array - MSIXPBA Bit Description Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 448 January 2011 NOTE: This page intentionally left blank. ...

  • Intel 324632-003 - page 449

    Diagnostics and Testability — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 449 15.0 Diagnostics and Testability 15.1 Diagnostics To assist in test and debug of device-driver software, a set of software-usable features ...

  • Intel 324632-003 - page 450

    Intel ® 82575EB Gigabit Ethernet Controller — Testability Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 450 January 2011 • MAC Loopback while operating with the internal PHY. • MAC Loopback, by setting the LBM bits in RCTL register to 11b. • Loopback - 10/100/1000BASE-T ...

  • Intel 324632-003 - page 451

    BYPASS Instruction — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 451 15.2.4 BYPASS Instruction This instruction is the only instruction defined by the standard that causes operation of the bypass register. The bypass ...

  • Intel 324632-003 - page 452

    Intel ® 82575EB Gigabit Ethernet Controller — BYPASS Instruction Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 452 January 2011 NOTE: This page intentionally left blank. ...

  • Intel 324632-003 - page 453

    Statistics — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 453 16.0 Statistics The 82575 supports different statistics counters as described in Section 14.0 . The statistics can be used to create statistics reports acco ...

  • Intel 324632-003 - page 454

    Intel ® 82575EB Gigabit Ethernet Controller — OID_GEN_STATISTICS Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 454 January 2011 A part of the optional package is also implemented as listed in the following table: 16.2 OID_GEN_STATISTICS The 82575 supports the part of the OID_ ...

  • Intel 324632-003 - page 455

    RMON — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 455 16.3 RMON The 82575 supports the part of the RMON Ethernet statistics group as defined by IETF RFC 2819. The following table lists the matching between the intern ...

  • Intel 324632-003 - page 456

    Intel ® 82575EB Gigabit Ethernet Controller — Linux net_device_stats Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 456 January 2011 § § tx_bytes GOTCL + GOTCH rx_errors CRCERRS + RLEC + RXERRC tx_errors ECOL + LATECOL rx_dropped N/A tx_dropped N/A multicast MPTC collisions ...

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All of them are important, but the most important information from the point of view of use of the device are in the user manual Intel 324632-003.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Intel 324632-003, service manual, brief instructions and user manuals Intel 324632-003. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Intel 324632-003.

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A complete manual for the device Intel 324632-003, how should it look like?
A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Intel 324632-003 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Intel 324632-003.

A complete Intel manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

1. Preface and tips on how to use the manual Intel 324632-003 - At the beginning of each manual we should find clues about how to use the guidelines. It should include information about the location of the Contents of the Intel 324632-003, FAQ or common problems, i.e. places that are most often searched by users in each manual
2. Contents - index of all tips concerning the Intel 324632-003, that we can find in the current document
3. Tips how to use the basic functions of the device Intel 324632-003 - which should help us in our first steps of using Intel 324632-003
4. Troubleshooting - systematic sequence of activities that will help us diagnose and subsequently solve the most important problems with Intel 324632-003
5. FAQ - Frequently Asked Questions
6. Contact detailsInformation about where to look for contact to the manufacturer/service of Intel 324632-003 in a specific country, if it was not possible to solve the problem on our own.

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