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Manual Cypress CY7C1382DV25

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  • Cypress CY7C1382DV25 - page 1

    18-Mbit (512K x 36/1M x 18) Pipelined SRAM CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Cypress Semiconductor Co rporation • 198 Champion Court • San J ose , CA 95134-1709 • 408-943-2600 Document #: 38-05546 Rev . *E Revised Feburary 15, 2007 Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, a ...

  • Cypress CY7C1382DV25 - page 2

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 2 of 29 Logic Block Diagram – CY7C1380DV25 /CY7C1380FV25 [3 ] (512K x 36) Logic Block Diagram – CY7C1382DV25 /CY7C1382FV25 [3 ] (1M x 18) ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BWE GW CE 1 CE 2 CE 3 OE ENABLE REGISTER OUTP ...

  • Cypress CY7C1382DV25 - page 3

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 3 of 29 Pin Configurations A A A A A 1 A 0 NC/72M NC/36M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQc V DDQ V ...

  • Cypress CY7C1382DV25 - page 4

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 4 of 29 Pin Configurations (continued) 234 567 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ AA DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS V SS ...

  • Cypress CY7C1382DV25 - page 5

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 5 of 29 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1380DV25 (512 K x 36) 234 5 67 1 A B C D E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D ...

  • Cypress CY7C1382DV25 - page 6

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 6 of 29 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one of the address loca tions . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 [2] are sampled active. A ...

  • Cypress CY7C1382DV25 - page 7

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 7 of 29 Functional Overview All synchronous inpu ts pass through input registers controlle d by the rising edge of th e clock. All data outputs pass through output registers controlled by the risin g edge of the clock. Maximum access delay from the clock rise ( ...

  • Cypress CY7C1382DV25 - page 8

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 8 of 29 ADSP triggered write accesses require two cl ock cycles to complete. If GW is asserted LOW on the seco nd clock rise, the data presented to the DQs inputs is written into the corresponding address location in the me mory array . If GW is HIGH, then the ...

  • Cypress CY7C1382DV25 - page 9

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 9 of 29 T ruth T able [4, 5, 6, 7, 8] Operation Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Pow er Down None H X X L X L X X X L-H T ri-St a te Deselect Cycle, Pow er Down None L L X L L X X X X L-H T ri-St a te Deselect Cycle, Pow ...

  • Cypress CY7C1382DV25 - page 10

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 10 of 29 T ruth T able for Read/W rite [6, 9] Function (CY7C1380DV25/CY7C 1380FV25) GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte A – (DQ A and DQP A ) H L HHH L Write Byte B – (DQ B and DQP B )H L H H L H Write Bytes B, A H L H H L ...

  • Cypress CY7C1382DV25 - page 11

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 1 1 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1380DV25/C Y7C1382DV25 incorpo rates a serial boundary scan test access port (T AP). This part is fully compliant with 1 149.1. T he T AP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. The ...

  • Cypress CY7C1382DV25 - page 12

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 12 of 29 Byp ass Register T o save time wh en serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed betwee n the TDI and TDO balls. This allows data to be sh ...

  • Cypress CY7C1382DV25 - page 13

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 13 of 29 instruction. When HIGH, it will en able the output bu ffers to drive the output bus. When LOW , this bit will place the output bus into a High-Z condition. This bit can be set by enterin g the SAMPLE/PRELOAD or EXTEST command, and th en shifting the de ...

  • Cypress CY7C1382DV25 - page 14

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 14 of 29 2.5V T AP AC T est Conditions Input pulse levels .......... .............. ................. ........V SS to 2.5V Input rise and fall time .............. ............ ........... ................ 1 ns Input timing reference levels ..................... ...

  • Cypress CY7C1382DV25 - page 15

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 15 of 29 Identification Codes Instruction Code Description EXTEST 0 00 Captures IO ri ng contents. Places th e boundary scan register between T DI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 L oads the ID register with the vendor ID code and pl ...

  • Cypress CY7C1382DV25 - page 16

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 16 of 29 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N 7 3 2 C 1 1 6 2 D 2 3 N10 33 A1 1 63 E2 4P 1 1 3 4 B 1 1 6 4 F 2 5 P 8 35 A 10 65 G2 6 R8 36 B10 66 H1 7R 9 3 7 A 9 6 7 H 3 8P 9 3 8 B 9 6 8 J 1 9P ...

  • Cypress CY7C1382DV25 - page 17

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 17 of 29 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guideline s, not tested. S torage T emperature .............. .............. ..... –65 ° C to +150 ° C Ambient T emperature wit h Power Applied ....... ...

  • Cypress CY7C1382DV25 - page 18

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 18 of 29 Cap acit ance [18] Parameter Descrip tion T est Conditions 100 TQFP Package 1 19 BGA Package 165 FBGA Package Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD /V DDQ = 2.5V 5 8 9 pF C CLK Clock Input Capacitance 5 8 9 pF C IO Input/Outp ut Ca ...

  • Cypress CY7C1382DV25 - page 19

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 19 of 29 Switching Characteristics Over the Operating Range [19, 20] Parameter Descriptio n 250 MHz 200 MHz 167 MHz Unit Min. Max Min. M ax. Min. Max t POWER V DD (T ypical) to the First Access [21] 1 11 ms Clock t CYC Clock Cycle T ime 4.0 56 ns t CH Clock HIG ...

  • Cypress CY7C1382DV25 - page 20

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 20 of 29 Switching W aveforms Read Cycle Timing [25] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BWx Data Out (Q) High-Z t CLZ t DOH t CO ADV t OEHZ t CO Single READ BURST READ t OEV t OELZ t CHZ ADV suspends burst. ...

  • Cypress CY7C1382DV25 - page 21

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 21 of 29 Write Cycle T iming [25, 26] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW X Data Out (Q) High-Z ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A ...

  • Cypress CY7C1382DV25 - page 22

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 22 of 29 Read/Write Cycle Timing [25, 27, 28] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CES BWE, BW X Data Out (Q) High-Z ADV Single WRITE D(A3) A4 A5 A6 D(A5) D(A6) Data In (D) BURST READ Bac ...

  • Cypress CY7C1382DV25 - page 23

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 23 of 29 ZZ Mode T iming [29, 30] Switching W aveforms (continued ) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes: 29. Device must be deselected when entering ZZ sleep mode. S ...

  • Cypress CY7C1382DV25 - page 24

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 24 of 29 Ordering Information Not all of the speed, package, and temperature ranges are available. Plea se contact your local sales representative or visit www .cypress.com for actual pr oducts offered. Spee d (MHz) Ordering Co de Package Diagram Part and Packa ...

  • Cypress CY7C1382DV25 - page 25

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 25 of 29 250 CY7C1380DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (1 4 x 20 x 1.4 mm) Pb-Free Commercial CY7C1382DV25-250AXC CY7C1380FV25-250BGC 5 1-851 15 1 19-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1382FV25-250BGC CY7C1380FV25-250BGXC 5 1-851 15 1 19 ...

  • Cypress CY7C1382DV25 - page 26

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 26 of 29 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-085050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 m ...

  • Cypress CY7C1382DV25 - page 27

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 27 of 29 Figure 2. 1 19-Ball BGA ( 14 x 22 x 2.4 mm) (51-85 1 15) Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.00(3X) R ...

  • Cypress CY7C1382DV25 - page 28

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 28 of 29 © Cypress Semicon ductor Corporati on, 2006-2007. Th e information contained her ein is subject to ch ange without no tice. Cypress S emiconductor Corporatio n assumes no responsibility for the use of any circuitry o ther than circuitry em bodied in a ...

  • Cypress CY7C1382DV25 - page 29

    CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev . *E Page 29 of 29 Document History Page Document Title: CY7C1380DV25/CY7C1382 DV25/CY7C 1380FV25/CY7C138 2FV25, 18-Mb it (512K x 36/1M x 18 ) Pipelined SRAM Document Number: 38-05546 REV . EC N NO. Issue Date Orig. of Change Description of Change ** 254515 See ECN RKF N ...

Manufacturer Cypress Category Computer Hardware

Documents that we receive from a manufacturer of a Cypress CY7C1382DV25 can be divided into several groups. They are, among others:
- Cypress technical drawings
- CY7C1382DV25 manuals
- Cypress product data sheets
- information booklets
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All of them are important, but the most important information from the point of view of use of the device are in the user manual Cypress CY7C1382DV25.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Cypress CY7C1382DV25, service manual, brief instructions and user manuals Cypress CY7C1382DV25. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Cypress CY7C1382DV25.

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A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Cypress CY7C1382DV25 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Cypress CY7C1382DV25.

A complete Cypress manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

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2. Contents - index of all tips concerning the Cypress CY7C1382DV25, that we can find in the current document
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4. Troubleshooting - systematic sequence of activities that will help us diagnose and subsequently solve the most important problems with Cypress CY7C1382DV25
5. FAQ - Frequently Asked Questions
6. Contact detailsInformation about where to look for contact to the manufacturer/service of Cypress CY7C1382DV25 in a specific country, if it was not possible to solve the problem on our own.

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