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Manual Texas Instruments TMS380C26

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  • Texas Instruments TMS380C26 - page 1

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Copyright  1993, T exas Instruments Incorporated 1 • IEEE 802.5 and IBM T oken-Ring Network Compatible • IEEE 802.3 and Blue Book Ethernet Network Compatible • Pin and Software Compatible With the TMS380C16 • Co ...

  • Texas Instruments TMS380C26 - page 2

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 2 pinout The pin assignments for TMS380C26 (132-pin quad flat-pack) are shown in Figure 1. 132-PIN QUAD FLA T P ACK (TOP VIEW) V SSC MRAS MW MCAS MAX2 MAX0 MDDIR V DD2 SYNCIN OSCIN V SS2 MROMEN MACS MAL MREF MBIAEN V DDL M ...

  • Texas Instruments TMS380C26 - page 3

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 description The TMS380C26 is a single-chip network communications processor (commprocessor) that supports token ring, or Ethernet Local Area Networks (LANs). Either token ring at data rates of 16 Mbps or 4 Mbps, or Ether ...

  • Texas Instruments TMS380C26 - page 4

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 4 block diagram and signal descriptions TMS380C26 has a bus interface to the host system, a bus interface to local memory , and an interface to the physical layer circuitry . As a rule of thumb in the pin nomenclature and ...

  • Texas Instruments TMS380C26 - page 5

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 T erminal Functions PIN NAME NO. I/O DESCRIPTION BTSTRP 23 IN Bootstrap. The value on this pin is loaded into the BOOT bit of the SIF ACL register at reset (i.e., when the SRESET pin is asserted or the ARESET bit in the ...

  • Texas Instruments TMS380C26 - page 6

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 6 T erminal Functions (continued) PIN NAME NO. I/O DESCRIPTION MAXPH 130 I/O Local Memory Extended Address and Parity High Byte. For the first quarter of a memory cycle this signal carries the extended address bit (AX1); f ...

  • Texas Instruments TMS380C26 - page 7

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 T erminal Functions (continued) PIN NAME NO. I/O DESCRIPTION MOE 11 8 OUT Memory Output Enable. This signal is used to enable the outputs of the DRAM memory during a read cycle. This signal is high for EPROM or BIA ROM r ...

  • Texas Instruments TMS380C26 - page 8

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 8 T erminal Functions (continued) PIN NAME NO. I/O DESCRIPTION PRTYEN 22 IN Parity Enable. The value on this pin is loaded into the PEN bit of the SIF ACL register at reset (i.e., when the SRESET pin is asserted or the ARE ...

  • Texas Instruments TMS380C26 - page 9

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 T erminal Functions (continued) System Interface – Intel Mode (SI/M =H ) PIN NAME NO. I/O DESCRIPTION SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 73 72 71 70 69 68 64 63 I/O System Address/Data Bus—high byte (see ...

  • Texas Instruments TMS380C26 - page 10

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 T erminal Functions (continued) System Interface – Intel Mode (SI/M =H ) PIN NAME NO. I/O DESCRIPTION SDDIR 38 OUT System Data Direction. This output provides to the external data buffers a signal indicating the direc ...

  • Texas Instruments TMS380C26 - page 11

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 T erminal Functions (continued) System Interface – Intel Mode (SI/M =H ) PIN NAME NO. I/O DESCRIPTION SRAS /SAS 39 I/O System Memory Address Strobe (see Note 3). This pin used to latch the SCS , SRSX – SRS2 register ...

  • Texas Instruments TMS380C26 - page 12

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 12 T erminal Functions (continued) System Interface – Intel Mode (SI/M =H ) PIN NAME NO. I/O DESCRIPTION SYNCIN 108 IN Reserved. This signal must be left unconnected (see Note 1). S8 /SHAL T 32 IN System 8/16-bit bus sel ...

  • Texas Instruments TMS380C26 - page 13

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 T erminal Functions (continued) System Interface – Motorola Mode (SI/M =L ) PIN NAME NO. I/O DESCRIPTION SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 73 72 71 70 69 68 64 63 I/O System Address/Data Bus—high byte ...

  • Texas Instruments TMS380C26 - page 14

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 14 T erminal Functions (continued) System Interface – Motorola Mode (SI/M =L ) PIN NAME NO. I/O DESCRIPTION SDDIR 38 OUT System Data Direction. This output provides to the external data buffers a signal indicating the di ...

  • Texas Instruments TMS380C26 - page 15

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 T erminal Functions (continued) System Interface – Motorola Mode (SI/M =L ) PIN NAME NO. I/O DESCRIPTION SRD/ SUDS 61 I/O Upper Data Strobe (see Note 3). This pin serves as the active-low upper data strobe. This pin i ...

  • Texas Instruments TMS380C26 - page 16

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 16 T erminal Functions (continued) Network Media Interface – T oken-Ring Mode (TEST1 = H, TEST2 = H) PIN NAME NO. I/O DESCRIPTION DRVR DRVR 89 88 OUT Differential Driver Data Output. These pins are the differential outpu ...

  • Texas Instruments TMS380C26 - page 17

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 T erminal Functions (continued) Network Media Interface – Ethernet Mode (TEST1 = L, TEST2 = H) PIN NAME NO. I/O DESCRIPTION DRVR DRVR 89 88 OUT These pins have no Ethernet function. In Ethernet Mode these pins are pla ...

  • Texas Instruments TMS380C26 - page 18

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 18 T erminal Functions (continued) PIN NAME NO. I/O DESCRIPTION TEST 0 TEST 1 TEST 2 79 78 77 IN IN IN Network Select inputs. These pins are used to select the network speed and type to be used by the TMS380C26. These inpu ...

  • Texas Instruments TMS380C26 - page 19

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 T erminal Functions (continued) PIN NAME NO. I/O DESCRIPTION V SSL 17 83 IN Ground reference for digital logic. All V SS pins must be attached to the common system ground plane. V SS1 V SS2 V SS3 V SS4 V SS5 V SS6 91 10 ...

  • Texas Instruments TMS380C26 - page 20

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 20 architecture The major blocks of the TMS380C26 include the Communications Processor (CP), System Interface (SIF), Memory Interface (MIF), Protocol Handler (PH), Clock Generator (CG), and the Adapter Support Function (AS ...

  • Texas Instruments TMS380C26 - page 21

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 On every cycle the system interface compares all the system clocks to a reference clock. If any of the clocks become invalid, the TMS380C26 enters the slow clock mode, which prevents latchup of the TMS380C26. If the SBC ...

  • Texas Instruments TMS380C26 - page 22

    NOTE: The Adapter-Internal Pointers T able is defined only after TMS380C26 initialization and until the OPEN command is issued. These pointers are defined by the TMS380C26 software (microcode), and this table describes the release 1.00 and 2.x software. TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 ...

  • Texas Instruments TMS380C26 - page 23

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 Adapter-Internal Pointers for T oken-Ring † ADDRESS DESCRIPTION >00.FFF8 ‡ Pointer to software raw microcode level in chapter 0. >00.FFF A ‡ Pointer to starting location of copyright notices. Copyright notic ...

  • Texas Instruments TMS380C26 - page 24

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 24 Adapter-Internal Pointers for Ethernet † ADDRESS DESCRIPTION >00.FFF8 ‡ Software raw microcode level in chapter 0. >00.FFF A ‡ Pointer to starting location of copyright notices. Copyright notices are separat ...

  • Texas Instruments TMS380C26 - page 25

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 User-Access Hardware Registers 808x 16-Bit Mode: (SI/M = 1, S8/SHAL T = 0) † Word T ransfers Normal Mode SBHE = 0 SRS2 = 0 Pseudo-DMA Mode Active SBHE = 0 SRS2 = 0 Byte T ransfers SBHE = 0 SBHE = 1 SRS2 = 1 SRS2 = 0 S ...

  • Texas Instruments TMS380C26 - page 26

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 26 SIF Adapter Control Register (SIF ACL) The SIF ACL register allows the host processor to control and to some extent reconfigure the TMS380C26 under software control. SIF ACL Register Bit # 0 1 2 3 4 5 6 7 8 9 10 1 1 12 ...

  • Texas Instruments TMS380C26 - page 27

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 Bit 6: SWHRQ — Current SHRQ Signal V alue This bit contains the current value on the SHRQ/SBRQ pin when in Intel mode, and the inverse of the SHRQ/SBRQ pin when in Motorola mode. This enables the host to easily determ ...

  • Texas Instruments TMS380C26 - page 28

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 28 Bit 12: SINTEN — System-Interrupt Enable This bit allows the host processor to enable or disable system interrupt requests from the TMS380C26. The system interrupt request from the TMS380C26 is on the SINTR/SIRQ pin. ...

  • Texas Instruments TMS380C26 - page 29

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 SIF ACL Control for Pseudo-DMA Operation Pseudo-DMA is software controlled by the use of five bits in the SIF ACL register . The logic model for the SIF ACL register control of pseudo-DMA operation is shown in Figure 3. ...

  • Texas Instruments TMS380C26 - page 30

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 30 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) † Supply voltage range, V DD (see Note 6) 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Texas Instruments TMS380C26 - page 31

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 P ARAMETER MEASUREMENT INFORMA TION Outputs are driven to a minimum high-logic level of 2.4 volts and to a maximum low-logic level of 0.6 volts. These levels are compatible with TTL devices. Output transition times are ...

  • Texas Instruments TMS380C26 - page 32

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 32 P ARAMETER MEASUREMENT INFORMA TION OSCIN OSCOUT MBCLK1 † MBCLK2 † 4 Periods 8 Periods 12 Periods 16 Periods 20 Periods When CLKDIV = 1 Reference † The MBCLK1 and MBCLK2 signals have no timing relationship to the ...

  • Texas Instruments TMS380C26 - page 33

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 P ARAMETER MEASUREMENT INFORMA TION timing parameters The timing parameters for all the pins of TMS380C26 are shown in the following tables and are illustrated in the accompanying figures. The purpose of these figures a ...

  • Texas Instruments TMS380C26 - page 34

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 34 P ARAMETER MEASUREMENT INFORMA TION power up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN , and SRESET timing NO. P ARAMETER MIN MAX UNIT 100 † t r(VDD ) Rise time from 1.2 V to V DD minimum high level 1 ms 101 †‡ t d(VD ...

  • Texas Instruments TMS380C26 - page 35

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 P ARAMETER MEASUREMENT INFORMA TION S8/SHAL T SRESET MBCLK2 MBCLK1 OSCIN SBCLK V DD 288 289 11 9 11 0 109 11 0 108 107 106 106 100 Minimun V DD High Level 104 105 103 102 101 11 7 11 8 111 NOTE A: In order to represent ...

  • Texas Instruments TMS380C26 - page 36

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 36 P ARAMETER MEASUREMENT INFORMA TION memory bus timing: clocks, MAL , MROMEN , MBIAEN , NMI , MRESET , and ADDRESS t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. P ARAMETER MIN MAX UNI ...

  • Texas Instruments TMS380C26 - page 37

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 P ARAMETER MEASUREMENT INFORMA TION MAL MAXPH, MAXPL, MADL0–MADL7 MAX0, MAX2, MROMEN MBCLK2 MBCLK1 Address Col Row Address ADD/EN 11 10 9 8 14 13 12 2 3 1 2 1 7 6 5 4 MADH0–MADH7 NMI MRESET 120 121 126 Status 129 t ...

  • Texas Instruments TMS380C26 - page 38

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 38 P ARAMETER MEASUREMENT INFORMA TION memory bus timing: clocks, MRAS , MCAS , and MAL to ADDRESS t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. P ARAMETER MIN MAX UNIT 15 Setup time of ...

  • Texas Instruments TMS380C26 - page 39

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 P ARAMETER MEASUREMENT INFORMA TION MADH0–MADH7 MAX0, MAX2, MROMEN MAL MCAS MRAS MAXPH, MAXPL, MADL0–MADL7 Row Column Column Row Address Status Status Address Address ADD/EN 31 30 28 29 24 26 27 25 20 21 16 19 15 20 ...

  • Texas Instruments TMS380C26 - page 40

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 40 P ARAMETER MEASUREMENT INFORMA TION memory bus timing: read cycle t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. P ARAMETER MIN MAX UNIT 32 Access time from address/enable valid on MA ...

  • Texas Instruments TMS380C26 - page 41

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 P ARAMETER MEASUREMENT INFORMA TION MDDIR MBEN MBIAEN MOE MCAS MRAS MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 MAX0, MAX2, MROMEN Address Enable Address/ Address Status Address/ Address Data/Parity 53 54 55 51 50 48 48a ...

  • Texas Instruments TMS380C26 - page 42

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 42 P ARAMETER MEASUREMENT INFORMA TION memory bus timing: write cycle t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. P ARAMETER MIN MAX UNIT 58 Setup time of MW low before MRAS no longer ...

  • Texas Instruments TMS380C26 - page 43

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 P ARAMETER MEASUREMENT INFORMA TION Data/Parity Out ADD/STS Address Address Enable Address/ MDDIR MBEN MW MCAS MRAS MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 MAX0, MAX2, MROMEN 60 63 64 58 72 73 71 70 69 67 66 65 Figur ...

  • Texas Instruments TMS380C26 - page 44

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 44 P ARAMETER MEASUREMENT INFORMA TION memory bus timing: TMS380C26 releases control of bus t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. P ARAMETER MIN MAX UNIT 74 Hold time of MIF out ...

  • Texas Instruments TMS380C26 - page 45

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 P ARAMETER MEASUREMENT INFORMA TION 78 77 76 75a 74a 75 74 75 74 75 74 MBCLK1 MBCLK2 MBEN MDDIR MAL MBIAEN MBRQ MBGR Figure 12. Memory Bus Timing: TMS380C26 Releases Control of Bus (continued) ...

  • Texas Instruments TMS380C26 - page 46

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 46 P ARAMETER MEASUREMENT INFORMA TION memory bus timing: TMS380C26 resumes control of bus t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. P ARAMETER MIN MAX UNIT 79 Hold time of MIF outp ...

  • Texas Instruments TMS380C26 - page 47

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 P ARAMETER MEASUREMENT INFORMA TION 80 79 80 79 80 79 80 79 80 79 80 79 MBCLK1 MAX0, MAX2, MOROMEN MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 MRAS MCAS MW MOE Figure 13. Memory Bus Timing: TMS380C26 Resumes Control of B ...

  • Texas Instruments TMS380C26 - page 48

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 48 P ARAMETER MEASUREMENT INFORMA TION 83 81 82 80 79 MBCLK1 MBCLK2 MBEN MDDIR MAL MBIAEN MBRQ MBGR 80 79 80 79 80 79 Figure 14. Memory Bus Timing: TMS380C26 Resumes Control of Bus (continued) ...

  • Texas Instruments TMS380C26 - page 49

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 49 P ARAMETER MEASUREMENT INFORMA TION memory bus timing: external bus master read from TMS380C26 t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. P ARAMETER MIN MAX UNIT 84 Setup time of ...

  • Texas Instruments TMS380C26 - page 50

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 50 P ARAMETER MEASUREMENT INFORMA TION 84 MBCLK1 MBCLK2 MAX0, MAX2 85 88 MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 Address In Data/Parity Address In Address In MDDIR MACS 86 87 Address In 89 90 91 93 92 95 94 Figure 15. M ...

  • Texas Instruments TMS380C26 - page 51

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 51 P ARAMETER MEASUREMENT INFORMA TION memory bus timing: external bus master write to TMS380C26 NO. P ARAMETER MIN MAX UNIT 96 Setup time of valid data/parity before MBCLK2 falling edge, external bus master write 21 ns 97 ...

  • Texas Instruments TMS380C26 - page 52

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 52 P ARAMETER MEASUREMENT INFORMA TION memory bus timing: DRAM refresh timing t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. P ARAMETER MIN MAX UNIT 15 Setup time of row address on MADL0 ...

  • Texas Instruments TMS380C26 - page 53

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 P ARAMETER MEASUREMENT INFORMA TION XMA TCH and XF AIL timing t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. P ARAMETER MIN MAX UNIT 127 Delay from status bit 7 high to XMA TCH and XF ...

  • Texas Instruments TMS380C26 - page 54

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 54 P ARAMETER MEASUREMENT INFORMA TION token ring — ring interface timing No. P ARAMETER MIN TYP MAX UNIT 153 Period of RCLK (see Note 14) 4Mbps 125 ns 153 Period of RCLK (see Note 14) 16 Mbps 31.25 ns 154L Pulse duratio ...

  • Texas Instruments TMS380C26 - page 55

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 P ARAMETER MEASUREMENT INFORMA TION token ring — transmitter timing (see Figure 20) NO. P ARAMETER MIN TYP MAX UNIT 159 Delay from DRVR rising edge (1.8 V) to DR VR falling edge (1.0 V) or DRVR falling edge (1.0 V) to ...

  • Texas Instruments TMS380C26 - page 56

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 56 P ARAMETER MEASUREMENT INFORMA TION ethernet timing of clock signals NO. P ARAMETER MIN TYP MAX UNIT 300 CLKPHS Pulse duration of TXC 45 ns 301 CLKPER Cycle time of TXC 95 1000 ns TXC 300 2.4 V 0.45 V 300 301 Figure 21. ...

  • Texas Instruments TMS380C26 - page 57

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 P ARAMETER MEASUREMENT INFORMA TION ethernet timing of RCV signals — start of frame NO. P ARAMETER MIN TYP MAX UNIT 310 RXDSET Setup of RXD before RXC no longer low 20 ns 31 1 RXDHLD Hold of RXD after RXC high 5 ns 31 ...

  • Texas Instruments TMS380C26 - page 58

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 58 P ARAMETER MEASUREMENT INFORMA TION ethernet timing of RCV signals — end of frame NO. P ARAMETER MIN TYP MAX UNIT 320 CRSSET Setup time of CRS low before RXC no longer low to determine if last data bit ”seen” on p ...

  • Texas Instruments TMS380C26 - page 59

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 P ARAMETER MEASUREMENT INFORMA TION ethernet timing of RCV signals — no RXC NO. P ARAMETER MIN TYP MAX UNIT 330 NORXC Time with no clock pulse on RXC, when CRS is high (see Note 19) 2 µ s NOTE 19: If NORXC is exceede ...

  • Texas Instruments TMS380C26 - page 60

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 60 P ARAMETER MEASUREMENT INFORMA TION ethernet timing of XMIT signals NO. P ARAMETER MIN TYP MAX UNIT 350 JAMTIM T ime from COLL sampled high (TXC high) to first transmitted ”JAM” bit on TXD (see Note 20) 4 cycles 351 ...

  • Texas Instruments TMS380C26 - page 61

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 P ARAMETER MEASUREMENT INFORMA TION 80x8x DIO read timing NO. P ARAMETER MIN MAX UNIT 255 Delay from SRDY low to either SCS or SRD high 15 ns 256 Pulse duration, SRAS high 30 ns 259 † Hold of SAD high-impedance after ...

  • Texas Instruments TMS380C26 - page 62

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 62 P ARAMETER MEASUREMENT INFORMA TION (High) Output Data V alid V alid (see Note A) V alid SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note B) SRDY † SDBEN SDDIR SRD SWR SIACK SRAS SCS , SRSX, SRS0–SRS2, SBHE 261 261a ...

  • Texas Instruments TMS380C26 - page 63

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 63 P ARAMETER MEASUREMENT INFORMA TION 80x8x DIO write timing NO. P ARAMETER MIN MAX UNIT 255 Delay from SRDY low to either SCS or SWR high 15 ns 256 Pulse duration, SRAS high 30 ns 262 Setup of SADH0–SADH7, SADL0–SADL ...

  • Texas Instruments TMS380C26 - page 64

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 64 P ARAMETER MEASUREMENT INFORMA TION (High) V alid Data SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note A) SRDY SDBEN † SDDIR SRD SWR SIACK SRAS SCS , SRSX, SRS0–SRS2, SBHE 262 276 267 266a 256 265 HI-Z HI-Z HI-Z HI ...

  • Texas Instruments TMS380C26 - page 65

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 65 P ARAMETER MEASUREMENT INFORMA TION 80x8x interrupt acknowledge timing – first SIACK pulse NO. P ARAMETER MIN MAX UNIT 286 Pulse duration, SIACK high between DIO accesses (see Note 21) 55 ns 287 Pulse duration, SIACK ...

  • Texas Instruments TMS380C26 - page 66

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 66 P ARAMETER MEASUREMENT INFORMA TION SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note A) SRDY † SDBEN SDDIR SRD SWR SIACK SCS , SRSX, SRS0–SRS2, SBHE Only SCS needs to be inactive. All others are Don’t Care. (High) ...

  • Texas Instruments TMS380C26 - page 67

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 67 P ARAMETER MEASUREMENT INFORMA TION 80x8x mode bus arbitration timing, SIF takes control NO. P ARAMETER MIN MAX UNIT 208a Setup of asynchronous signal SBBSY and SHLDA before SBCLK no longer high to guarantee recognition ...

  • Texas Instruments TMS380C26 - page 68

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 68 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • P ARAMETER MEASUREMENT INFORMA TION SOWN (see Note A) SDDIR SADH0–SADH7, SADL0–SADL7, SPH, SPL SBHE SRD , SWR SHRQ SIF Outputs: SBBSY , SHLDA SBCLK SIF Inputs: SIF Master Bus Exchange User Master T1 TX I2 I1 (T4) Read Writ ...

  • Texas Instruments TMS380C26 - page 69

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 69 P ARAMETER MEASUREMENT INFORMA TION 80x8x mode DMA read timing NO. P ARAMETER MIN MAX UNIT 205 Setup of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid before SBCLK in T3 cycle no longer high 15 ns 206 Hold of SADL0– ...

  • Texas Instruments TMS380C26 - page 70

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 70 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • P ARAMETER MEASUREMENT INFORMA TION 214 Address Data Address Extended Address V alid Low (High) SDDIR SDBEN (see Note A) SRDY SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note C) SALE SXAL SRD (see Note A) SWR SBHE (see Note B) ...

  • Texas Instruments TMS380C26 - page 71

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 71 P ARAMETER MEASUREMENT INFORMA TION 80x8x mode DMA write timing NO. P ARAMETER MIN MAX UNIT 208a Setup of asynchronous signal SRDY before SBCLK no longer high to guarantee recognition on that cycle 15 ns 208b Hold of as ...

  • Texas Instruments TMS380C26 - page 72

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 72 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • P ARAMETER MEASUREMENT INFORMA TION 218 SDDIR SDBEN SRDY SADL0–SADH7, SADH0–SADL7, SPH, SPL (see Note B) SALE SXAL SWR SRD SBHE (see Note A) SBCLK TW AIT V T1 T4 T3 T2 T1 TX T4 208b 208a 216a 225WH 223W 219 212 212 233 216 ...

  • Texas Instruments TMS380C26 - page 73

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 73 P ARAMETER MEASUREMENT INFORMA TION 80x8x mode bus arbitration timing, SIF returns control NO. P ARAMETER MIN MAX UNIT 220 † Delay from SBCLK low in I1 cycle to SADH0–SADH7, SADL0–SADL7, SPL, SPH, SRD , and SWR hi ...

  • Texas Instruments TMS380C26 - page 74

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 74 P ARAMETER MEASUREMENT INFORMA TION 80x8x mode bus release timing NO. P ARAMETER MIN MAX UNIT 208a Setup of asynchronous input SBRLS low before SBCLK no longer high to guarantee recognition 15 ns 208b Hold of asynchrono ...

  • Texas Instruments TMS380C26 - page 75

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 75 P ARAMETER MEASUREMENT INFORMA TION 68xxx DIO read timing NO. P ARAMETER MIN MAX UNIT 255 Delay from SDT ACK low to either SCS , SUDS , or SLDS high 15 ns 259 † Hold of SAD high-impedance after SUDS or SLDS low (see N ...

  • Texas Instruments TMS380C26 - page 76

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 76 P ARAMETER MEASUREMENT INFORMA TION (High) V alid Output Data V alid SADH0–SADH7, SADL0–SADL7, SPH, SPL SDT ACK † SDBEN SDDIR SUDS, SLDS SRNW SIACK SCS , SRSX, SRS0, SRS1 260 282a 275 283R 273 268 272 HI-Z HI-Z HI ...

  • Texas Instruments TMS380C26 - page 77

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 77 P ARAMETER MEASUREMENT INFORMA TION 68xxx DIO write timing NO. P ARAMETER MIN MAX UNIT 255 Delay from SDT ACK low to either SCS , SUDS or SLDS high 15 ns 262 Setup of write data valid before SUDS or SLDS no longer low 2 ...

  • Texas Instruments TMS380C26 - page 78

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 78 P ARAMETER MEASUREMENT INFORMA TION SADH0–SADH7, SADL0–SADL7, SPH, SPL SDT ACK † SDBEN ‡ SDDIR SUDS , SLDS (see Note A) SRNW SIACK SCS SRSX, SRS0, SRS1 HI-Z HI-Z HI-Z HI-Z (High) V alid Data 263 262 275 283W 282 ...

  • Texas Instruments TMS380C26 - page 79

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 79 P ARAMETER MEASUREMENT INFORMA TION 68xxx interrupt acknowledge cycle timing NO. P ARAMETER MIN MAX UNIT 255 Delay from SDT ACK low to either SCS or SUDS , or SIACK high 15 ns 259 † Hold of SAD high-impedance after SI ...

  • Texas Instruments TMS380C26 - page 80

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 80 P ARAMETER MEASUREMENT INFORMA TION Output Data V alid (High) Only SCS needs to be Inactive. All Others are Don’t Care. SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note A) SDT ACK † SDBEN SDDIR SLDS SRNW SIACK SCS , ...

  • Texas Instruments TMS380C26 - page 81

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 81 P ARAMETER MEASUREMENT INFORMA TION 68xxx mode bus arbitration timing, SIF takes control NO. P ARAMETER MIN MAX UNIT 208a Setup of asynchronous input SBGR before SBCLK no longer high to guarantee recognition on this cyc ...

  • Texas Instruments TMS380C26 - page 82

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 82 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • P ARAMETER MEASUREMENT INFORMA TION SOWN (see Note B) SDDIR SADH0–SADH7, SADL0–SADL7, SPH, SPL SRNW SAS , SLDS, SUDS SBRQ (see Note A) SIF Outputs: SBERR, SDT ACK, SBBSY SBGR SBCLK SIF Inputs: SIF Master Bus Exchange User ...

  • Texas Instruments TMS380C26 - page 83

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 83 P ARAMETER MEASUREMENT INFORMA TION 68xxx mode DMA read timing NO. P ARAMETER MIN MAX UNIT 205 Setup of input data valid before SBCLK in T3 cycle no longer high 15 ns 206 Hold of input data valid after SBCLK low in T4 c ...

  • Texas Instruments TMS380C26 - page 84

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 84 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • P ARAMETER MEASUREMENT INFORMA TION SALE SDBEN (see Note A) SDDIR SDT ACK (see Notes B and C) SADL0–SADH7, SADH0–SADL7, SPH, SPL SXAL SRNW SUDS, SLDS SAS (see Note A) SBCLK HI-Z Data In Address S7 S6 S5 S4 S3 S2 S1 T1 T4 T ...

  • Texas Instruments TMS380C26 - page 85

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 85 P ARAMETER MEASUREMENT INFORMA TION 68xxx mode DMA write timing NO. P ARAMETER MIN MAX UNIT 208a Setup of asynchronous input SDT ACK before SBCLK no longer high to guarantee recognition on this cycle 15 ns 208b Hold of ...

  • Texas Instruments TMS380C26 - page 86

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 86 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • P ARAMETER MEASUREMENT INFORMA TION 233a 21 1a TW AIT V T1 T4 T3 T2 T1 TX T4 SDBEN SDDIR SDT ACK (see Notes A and B) SADL0–SADH7, SADH0–SADL7, SPL, SPH SALE SXAL SRNW SUDS, SLDS SAS SBCLK Output Data Address Extended Addre ...

  • Texas Instruments TMS380C26 - page 87

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 87 P ARAMETER MEASUREMENT INFORMA TION 68xxx mode bus arbitration timing, SIF returns control NO. P ARAMETER MIN MAX UNIT 220 † Delay from SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS , and SLDS high-impedance, bus relea ...

  • Texas Instruments TMS380C26 - page 88

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 88 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • P ARAMETER MEASUREMENT INFORMA TION User Bus Exchange SIF Master T1 I2 I1 T4 T3 T2 SOWN SDDIR SADH0–SADH7, SADL0–SADL7, SPH, SPL SRNW SAS , SUDS, SLDS SBRQ (see Note A) SIF Outputs: SDT ACK SBGR SBCLK SIF Inputs: 230 220 2 ...

  • Texas Instruments TMS380C26 - page 89

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 89 P ARAMETER MEASUREMENT INFORMA TION 68xxx mode bus release and error timing NO. P ARAMETER MIN MAX UNIT 208a Setup of asynchronous input before SBCLK no longer high to guarantee recognition 15 ns 208b Hold of asynchrono ...

  • Texas Instruments TMS380C26 - page 90

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 90 P ARAMETER MEASUREMENT INFORMA TION normal completion with delayed start † SBCLK T1 T(W or 2) T3 T4 SDT ACK SBERR SHAL T TH T1 rerun cycle with delayed start † SBCLK T1 T2 T3 T4 TH B TH E SDT ACK SBERR SHAL T T1 SOW ...

  • Texas Instruments TMS380C26 - page 91

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 91 MECHANICAL DA T A JEDEC plastic leaded quad flat package (PQ suffix) Each of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated within an electrically nonconductive plastic compou ...

  • Texas Instruments TMS380C26 - page 92

    IMPORT ANT NOTICE T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify , before placing orders, that information being relied on is current and complete. All product ...

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