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Manual National Semiconductor DS90C3202

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Summary
  • National Semiconductor DS90C3202 - page 1

    DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver General Description The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs. The DS90C3202 is designed to interface between the digital video processor and the display device ...

  • National Semiconductor DS90C3202 - page 2

    Typical Application Diagram 20147102 FIGURE 2. LCD Panel Application Diagram Functional Description The DS90C3201 and DS90C3202 are a dual 10-bit color T ransmitter and Receiver FPD-Link chipset designed to transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface be- tween the digital video processor and t ...

  • National Semiconductor DS90C3202 - page 3

    Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply V oltage (V DD ) −0.3V to +4V L VCMOS/L VTTL Input V oltage −0.3V to (V DD + 0.3V) L VCMOS/L VTTL Output V oltage −0.3V to (V DD + 0.3V) L VDS ...

  • National Semiconductor DS90C3202 - page 4

    Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current Worst Case ( Figures 2, 4 ) C L = 8 pF, Worst Case Pattern Default Register Settings f = 8 MHz 65 130 mA f = 135 MHz 375 550 m ...

  • National Semiconductor DS90C3202 - page 5

    Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Condition/ Reference Min Typ Max Units CLHT LVCMOS/LVTTL Low-to-High Transition Time, C L = 8pF, ( Figure 5 ) (Note 8) Register addr 28d/1ch, bit [2] (RCLK)=0b (Default), bit [1] (RXE) =0b (Default), bit [0] (RXO) ...

  • National Semiconductor DS90C3202 - page 6

    Two-Wire Serial Communication Interface Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units f SC S2CLK Clock Frequency 400 kHz SC:LOW Clock Low Period R P = 4.7K Ω ,C L = 50pF 1.5 us SC:HIGH Clock High Period R P = 4.7K Ω ,C L = 50pF 0.6 us SCD:TR S2CLK and S2DAT Ris ...

  • National Semiconductor DS90C3202 - page 7

    AC Timing Diagrams (Continued) 20147103 FIGURE 2. “Worst Case” T est Pattern 20147104 FIGURE 3. Incremental T est Pattern 20147105 FIGURE 4. T ypical and Max ICC with Worse Case and Incremental Pattern 20147106 FIGURE 5. L VCMOS/L VTTL Output Load and T ransition Times DS90C3202 www .national.com 7 ...

  • National Semiconductor DS90C3202 - page 8

    AC Timing Diagrams (Continued) 20147107 FIGURE 6. Receiver Phase Lock Loop W ake-up Time 20147108 FIGURE 7. Powerdown Delay 20147109 FIGURE 8. Receiver Propagation Delay DS90C3202 www .national.com 8 ...

  • National Semiconductor DS90C3202 - page 9

    AC Timing Diagrams (Continued) 20147110 FIGURE 9. RFB: L VTTL Level Programmable Strobe Select 20147111 RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 11) + ISI (Inter-symbol interference) (Note 12) Cable Skew — typically 10 ps– 40 ps per foot, media dependent Please see National’s AN-1217 for more details. N ...

  • National Semiconductor DS90C3202 - page 10

    AC Timing Diagrams (Continued) 20147113 RegisterAddress 29d/1dh bit [2:1] = 00b FIGURE 12. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled 20147114 FIGURE 13. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled DS90C3202 www .national.com 10 ...

  • National Semiconductor DS90C3202 - page 11

    AC Timing Diagrams (Continued) 20147115 FIGURE 14. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Enabled DS90C3202 www .national.com 11 ...

  • National Semiconductor DS90C3202 - page 12

    AC Timing Diagrams (Continued) 20147116 FIGURE 15. L VDS Input Mapping DS90C3202 www .national.com 12 ...

  • National Semiconductor DS90C3202 - page 13

    AC Timing Diagrams (Continued) 20147117 FIGURE 16. Receiver RITOL Min and Max DS90C3202 www .national.com 13 ...

  • National Semiconductor DS90C3202 - page 14

    Pin Diagram DS90C3202 Receiver 20147118 DS90C3202 www .national.com 14 ...

  • National Semiconductor DS90C3202 - page 15

    DS90C3202 Pin Descriptions Pin No. Pin Name I/O Pin Type Description 1 S2DAT I/OP Digital Two-wire Serial Interface – Data 2 S2CLK I/P Digital Two-wire Serial Interface – Clock 3 VDDP1 VDD PLL Power supply for PLL circuitry 4 VSSP1 GND PLL Ground pin for PLL circuitry 5 VSSP0 GND PLL Ground pin for PLL circuitry 6 VDDP0 VDD PLL Power supply for ...

  • National Semiconductor DS90C3202 - page 16

    DS90C3202 Pin Descriptions (Continued) Pin No. Pin Name I/O Pin Type Description 46 VDD2 VDD LVTTL O/P PWR Power supply pin for LVTTL outputs and digital circuitry 47 RXEA0 O/P LVTTL O/P LVTTL level data output 48 RXEA1 O/P LVTTL O/P LVTTL level data output 49 RXEA2 O/P LVTTL O/P LVTTL level data output 50 RXEA3 O/P LVTTL O/P LVTTL level data outpu ...

  • National Semiconductor DS90C3202 - page 17

    DS90C3202 Pin Descriptions (Continued) Pin No. Pin Name I/O Pin Type Description 92 RXOA4 O/P LVTTL O/P LVTTL level data output 93 RXOA5 O/P LVTTL O/P LVTTL level data output 94 RXOA6 O/P LVTTL O/P LVTTL level data output 95 VDD5 VDD LVTTL O/P PWR Power supply pin for LVTTL outputs and digital circuitry 96 VSS5 GND LVTTL O/P PWR Ground pin for LVTT ...

  • National Semiconductor DS90C3202 - page 18

    Two-Wire Serial Communication Interface Description The DS90C3202 operates as a slave on the Serial Bus, so the S2CLK line is an input (no clock is generated by the DS90C3202) and the S2DA T line is bi-directional. DS90C3202 has a fixed 7bit slave address. The address is not user configurable in anyway . A zero in front of the register address is r ...

  • National Semiconductor DS90C3202 - page 19

    DS90C3202 Two-Wire Serial Interface Register Table Address R/W RESET Bit # Description Default Value 0d/0h R PWDN [7:0] Vender ID low byte[7:0] = 05h 0000_0101 1d/1h R PWDN [7:0] Vender ID high byte[15:8] =13h 0001_0011 2d/2h R PWDN [7:0] Device ID low byte[7:0] = 28h 0010_1000 3d/3h R PWDN [7:0] Device ID high byte 15:8] = 67h 0110_0111 4d/4h R PW ...

  • National Semiconductor DS90C3202 - page 20

    DS90C3202 Two-Wire Serial Interface Register Table (Continued) Address R/W RESET Bit # Description Default Value 26d/1ah R/W None [7] Reserved 0000_0000 [6:4] LVDS input skew control for RXE channel B, 000 (default) applies to no delay added, ONE buffer delay per step adjustment towards Thold improvements [3] Reserved [2:0] LVDS input skew control ...

  • National Semiconductor DS90C3202 - page 21

    DS90C3202 Two-Wire Serial Interface Register Table (Continued) Address R/W RESET Bit # Description Default Value 30d/1eh R/W None [7:5] Reserved 0000_0000 [4] I/O disable control for RXE channel A, 1: disable, 0: enable (default) [3] I/O disable control for RXE channel B, 1: disable, 0: enable (default) [2] I/O disable control for RXE channel C, 1: ...

  • National Semiconductor DS90C3202 - page 22

    Physical Dimensions inches (millimeters) unless otherwise noted 128-Pin TQFP Package Order Number DS90C3202VS NS Package Number VJX128A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifi ...

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