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Cypress CY7C1310AV18 - page 1
PRELIMINARY 18-Mb QDR™-II SRAM 2-W ord Burst Architecture CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose , CA 95134 • 408-943-2600 Document #: 38-05497 Rev . *A Revised June 1, 2004 Features • Separate independent Read and Write data ports — Supports concurrent transact ...
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Cypress CY7C1310AV18 - page 2
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 2 of 21 Selection Guide 167 MHz 133 MHz Unit Maximum Operating Freq uency 167 133 MHz Maximum Operating Curren t 800 700 mA Logic Block Diagram (CY7C1312A V18) CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. De code Read Data Reg. RPS WP ...
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Cypress CY7C1310AV18 - page 3
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 3 of 21 Pin Configurations CY7C1310A V18 (2M × 8) – 1 1 × 15 BGA 23 45 6 7 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC V SS /72M A BWS 1 K WPS NC/144M NC NC NC NC NC TDO NC NC D5 NC NC NC TCK NC NC A NC/288M K BWS 0 V SS AAA NC V SS V SS V SS V ...
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Cypress CY7C1310AV18 - page 4
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 4 of 21 Pin Definitions Pin Name I/O Pin Description D [x:0] Input- Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations . CY7C1310A V18 - D [7:0] CY7C1312A V18 - D [17:0] CY7C1314A V18 - D [35:0] WPS Input- ...
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Cypress CY7C1310AV18 - page 5
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 5 of 21 Q [x:0] Outputs- Synchronous Data Output signals . These pins drive out the reque st ed data during a Read operati on. V alid data is driven out on the ri sing edge of both the C and C clocks during Read operations or K and K when in single clock mode. ...
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Cypress CY7C1310AV18 - page 6
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 6 of 21 Introduction Functional Overview The CY7C1310A V18/CY7C1312A V18/CY7C1314A V18 are synchronous pi pelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Writ e port is dedicated to Writ ...
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Cypress CY7C1310AV18 - page 7
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 7 of 21 Depth Exp ansion The CY7C1312A V18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can dese lect the specified por ...
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Cypress CY7C1310AV18 - page 8
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 8 of 21 Write Cycl e Descriptions (CY7C1310A V18 and CY7C1312A V18) [2, 8] BWS 0 BWS 1 KK Comment s L L L-H – During the Data portion of a Write sequence : CY7C1310A V18 − both nibbles (D [7:0] ) are written into the device, CY7C1312A V18 − both bytes (D ...
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Cypress CY7C1310AV18 - page 9
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 9 of 21 Maximum Ratings (Above which useful l ife may be impaired.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... –55°C to +125°C Supply ...
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Cypress CY7C1310AV18 - page 10
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 10 of 21 Switching Characteristics Over the Operating Range [1 6,17] Cypress Consortium Description 167 MHz 133 MHz Unit Parameter Parameter Min. Max. Min. Max. t CYC t KHKH K Clock and C Clock Cycle T ime 6.0 7.9 7.5 8.4 ns t KH t KHKL Input Clock (K/K and C/C ...
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Cypress CY7C1310AV18 - page 11
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 1 1 of 21 Cap acit ance [20] Parameter Descripti on T est Conditions Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V V DDQ = 1.5V 5p F C CLK Clock Input Capacitance 6 pF C O Output Capacitance 7 pF AC T est Loads and W aveforms Note: 20. ...
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Cypress CY7C1310AV18 - page 12
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 12 of 21 Switching W aveforms [21,22,23] Notes: 21. Q00 refers to output from address A0. Q01 refers to out put from the next internal burst address following A0 i.e., A0+1. 22. Output are disabled (High-Z) one clock cycle after a NOP . 23. In this example , if ...
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Cypress CY7C1310AV18 - page 13
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 13 of 21 IEEE 1 149.1 Serial Boundary Sc an (JT AG) These SRAMs incorporate a serial bo undary scan test access port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149.1-1900. The T AP operates using JEDEC standard 1.8V I/O logi ...
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Cypress CY7C1310AV18 - page 14
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 14 of 21 is loaded into the instruction register upon power-up or whenever the T AP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction caus es the b oundary scan register to be connected between th e TDI and TDO pins when th e T AP ...
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Cypress CY7C1310AV18 - page 15
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 15 of 21 Note: 24. The 0/1 next to each state represent s the value at TMS at the rising edge of TCK. T AP Controller S tate Diagram [24] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P A USE-DR EXIT2-DR UPDA TE-DR SELECT IR-S ...
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Cypress CY7C1310AV18 - page 16
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 16 of 21 T AP Controller Block Diagram T AP Electric al Characteristics Over the Operating R ange [9,12,25] Parameter Description T est Conditions Min. Max. Unit V OH1 Output HIG H V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIG H V oltage I OH = − 100 µ A ...
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Cypress CY7C1310AV18 - page 17
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 17 of 21 T AP AC Switc hing Characteristics Over the Operating Range [26, 27] Parameter Description Min. Max. Unit t TCYC TCK Clock Cycle T i me 100 ns t TF TCK Clock Frequency 10 MHz t TH TCK Clock HIGH 40 ns t TL TCK Clock LOW 40 ns Set-up Times t TMSS TMS Se ...
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Cypress CY7C1310AV18 - page 18
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 18 of 21 Identification Register Definitions Instruction F ield CY7C1310A V18 CY7C1312A V18 CY7C1314 A V18 Description 2M x 8 1M x 18 512K x 36 Revision Number (31:29) 000 000 000 V ersion number. Cypress Device ID (28:12) 1 101001 1010000101 1 101001 10 100101 ...
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Cypress CY7C1310AV18 - page 19
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 19 of 21 30 1 1F 31 1 1G 32 9F 33 10F 34 1 1E 35 10E 36 10D 37 9E 38 10C 39 1 1D 40 9C 41 9D 42 1 1B 43 1 1C 44 9B 45 10B 46 1 1A 47 Internal 48 9A 49 8B 50 7C 51 6C 52 8A 53 7A 54 7B 55 6B 56 6A 57 5B 58 5A 59 4A 60 5C 61 4B 62 3A 63 1H 64 1A 65 2B 66 3B 67 1C ...
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Cypress CY7C1310AV18 - page 20
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 20 of 21 QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress, Hi tachi, IDT , NEC and Samsung technology . All product and company names mentioned in th is documen t are the trademarks of their respe ctive holders. ...
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Cypress CY7C1310AV18 - page 21
CY7C1310A V18 CY7C1312A V18 CY7C1314A V18 PRELIMINARY Document #: 38-05497 Rev . *A Page 21 of 21 Document History Page Document Title: CY7C1310 A V18/CY7C1312A V18/CY7C1314A V1 8 18-Mb QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05497 REV . ECN No. Issue Date Orig. of Change Description of Change ** 208405 see ECN DIM New Data She ...
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