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Cypress Semiconductor CY7C1350G - page 1
4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture CY7C1350G Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05524 Rev . *F Revised July 5, 2006 Features • Pin comp atible and functio nally equivalent to ZBT™ devices • Internally self-time d output buffer cont ...
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Cypress Semiconductor CY7C1350G - page 2
CY7C1350G Document #: 38-05524 Rev . *F Page 2 of 15 Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit Maximum Access T ime 2.6 2.8 3.5 4.0 4.5 ns Maximum Operating Curren t 325 265 240 225 205 mA Maximum CMOS S tandby Current 40 40 40 40 40 mA Pin Configurations A A A A A 1 A 0 NC/288M NC/144M V SS V DD NC/36M A A A A A A DQP B DQ B DQ ...
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Cypress Semiconductor CY7C1350G - page 3
CY7C1350G Document #: 38-05524 Rev . *F Page 3 of 15 Pin Configurations (continued) 23 4 56 7 1 A B C D E F G H J K L M N P R T U DQ A V DDQ NC/576 M NC/1G DQ C DQ D DQ C DQ D AA AA NC/18M V DDQ CE 2 A V DDQ V DDQ V DDQ V DDQ NC/144 M NC A DQ C DQ C DQ D DQ D NC V DD A NC/72M DQP D A A ADV/LD A CE 3 NC V DD AA N C V SS V SS NC DQP B DQ B DQ B DQ A ...
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Cypress Semiconductor CY7C1350G - page 4
CY7C1350G Document #: 38-05524 Rev . *F Page 4 of 15 Functional Overview The CY7C1350G is a synchronous-pipelin ed Burst SRAM designed specifically to el iminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with th e Clock Ena ...
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Cypress Semiconductor CY7C1350G - page 5
CY7C1350G Document #: 38-05524 Rev . *F Page 5 of 15 On the subsequent clock rise the data line s are a utomatically tri-stat ed regardless o f the stat e of the OE input signal. This allows the external lo gic to present the data on DQs and DQP [A:D] . In addition, the ad dress for the subsequent access (Read/Write/Deselect) is latched into the Ad ...
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Cypress Semiconductor CY7C1350G - page 6
CY7C1350G Document #: 38-05524 Rev . *F Page 6 of 15 NOP/WRITE ABORT (Begin Burs t) None L L L L H X L L-H T ri-S tate WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-S tate IGNORE CLOCK EDGE (S tall) Current X L X X X X H L-H — SNOOZE MODE None X H X X X X X X T ri-S tate Partial T ruth T able for Read/Write [2, 3, 9] Function WE BW D BW ...
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Cypress Semiconductor CY7C1350G - page 7
CY7C1350G Document #: 38-05524 Rev . *F Page 7 of 15 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ......... ............ ........... ..... − 65°C to +150°C Ambient T emperature with Power Applied ....... ........... ........... ........... .......... − 55°C to +125°C ...
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Cypress Semiconductor CY7C1350G - page 8
CY7C1350G Document #: 38-05524 Rev . *F Page 8 of 15 I SB3 Automatic CE Power-Down Current—CMOS Inputs V DD = Max, Device Deselected, or V IN ≤ 0.3V or V IN > V DDQ – 0.3V f = f MAX = 1/t CYC 4-ns cycle, 250 MHz 105 mA 5-ns cycle, 200 MHz 95 mA 6-ns cycle, 166 MHz 85 mA 7.5-ns cycle, 133 MHz 75 mA 10-ns cycle, 100 MHz 65 mA I SB4 Automatic ...
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Cypress Semiconductor CY7C1350G - page 9
CY7C1350G Document #: 38-05524 Rev . *F Page 9 of 15 Switching Characteristics Over the Operating Range [17, 18] –250 –20 0 –166 –133 –100 Parameter Description Min. Max. Min. Max. Mi n. Max. Min. Max. Min. Max. Unit t POWER V DD (typical) to the first Access [13] 1 1 1 1 1 ms Clock t CYC Clock Cycle T ime 4.0 5.0 6.0 7.5 10 ns t CH Clock ...
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Cypress Semiconductor CY7C1350G - page 10
CY7C1350G Document #: 38-05524 Rev . *F Page 10 of 15 Switching W aveforms Read/W rite Timing [19, 20, 21] Notes: 19. For this waveform ZZ is tied LOW . 20. When CE is LOW , CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW . When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 21. Order of the Burst sequence is determined by the statu s of the MO ...
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Cypress Semiconductor CY7C1350G - page 11
CY7C1350G Document #: 38-05524 Rev . *F Page 1 1 of 15 NOP , ST ALL, and DESELECT Cycles [19, 20 , 22] ZZ Mode T iming [23, 24] Notes: 22. The IG NOR E CLOCK EDGE or ST ALL cycle (Clock 3) illustrates CEN being used to create a p ause. A write is not performed during this cycle. 23. Device must be deselected when entering ZZ mode. See cycle descrip ...
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Cypress Semiconductor CY7C1350G - page 12
CY7C1350G Document #: 38-05524 Rev . *F Page 12 of 15 Ordering Information Not all of the speed, package and temperature ranges are av ailable. Please contact your local sales representative or visit www .cyp ress.com for actual products offered. Speed (MHz) Ordering Code Pa ckage Diagram Package T ype Operating Range 100 CY7C1350G-10 0AXC 51-85050 ...
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Cypress Semiconductor CY7C1350G - page 13
CY7C1350G Document #: 38-05524 Rev . *F Page 13 of 15 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.30±0 ...
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Cypress Semiconductor CY7C1350G - page 14
CY7C1350G Document #: 38-05524 Rev . *F Page 14 of 15 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do ...
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Cypress Semiconductor CY7C1350G - page 15
CY7C1350G Document #: 38-05524 Rev . *F Page 15 of 15 Document History Page Document Title: CY7C1350G 4-Mbit (128K x 36) Pipe lined SRAM with NoBL™ Arch itecture Document Number: 38-05524 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 224380 See ECN RKF New data sheet *A 276690 See ECN VBL Changed TQFP pkg to lead-free TQFP in ...
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