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Intel 82543GC - page 1
i 82543GC Gigabit Ethernet Controller Specification Update June 18, 2004 Revision 2.1 The 82543GC Gigabit Ethernet C ontroller may cont ain design defects or erro rs known as errata that ma y cause the product to devi ate from published specifications. Current characterized errata are document ed in this Specification Update. ...
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Intel 82543GC - page 2
82543GC Gigabit Ethernet Controller Specificati on Update ii Information in thi s document is prov ided in connection w ith Inte l pr oducts. No license, ex press or implied, by estoppel or o the rwise, to any intellectual property rights is granted by this document. Ex cept as provided in Intel's Terms and Conditi ons of Sale for such produ c ...
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Intel 82543GC - page 3
82543GC Gigabit Ethernet Controller Specificati on Update 3 CONTENTS CONTENTS .........................................................................................................................................................3 REVISION HISTORY .................................................................................................... ...
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Intel 82543GC - page 4
82543GC Gigabit Ethernet Controller Specificati on Update 4 27. Link Status Change Interrupt On ly Occurs If Link is Up ....................................................................17 28. Early Transmit Feature Does Not Operate Correctl y .........................................................................17 29. TDO Output Not Floated W ...
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Intel 82543GC - page 5
82543GC Gigabit Ethernet Controller Specificati on Update 5 REVISION HISTORY 82543GC Gigabit Ethernet Controller Specification Update Date of Revision Revision Description June 18, 2004 2.1 Initial Public Release ...
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Intel 82543GC - page 6
82543GC Gigabit Ethernet Controller Specificati on Update 6 Note: This page is intentionally left blank. ...
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Intel 82543GC - page 7
82543GC Gigabit Ethernet Controller Specificati on Update 7 PREFACE This document is an update to published specifications. There are two current specification documents: • 82543GC Gigabit Ethernet Controller Datasheet, Intel Corpor ation. • OR-2710 82543GC Gigabit Ether net Contr oller Developer’s Manual, Intel Corporation. This document is ...
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Intel 82543GC - page 8
82543GC Gigabit Ethernet Controller Specificati on Update 8 GENERAL INFORMATION This section covers the 82543GC device. 82543GC COMPONENT M ARKING INFORMATION Stepping QDF Number S- Spec Number Top Marking Notes A0 Q415 S L3N8 FW82543GC Engineering Samples. May be marked with either QDF number or S-spec number. A1 Q416 S L3N9 FW82543GC Engineering ...
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Intel 82543GC - page 9
82543GC Gigabit Ethernet Controller Specificati on Update 9 Summary Table of Changes The following table indicates the Specification Changes, Errata, Sp ecification Clarifications or Documentation Changes, which a ppl y to the listed 82543GC steppings. Intel intends to fix some of t he errata in a future ste pping of the component, and to account f ...
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Intel 82543GC - page 10
82543GC Gigabit Ethernet Controller Specificati on Update 10 26 X X X NoFix Default Speed Selection May Depend on EEPROM Presence 15 27 X X X NoFix Link Status Change Interrupt On ly Occurs If Link is Up 15 28 X X X NoFix Early Transmit Feature Does Not Operate Co rrectly 15 29 X X X NoFix TDO Output Not Floated When JTAG TAP Co ntroller Inactive 1 ...
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Intel 82543GC - page 11
82543GC Gigabit Ethernet Controller Specificati on Update 11 SPECIFICATION CHANGES 1. GMII Setup and Hold Times Problem : The data sheet contains incorrect setup and hold time specifications for the GMII interface. The old setup and hold times were 2.5ns minimum and 4ns. typical. For the receive signals, the new setup time is 2.0ns. (m in.) the ne ...
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Intel 82543GC - page 12
82543GC Gigabit Ethernet Controller Specificati on Update 12 Workaround : None. Status: This erratum was resolved in the A1 stepping of the 82543GC Giga bit Ethernet Controller. 4. Some Registers Cannot Be Accessed During Reset Problem : PCI accesses to transmit descriptor registers will not succeed if the 82543GC controller is in a transmit reset ...
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Intel 82543GC - page 13
82543GC Gigabit Ethernet Controller Specificati on Update 13 Implication : Data transfer performance is subs tantially reduced due to error p ackets. Workaround : None. Status: Intel resolved this erratum in the A1 stepping of the 82543GC Giga bit Ethernet Controller. 8. 48 Bit Preambles Sent in 10Mb and 100Mb Operation Problem: The 82543GC device ...
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Intel 82543GC - page 14
82543GC Gigabit Ethernet Controller Specificati on Update 14 Workaround : None. Status: Intel does not plan to resolve this erratum in a future stepping of the 82543 GC Gigabit Ethernet Controller. 13. Zero-Byte PCI Bus Writes Problem : The 82543GC Gigabit Ethernet C ontroller can generate zero -b yte writes on a 32-bit PC I bus because it is has a ...
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Intel 82543GC - page 15
82543GC Gigabit Ethernet Controller Specificati on Update 15 Workaround: When using half-duplex mode, progr am the 82543GC Gigabit Ethernet Controller for a very high collision threshold and allow it to retransmit packets that encounter a late collision. Also , if the “early transmit” feature is used, configure the device to retransmi t packets ...
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Intel 82543GC - page 16
82543GC Gigabit Ethernet Controller Specificati on Update 16 When the size of a received packet exceeds the s pace in the packet buffer memory , the 82543GC Gigabit Ethernet Controller will drop the packet. This behavior is normal and is not affected by the erratum. Implication: Software cannot directly access packet buffer memory . Such accesses a ...
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Intel 82543GC - page 17
82543GC Gigabit Ethernet Controller Specificati on Update 17 Problem : Bits SWDPIO_EXT[7:4] of Initialization Control Word 2 in the EEPROM are supposed to map to bits SWDPIOHI[11:8] in the Extended Device Control R egister at offset 0x00018. Instead, the bits map to SWDPINSHI[7:4] of that register. Implication: The input/output characteristic of so ...
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Intel 82543GC - page 18
82543GC Gigabit Ethernet Controller Specificati on Update 18 Problem : Use of the early transmit function may cause hangs in 10/100 Mb/s operation. Implication: The early transmit feature is only applicable to 10/100 Mbps operation, where it was expected to improve overall data transfer rates. With the feature enable d , the 82543GC controller may ...
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Intel 82543GC - page 19
82543GC Gigabit Ethernet Controller Specificati on Update 19 Problem : Asserting the collision input si gnal (COL) can cause the transmitter to hang intermittently in TBI mode. Implication: When the 82543GC Gigabit Ethernet Controller is in TB I mode, the collision signal is meaningless because receive and transmit channels each have their own dedi ...
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Intel 82543GC - page 20
82543GC Gigabit Ethernet Controller Specificati on Update 20 Implication : Corrupted descriptor writebacks may include writing back unconsumed descriptors, descriptor writebacks to incorrect addresses, or writebacks missed altogether. In addition, the device may cease to access the PCI bus or cease packet transmission. If the device hangs, a full s ...
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Intel 82543GC - page 21
82543GC Gigabit Ethernet Controller Specificati on Update 21 SPECIFICATION CLARIFICATIONS 1. 0-70C Ambient Temperature Range Problem : The data sheet contains conflicti ng information on the controller’s rated temperature range. The recommended temperature range is given as 0-55C both in a specif ication table and Section 5.3, Thermal Specificati ...
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Intel 82543GC - page 22
82543GC Gigabit Ethernet Controller Specificati on Update 22 TX_RING_LENGTH 00428 03808 TX_DESC_HEAD 00430 03810 TX_DESC_TAIL 00438 03818 TX_INTERRUPT_DELAY 00440 03820 RX_PB_HEAD 08000 02410 RX_PB_TAIL 08008 02418 TX_PB_HEAD 08010 03410 TX_PB_TAIL 08018 03418 FLOW_CONTROL RX THRESH HI 00160 02168 FLOW_CONTROL RX THRESH LO 00168 02160 Affected Docs ...
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Intel 82543GC - page 23
82543GC Gigabit Ethernet Controller Specificati on Update 23 5. Register Summary Uses Improper Page Reference Format Problem : The 82543GC Register Summary refers to page n umbers in the format (11-182, 11-186, 11-1 88, …) and (10- 162, 10-166, 10-166, …). The pagination will change to the format (182, 186, 188, …) and (1 62, 166, 186, …). ...
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Intel 82543GC - page 24
82543GC Gigabit Ethernet Controller Specificati on Update 24 segmentation. The Transfer DMA Cont rol Register (TXDMAC) will be removed from the developer’s manual and text in 12.6 Reset should change. Note: Erratum #14 prohibits using TCP segmentat ion regardless of the preemption function. Affected Docs: OR-2710 82543 GC Gigabit Ethernet Control ...
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