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Инструкция обслуживания Intel 253666-024US

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  • Intel 253666-024US - page 1

    In tel® 64 and IA-32 Ar chitectur es So ftw ar e De v eloper’ s Manual Vo l u m e 2 A : Instruction Se t R e f er ence, A-M NO TE: The In tel 64 and IA-32 Architectu re s S of tw are D eve lo pe r 's Ma n ua l cons ist s of f ive volu me s: Basic Architecture , Or der Number 253665; Instruction Se t R e fer ence A-M , Or der Number 253666; ...

  • Intel 253666-024US - page 2

    ii Vol. 2A INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH I NTEL PRODUCTS . NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPE L OR OTHERWISE, TO ANY INTELLECTUAL PROP ERTY RIGHTS IS GRANT- E D B Y T H I S D O C U M E N T . E XC E P T AS P R O VI D E D I N INTEL’ S T ERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSU MES NO LIABILITY ...

  • Intel 253666-024US - page 3

    Vol. 2A iii CONT ENTS PAG E CHAP TER 1 ABOUT THIS MANUAL 1.1 IA-32 PROCES SORS COVERED IN THIS MAN UAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 OVERVIEW OF VOLUME 2A AN D 2B: INSTRUCTION SET REFERENCE . . . . . . . . . . . . . . . . . . 1-2 1.3 NOTATIONAL CON VENTIONS . . . . . . . . . . . . . . . . . . . . ...

  • Intel 253666-024US - page 4

    CONTE NTS iv Vol. 2A PAG E 3.1.1.5 Description Col umn in the Instruction Summary Ta ble . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.1.6 Description Secti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.1.7 Operation Se ction . . . . . . . . . . . . . . . ...

  • Intel 253666-024US - page 5

    Vol. 2A v CONTE NTS PAG E CLFLUSH—Flu sh Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -108 CLI — Clear Int errupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110 CLTS—Clear Ta sk-Switched Flag in C R0 . . ...

  • Intel 253666-024US - page 6

    CONTE NTS vi Vol. 2A PAG E Double-Precision F loating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-231 CVTSS2SI—Convert Sca lar Single-Precision Floatin g-Point Value to Doubleword Integ er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 4 CVTT ...

  • Intel 253666-024US - page 7

    Vol. 2A vii CONTE NTS PAG E FLD—Load Floa ting Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 41 FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLD Z— Load Constant . . . . . . . . . . . 3-344 FLDCW—Load x87 FPU Cont rol Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Intel 253666-024US - page 8

    CONTE NTS viii Vol. 2A PAG E JMP—Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-508 LAHF—Load S tatus Flags into AH Regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-518 LAR—Load Access Ri ghts Byte. . . . . . . ...

  • Intel 253666-024US - page 9

    Vol. 2A ix CONTE NTS PAG E MOVNTDQ—Store Do uble Quadword Using Non-Te mporal Hint . . . . . . . . . . . . . . . . . 3-649 MOVNTI—Store Do ubleword Using Non-Te mporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . 3-652 MOVNTPD—Store Packed Dou ble-Precision Floating-Poin t Values Using Non-Temporal Hi nt . . . . . . . . . . . . . . ...

  • Intel 253666-024US - page 10

    CONTE NTS x Vol. 2A PAG E PAVGB/PAVGW— Average Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 PCMPEQB/PCMPEQW/PC MPEQD— Compare Packed Data for E qual . . . . . . . . . . . . . . . . 4-64 PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed S igned Integers for Greater Than . 4- 68 PEXTRW—Extract Word . . ...

  • Intel 253666-024US - page 11

    Vol. 2A xi CONTE NTS PAG E PUSH—Push Word, Dou bleword or Quadword Onto the Stack . . . . . . . . . . . . . . . . . . . 4-217 PUSHA/PUSHAD—Push All Gener al-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-222 PUSHF/PUSHFD—Pus h EFLAGS Register on to the Stack . . . . . . . . . . . . . . . . . . . . . . . . 4-225 PXOR? ...

  • Intel 253666-024US - page 12

    CONTE NTS xii Vol. 2A PAG E SYSCALL—Fa st System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-367 SYSENTER—Fast S ystem Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 69 SYSEXIT—Fast Retu rn from Fast System Call . . ...

  • Intel 253666-024US - page 13

    Vol. 2A xiii CONTE NTS PAG E CHAPTER 6 SAFER MODE EXTENSIONS REF ERENCE 6.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 6.2 SMX FUNCTI ONALITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Intel 253666-024US - page 14

    CONTE NTS xiv Vol. 2A PAG E A.5.2.3 Escape Opcodes with DA as Fi rst Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25 A.5.2.4 Escape Opcodes with DB as First B yte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26 A.5.2.5 Escape Opcodes with DC as First By te. . . . . . . . . . ...

  • Intel 253666-024US - page 15

    Vol. 2A xv CONTE NTS PAG E FIGUR ES Figure 1-1. Bit and Byte Or der . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Figure 1-2. Syntax for CPUID, CR , and MSR Data Presenta tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Figure 2-1. Intel 64 and IA-32 Arch ...

  • Intel 253666-024US - page 16

    CONTE NTS xvi Vol. 2A PAG E TABLES Table 2-1. 16-Bit Addressing Fo rms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Table 2-2. 32-Bit Addressing Fo rms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Table 2-3. 32-Bit Addressing Fo rms with the SIB Byte . . . . . . . . ...

  • Intel 253666-024US - page 17

    Vol. 2A xvii CONTE NTS PAG E Table 3-38. FP TAN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-365 Table 3-39. FS CALE Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-377 Table 3-40. FS I ...

  • Intel 253666-024US - page 18

    CONTE NTS xviii Vol. 2A PAG E Table A-1. Superscripts Utilized in Op code Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Table A-2. One-byte Opcode Map: (00H — F7H) *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -9 Table A-3. Two-byte Opcode Map: 00H — 77H (First ...

  • Intel 253666-024US - page 19

    Vol. 2A xix CONTE NTS PAG E Table B-23. Format and Enco ding of SSE Cacheability & Memory Ordering Instruc tions . . . . . . B-67 Table B-24. Enco ding of Granularity of D ata Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B -68 Table B-25. Formats an d Encodings of SSE2 Floating-Poi nt Instructions . . . . ...

  • Intel 253666-024US - page 20

    CONTE NTS xx Vol. 2A PAG E ...

  • Intel 253666-024US - page 21

    Vol. 2A 1-1 CHAP TER 1 ABOUT THIS MANUAL The Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B : Instruction Set Reference (order numbers 253666 and 253667 ) are part of a set that describes the architecture and programming environment of all Intel 64 and IA-32 architecture processors. Other volumes in this set ...

  • Intel 253666-024US - page 22

    1-2 Vol. 2A ABOUT THIS M ANUAL • Intel ® Core™2 Duo processor • Intel ® C o r e™ 2 Q u a d p r oc e s s o r • Intel ® Xe on ® processor 3000, 3200 series • Intel ® Xe on ® processor 5000 series • Intel ® Xe on ® processor 5100, 5300 series • Intel ® Core™2 Extreme proc essor • Intel ® Core™2 Extreme Quad-core process ...

  • Intel 253666-024US - page 23

    Vol. 2A 1-3 ABOUT THIS MANUAL Chapter 1 — About This Manual. Gives an overview of all five volumes of the Intel ® 64 and IA-32 Architectures Software Developer’ s Manual . It also describes the notational conventions in these manuals and lists related Intel ® manuals and docu- mentation of interest to programmers and hardware designers. Chapt ...

  • Intel 253666-024US - page 24

    1-4 Vol. 2A ABOUT THIS M ANUAL 1.3.1 Bit and Byte Order In illustrations of data structures in memory , smaller addresses appear toward the bottom of the figure; addresses increase tow ard the top. Bit positions are numbered from right to left. The numerical v alue of a set bit is equal to two raised to the power of the bit position. IA -32 process ...

  • Intel 253666-024US - page 25

    Vol. 2A 1-5 ABOUT THIS MANUAL 1.3.2 R eserved Bits and Softw a r e Compatibility In many register and memory layout descriptions, certain bits are marked as reserved . When bits are marked as reserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unknown, effect. The behavior of ...

  • Intel 253666-024US - page 26

    1-6 Vol. 2A ABOUT THIS M ANUAL 1.3.3 Instruction Oper ands When instructions are represented symbol ically , a subset of the IA -32 assembly language is used. In this subset, an instruction has the following format: label: mnemo nic argument1, argument2, arg ument3 where: • A label is an identifier which is followed by a colon. • A mnemonic is ...

  • Intel 253666-024US - page 27

    Vol. 2A 1-7 ABOUT THIS MANUAL For example, a progr am can keep its code (instructions) and stack in separate segments. Code addresses would always refer to the code space, and stack addresses would always refer to the stack space. The following notation is used to specify a byte address within a segment: Segment-register:Byte-address For example, t ...

  • Intel 253666-024US - page 28

    1-8 Vol. 2A ABOUT THIS M ANUAL 1.4 R ELATED LITER ATURE Literature related to Intel 64 and IA -32 processors is listed on-line at: http://developer .intel.com/products/processor/manuals/index.htm Some of the documents listed at this web site can be viewed on-line; others can be ordered. The literature av ailable is listed by Intel processor and the ...

  • Intel 253666-024US - page 29

    Vol. 2A 1-9 ABOUT THIS MANUAL literature types: applications notes, data sheets, manuals, papers, and specification updates. See also: • The data sheet for a particular Intel 64 or IA -32 processor • The specification update for a particular Intel 64 or IA-32 processor • Intel ® C++ Compiler documentation and online help http://www .intel.co ...

  • Intel 253666-024US - page 30

    1-10 Vol. 2A ABOUT THIS M ANUAL • Intel 64 and IA-32 processor manuals (printed or PDF downloads): http://developer .intel.com/products/processor/manuals/index.h tm • Intel ® Multi-Core T echnology: http://developer .intel.com/multi-core/index.htm • Hyper- Threading T echnology (HT T echnolog y): http://developer .intel.com/technology/h yper ...

  • Intel 253666-024US - page 31

    Vol. 2A 2-1 CHAP TER 2 INSTRUCTION F ORMAT This chapter describes the instruction format for all Intel 64 and IA -32 processors. The instruction format for protected mode, real- address mode and virtual-8086 mode is described in Section 2.1. Increm ents provided for IA -32e mode and its sub- modes are described in Section 2.2. 2.1 INSTRUCTION F ORM ...

  • Intel 253666-024US - page 32

    2-2 Vol. 2A INSTRUCTION F ORMAT • F2H—REPNE/REPNZ (used only with string instructions; when u sed with the escape opcode 0FH, this prefix is treated as a mandatory prefix for some SIMD instructions) • F3H—REP or REPE/REPZ (used only with string instructions; when used with the escape opcode 0FH, this pref ix is treated as an mandatory prefi ...

  • Intel 253666-024US - page 33

    Vol. 2A 2-3 INSTRUCTION F ORMAT opcodes with Intel 64 or IA-32 instructions is reserved; such use may cause unpre- dictable behavior . The operand-size override prefix allows a progr am to switch between 16- and 32-bit operand sizes. Either size can be the default; use of th e prefix selects the non-default size. Use of 66H followed by 0FH is tr ea ...

  • Intel 253666-024US - page 34

    2-4 Vol. 2A INSTRUCTION F ORMAT 2.1.3 ModR/M and SIB Bytes Many instructions that refer to an oper and in memory have an addressing-form spec- ifier byte (called the ModR/M byte) followi ng the primary opcode. Th e ModR/M byte contains three fields of information: • The mod field combines with the r/m field to form 32 possible values: eight regis ...

  • Intel 253666-024US - page 35

    Vol. 2A 2-5 INSTRUCTION F ORMAT location; the last eight (Mod = 11B) prov ide ways of specifying gener al-purpose, MMX technology and XMM registers. The Mod and R/M columns in T able 2-1 and T a ble 2-2 give the binary encodings of the Mod and R/M fields required to obtain the effective address listed in the first column. For example: see the row i ...

  • Intel 253666-024US - page 36

    2-6 Vol. 2A INSTRUCTION F ORMAT NO TES: 1. The default segm ent regi ster is SS f or the eff ective addr esses c ontaining a BP index, DS f or other eff ective addr esses. 2. The disp16 nomenclature denotes a 16-bit displace ment that f ollows the ModR/M byte and that is added t o the index. 3. The disp8 nomencla ture deno tes an 8-bit displace men ...

  • Intel 253666-024US - page 37

    Vol. 2A 2-7 INSTRUCTION F ORMAT NOT ES: 1. The [--][--] nomenclature mean s a SIB follo ws the ModR/M byte. 2. Th e disp32 nomenclature denotes a 32-bit di spla cement tha t follo ws the ModR/M byte (or the SIB byte if one is presen t) and that is added t o the index. 3. Th e disp8 nomenclature denotes an 8-bit displace me n t t ha t f ol lo ws t h ...

  • Intel 253666-024US - page 38

    2-8 Vol. 2A INSTRUCTION F ORMAT of the table indicate the register used as th e index (SIB byte bits 3, 4 and 5) and the scaling factor (determined by SI B byte bits 6 and 7). NO TES: 1. The [*] nomenclature means a disp 32 with no base if the MOD is 00B. Otherwise, [*] means disp8 or disp32 + [EBP]. This pro vid es the following address modes: MOD ...

  • Intel 253666-024US - page 39

    Vol. 2A 2-9 INSTRUCTION F ORMAT 2.2 IA-32E MODE IA-32e mode has two sub-modes. These are: • Compatibility Mode. Enables a 64-bit operating sy stem to run most legacy protected mode software unmodified. • 64-Bit Mode. Enables a 64-bit operating system to run applications written to access 64-bit address space. 2.2.1 R EX Prefix es REX prefixes a ...

  • Intel 253666-024US - page 40

    2-10 Vol. 2A INSTRUCTION F ORMAT 2.2.1.1 Encoding Intel 64 and IA-32 instruction formats specify up to three registers by using 3-bit fields in the encodin g, depending on the format: • ModR/M: the reg and r/m fields of the ModR/M byte • ModR/M with SIB: the reg field of the ModR/M byte, the base and index field s of the SIB (scale, index, base ...

  • Intel 253666-024US - page 41

    Vol. 2A 2-11 INSTRUCTION F ORMAT T able 2-4. REX Pre fix Fields [BITS: 0100WRXB] Field Name Bit Position Definition - 7:4 0100 W 3 0 = Operand size de termin ed by CS.D 1 = 64 Bit Oper and Size R 2 Extension of the ModR/M r eg field X 1 Extension of the SIB inde x field B 0 Extension o f the ModR/M r/m field, SIB base field, or Opc ode reg f ield F ...

  • Intel 253666-024US - page 42

    2-12 Vol. 2A INSTRUCTION F ORMAT In the IA-32 architecture, byte registers (AH, A L, BH, BL, CH, CL, DH, and DL) are encoded in the ModR/M byte’s reg field, the r/m field or the opcode reg field as regis- ters 0 through 7. REX prefixes provide an additional addressing capability for byte- registers that makes the least -significant byte of GPRs a ...

  • Intel 253666-024US - page 43

    Vol. 2A 2-13 INSTRUCTION F ORMAT 2.2.1.3 Displacemen t Addressing in 64-bit mod e uses existing 32-bit ModR/M and SIB encodings. The ModR/M and SIB displacement sizes do not change. They remain 8 bits or 32 bits and are sign-extended to 64 bits. 2.2.1.4 Direct Memory-Off set MO V s In 64-bit mode, direct memory -offset form s of the MOV instruction ...

  • Intel 253666-024US - page 44

    2-14 Vol. 2A INSTRUCTION F ORMAT size of the memory offset follows the addre ss-size default (64 bits in 64-bit mode). See T able 2-6. 2.2.1.5 Immediates In 64-bit mode, the typical size of immedi ate operands remains 32 bits. When the operand size is 64 bits, the processor sign-extends all immediates to 64 bits prior to their use. Support for 64-b ...

  • Intel 253666-024US - page 45

    Vol. 2A 2-15 INSTRUCTION F ORMAT The ModR/M encoding for RIP-relative addressing does not depend on using prefix. Specifically , the r/m bit field encoding of 10 1B (used to select RIP-relative addressing) is not affected by the REX pref ix. For example, selecting R13 (REX.B = 1, r/m = 101B) with mod = 00B still results in RIP-relative addressing. ...

  • Intel 253666-024US - page 46

    2-16 Vol. 2A INSTRUCTION F ORMAT ...

  • Intel 253666-024US - page 47

    Vol. 2A 3-1 CHAP TER 3 INSTRUCTION SE T R EF ERENCE, A-M This chapter describes the instruction set for the Intel 64 and IA -32 architectures (A-M) in IA-32e, protected, Virtual-8086, and real modes of operation. The set includes general-purpose, x87 FPU, MMX, S SE/SSE2/SSE3/S SSE3, and system instructions. See also Chapter 4, “Instruction Set Re ...

  • Intel 253666-024US - page 48

    3-2 Vol. 2A INSTRUCTION SE T REF ERENCE, A-M 3.1.1.1 Opcode Column in the Ins truction Summary T able The “Opcode” column in the table abov e sh ows the object code produced for each form of the instruction. When possible, codes are given as hexadecimal bytes in the same order in which they appear in memory . Definitions of entries other than h ...

  • Intel 253666-024US - page 49

    Vol. 2A 3-3 INSTRUCTION SE T REF ERENCE, A-M 3.1.1.2 Instruction Column in the Opc ode Summary T able The “Instruction” column gives the syntax of the instruction statement as it would appear in an ASM386 progr am. The following is a list of the symbols used to repre- sent operands in the instruction statements: • rel8 — A relative a ddress ...

  • Intel 253666-024US - page 50

    3-4 Vol. 2A INSTRUCTION SE T REF ERENCE, A-M • ptr16:16, ptr16:32 and ptr16:64 — A far pointer , typically to a code segment different from that of the instruction. The notation 16:16 indicates that the value of the pointer has two parts. The value to th e left of the colon is a 16-bit selector or value destined for the code segment register . ...

  • Intel 253666-024US - page 51

    Vol. 2A 3-5 INSTRUCTION SE T REF ERENCE, A-M • r/m32 — A doubleword gener al-purpose register or memory operand used for instructions whose operand-size attribute is 32 bits. The doubleword general- purpose registers are: EAX, ECX, EDX, EBX, ESP , EBP , ESI, EDI. The con tents of memory are found at the address provided by the effective address ...

  • Intel 253666-024US - page 52

    3-6 Vol. 2A INSTRUCTION SE T REF ERENCE, A-M • Sreg — A segment register . The segment register bit assignments are ES = 0, CS = 1, SS = 2, DS = 3, FS = 4, and GS = 5. • m32fp, m64fp, m80fp — A single-precision, double-precision, and double extended-precision (respectively) floating-point operand in memory . These symbols designate floating ...

  • Intel 253666-024US - page 53

    Vol. 2A 3-7 INSTRUCTION SE T REF ERENCE, A-M • N.P. — Indicates the REX prefix does not affect the legacy instruction in 64-bit mode. • N.I. — Indicates the opcode is treated as a new instruction in 64-bit mode. • N.S. — Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not supported. Using a ...

  • Intel 253666-024US - page 54

    3-8 Vol. 2A INSTRUCTION SE T REF ERENCE, A-M address contained in register SI relative to the SI register’s default segment (DS) or the overridden segment. • P arentheses around the “E” in a general-pu rpose register name, such as (E)SI, indicates that the offset is read from the SI register if the address-size attribute is 16, from the ESI ...

  • Intel 253666-024US - page 55

    Vol. 2A 3-9 INSTRUCTION SE T REF ERENCE, A-M Attribut e for Stack” in Chapter 6, “P rocedure Calls, Interrupts, an d Exceptions, ” of the Intel® 64 and IA-32 Architectures Soft ware Developer’s Manual, Volu me 1 . • SRC — R epresents the source operand. • DEST — R epresents the destination oper and. The following functions are used ...

  • Intel 253666-024US - page 56

    3-10 Vol. 2A INSTRUCTION SE T REF ERENCE, A-M zero (00H); if it is greater than 65535, it is represented by the saturated v alue 65535 (FFFFH). • LowOrderWord(DEST * SRC) — Multiplies a word operand by a word oper and and stores the least significant word of the doubleword result in the destination operand. • HighOrderWord(DEST * SRC) — Mul ...

  • Intel 253666-024US - page 57

    Vol. 2A 3-11 INSTRUCTION SE T REF ERENCE, A-M The addressed bit is numbere d (Offset MOD 8) within the byte at address (BitBase + (BitOffset DIV 8)) where DIV is sign ed division with rounding towards negative infinit y and MOD returns a positive number (se e Figure 3-2). 3.1.1.8 Intel ® C/C + + Compiler Intrinsic s Equiva lents Section The Intel ...

  • Intel 253666-024US - page 58

    3-12 Vol. 2A INSTRUCTION SE T REF ERENCE, A-M See Appendix C, “InteL® C/C++ Compiler In trinsics and Functional Equivalents, ” in the Intel® 64 and IA-3 2 Architectures Software Developer’s Manual, Volume 2B , for more information on using intrinsics. Intri nsics API The benefit of coding with MMX technology intrinsics and the SSE/SSE2/SSE3 ...

  • Intel 253666-024US - page 59

    Vol. 2A 3-13 INSTRUCTION SE T REF ERENCE, A-M • The __m128i data type can hold sixteen by te, eight word, or four doubleword, or two quadword integer v alues. The compiler aligns __m1 28, __m128d, and __m128i local a nd global data to 16-byte boundaries on the stack. T o align in teger , float, or double arr ays, use the declspec statement as des ...

  • Intel 253666-024US - page 60

    3-14 Vol. 2A INSTRUCTION SE T REF ERENCE, A-M Some intrinsics are “composites” because th ey require more than one instruction to implement them. Y ou should be familiar with the hardware features provided by the SSE, SS E2, SSE3 , and M MX tech nology when writing programs with the intrinsics. K eep the following important issues in mind: • ...

  • Intel 253666-024US - page 61

    Vol. 2A 3-15 INSTRUCTION SE T REF ERENCE, A-M letter mnemonic with the correspon ding interrupt v ector number and exception name. See Chapter 5, “Interrupt and Ex ception Handling, ” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A , for a detailed description of the exceptions. Application programmers should ...

  • Intel 253666-024US - page 62

    3-16 Vol. 2A INSTRUCTION SE T REF ERENCE, A-M 3.1.1.12 Real-Addr ess Mo de Exc eptions Section The “Real- Address Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in real-address mode (see T able 3-3). 3.1.1.13 Virtual-8086 Mode Ex ceptions Section The “Virtual-8086 Mode Exceptions” section lists ...

  • Intel 253666-024US - page 63

    Vol. 2A 3-17 INSTRUCTION SE T REF ERENCE, A-M 3.1.1.15 SIMD Floating-Poin t Exc eptions Section The “SIMD Floating-P oint Exceptions” section lists exceptions that can occur when an SSE/SSE2/S SE3 floating-point instruction is executed. All of these exception condi- tions result in a SIMD floating-point error exception (#XM, vector n umber 19) ...

  • Intel 253666-024US - page 64

    3-18 Vol. 2A INSTRUCTION SE T REF ERENCE, A-M 3.2 INSTRUCTIONS (A-M) The remainder of this chapter provides descr iptions of Intel 64 and IA-32 instructions (A-M). See also: Chapter 4, “Instruc tion Set R eference, N-Z, ” in the Intel® 64 and IA-32 Architectures Software Develope r’s Manual, Volume 2B . ...

  • Intel 253666-024US - page 65

    Vol. 2A 3-19 INSTRUCTION SE T REF ERENCE, A-M AAA—ASCII Adjust After Addition AAA—ASCII Adjust A fter Addition Description Adjusts the sum of two unpacked BCD v alues to create an unpacked BCD result. The AL register is the implied source and destin ation operand for this instruction. The AAA instruction is only useful when it follows an ADD in ...

  • Intel 253666-024US - page 66

    3-20 Vol. 2A AAA—ASCII Adjust After Addition INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #UD If the LOCK prefix is used. Real-Addr ess Mode Exc eptions Same exceptions as protected mode. Virtual-8086 Mode E xce ptions Same exceptions as protected mode. Compatibility Mode Exc e p tions Same exceptions as protected mode. 64-Bit Mod ...

  • Intel 253666-024US - page 67

    Vol. 2A 3-21 INSTRUCTION SE T REF ERENCE, A-M AAD—ASCII Adjust AX Before Division AAD—ASCII Adjust AX Be for e Division Description Adjusts two unpacked BCD digits (the least-si gnificant digit in the AL register and the most-significant digit in the AH register) so that a division op er ation performed on the result will yield a correct unpack ...

  • Intel 253666-024US - page 68

    3-22 Vol. 2A AAD—ASCII Adjust AX Before Division INSTRUCTION SE T REF ERENCE, A-M Flags A ffected The SF , ZF , and PF flags are set according to the resulting binary value in the AL register; the OF , AF , and CF flags are undefined. Pro tected Mode Ex ceptions #UD If the LOCK prefix is used. Real-Addr ess Mode Exc eptions Same exceptions as pro ...

  • Intel 253666-024US - page 69

    Vol. 2A 3-23 INSTRUCTION SE T REF ERENCE, A-M AAM—ASCII Adjust AX After Multiply AAM—ASCII Adjust AX A fter Mul tiply Description Adjusts the result of the multiplic ation of two unpacked BCD values to create a pair of unpacked (base 10) BCD values. The AX register is the impli ed source and desti- nation operand for this instruction. The AAM i ...

  • Intel 253666-024US - page 70

    3-24 Vol. 2A AAM—ASCII Adjust AX After Multiply INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #DE If an immediate value of 0 is used. #UD If the LOCK prefix is used. Real-Addr ess Mode Exc eptions Same exceptions as protected mode. Virtual-8086 Mode E xce ptions Same exceptions as protected mode. Compatibility Mode Exc e p tions Sa ...

  • Intel 253666-024US - page 71

    Vol. 2A 3-25 INSTRUCTION SE T REF ERENCE, A-M AAS—ASCII Adjust AL After Subtraction AAS—ASCII Adjust A L A fter Subtr action Description Adjusts the result of the subtraction of two unpacked BCD v alues to create a unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAS instruction is onl ...

  • Intel 253666-024US - page 72

    3-26 Vol. 2A AAS—ASCII Adjust AL After Subtraction INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #UD If the LOCK prefix is used. Real-Addr ess Mode Exc eptions Same exceptions as protected mode. Virtual-8086 Mode E xce ptions Same exceptions as protected mode. Compatibility Mode Exc e p tions Same exceptions as protected mode. 64-B ...

  • Intel 253666-024US - page 73

    Vol. 2A 3-27 INSTRUCTION SE T REF ERENCE, A-M ADC—Add with Carry ADC—Add with Carry Opcode Instruction 64-Bi t Mode Compat/ Leg M ode Description 14 ib ADC AL, imm8 V alid V alid Add with carry imm8 to AL. 15 iw ADC AX, imm16 Valid V alid Add with carry imm16 to AX. 15 id ADC EAX, imm32 V alid V alid Add w ith carry imm32 to EAX . REX.W + 15 id ...

  • Intel 253666-024US - page 74

    3-28 Vol. 2A ADC—Add with Carry INSTRUCTION SE T REF ERENCE, A-M Descripti on Adds the destination operand (first operan d), the source operand (second oper and), and the carry (CF) flag and stores the result in the destination operand. The destina- tion operand can be a register or a memory location; the source operand can be an immediate, a reg ...

  • Intel 253666-024US - page 75

    Vol. 2A 3-29 INSTRUCTION SE T REF ERENCE, A-M ADC—Add with Carry If the DS, ES, FS , or GS register is used to access memory and it contains a NULL segment selector . #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memor ...

  • Intel 253666-024US - page 76

    3-30 Vol. 2A ADD—Add INSTRUCTION SE T REF ERENCE, A-M ADD—Add Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 04 ib ADD AL, imm8 Val i d Val i d A d d imm8 to AL. 05 iw ADD AX, imm16 Va li d Va l i d Ad d imm16 to A X. 05 id ADD EAX, imm32 Va li d Va l i d Ad d imm32 to E AX. REX.W + 05 id ADD RAX, imm32 Val i d N . E. Ad d imm32 si ...

  • Intel 253666-024US - page 77

    Vol. 2A 3-31 INSTRUCTION SE T REF ERENCE, A-M ADD—Add Description Adds the destination operand (first op erand) and the source oper and (second operand) and then stores the result in the destination operand. The destination operand can be a register or a memory location; the source operan d can be an imme- diate, a register , or a memory location ...

  • Intel 253666-024US - page 78

    3-32 Vol. 2A ADD—Add INSTRUCTION SE T REF ERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used but the destination is not a memory operand. Virtual-8086 Mode E xc eptions #GP(0) If a memory oper and effectiv e address is outsid e the CS, DS, ES, FS, or GS segment limit. #SS(0) If a ...

  • Intel 253666-024US - page 79

    Vol. 2A 3-33 INSTRUCTION SE T REF ERENCE, A-M ADDPD—Add Packed Double-Precision Floating-Point Values ADDPD—Add Pack ed Double-Preci sion Floating-Point V alues Description Performs a SIMD add of the two packed doub le-precision floating-point values from the source operand (second oper and) and the destination operand (first operand), and stor ...

  • Intel 253666-024US - page 80

    3-34 Vol. 2A ADDPD—Add Packed Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CRO .EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Addr ess Mode Exc eptions #GP(0) If a memory ...

  • Intel 253666-024US - page 81

    Vol. 2A 3-35 INSTRUCTION SE T REF ERENCE, A-M ADDPD—Add Packed Double-Precision Floating-Point Values #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 82

    3-36 Vol. 2A ADDPS—Add Packed Single-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M ADDPS—Add Pa ck ed Single-Precision Floating-P oint V alues Descripti on Performs a SIMD add of the four packed si ngle-precision floating-point v alues from the source operand (second oper and) and the destination operand (first operand), and ...

  • Intel 253666-024US - page 83

    Vol. 2A 3-37 INSTRUCTION SE T REF ERENCE, A-M ADDPS—Add Packed Single-Precision Floating-Point Values #XM If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE[bit 25] ...

  • Intel 253666-024US - page 84

    3-38 Vol. 2A ADDPS—Add Packed Single-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = ...

  • Intel 253666-024US - page 85

    Vol. 2A 3-39 INSTRUCTION SE T REF ERENCE, A-M ADDSD—Add Scalar Double-Precision Floating-Point Values ADDSD—Add Scalar Double-Preci sion Floating-Poin t V alues Description Adds the low double-precision floating-point values from the source oper and (second operand) and the destination operand (first oper and), and stores the double-preci- sion ...

  • Intel 253666-024US - page 86

    3-40 Vol. 2A ADDSD—Add Scalar Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an ...

  • Intel 253666-024US - page 87

    Vol. 2A 3-41 INSTRUCTION SE T REF ERENCE, A-M ADDSD—Add Scalar Double-Precision Floating-Point Values #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an una ...

  • Intel 253666-024US - page 88

    3-42 Vol. 2A ADDSS—Add Scalar Single-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M ADDSS—Add Scalar Single-Precision Floating-Point V alues Descripti on Adds the low single-precision floating-point values from the source oper and (second operand) and the destination oper and (first operand), and stores the single-precision f ...

  • Intel 253666-024US - page 89

    Vol. 2A 3-43 INSTRUCTION SE T REF ERENCE, A-M ADDSS—Add Scalar Single-Pre cision Floating-Point Values #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an una ...

  • Intel 253666-024US - page 90

    3-44 Vol. 2A ADDSS—Add Scalar Single-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an una ...

  • Intel 253666-024US - page 91

    Vol. 2A 3-45 INSTRUCTION SE T REF ERENCE, A-M ADDSUBPD—Packed Double-FP Add/Subtract ADDSUBPD—Pack ed Double-FP Add/Subtr act Description Adds the double-precision floating-point va lues in the high quadword of the source and destination operands and stores the resu lt in the high quadword of the destina- tion operand. Subtracts the double-prec ...

  • Intel 253666-024US - page 92

    3-46 Vol. 2A ADDSUBPD—Packed Double-FP Add/Subtract INSTRUCTION SE T REF ERENCE, A-M Operat ion xmm1[63:0] = xmm1[63:0] − xmm2/m128[63:0]; xmm1[127:64] = xmm1[127 :64] + xmm2/m128[12 7:64]; Intel C/C + + Compiler Intrinsic Equivalent ADDSUBPD __ m128d _mm_addsub_pd(__m128 d a, __m128d b) Exc e p tions When the source oper and is a memory oper a ...

  • Intel 253666-024US - page 93

    Vol. 2A 3-47 INSTRUCTION SE T REF ERENCE, A-M ADDSUBPD—Packed Double-FP Add/Subtract #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric excep- tion (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID. 01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. Virtual 8086 Mode Exc eptions GP(0) If an y part of the ...

  • Intel 253666-024US - page 94

    3-48 Vol. 2A ADDSUBPD—Packed Double-FP Add/Subtract INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 95

    Vol. 2A 3-49 INSTRUCTION SE T REF ERENCE, A-M ADDSUBPS—Packed Single-FP Add/S ubtract ADDSUBPS—Pack ed Single-FP Add/Subtra ct Description Adds odd-numbered single-precision floati ng-point values of the source oper and (second operand) with the corresponding single-precision floating-point values from the destination operand (first operand); s ...

  • Intel 253666-024US - page 96

    3-50 Vol. 2A ADDSUBPS—Packed Single-FP Add/Subtract INSTRUCTION SE T REF ERENCE, A-M Operat ion xmm1[31:0] = xmm1[31:0] − xmm2/m128[31:0]; xmm1[63:32] = xmm1[6 3:32] + xmm2/m12 8[63:32]; xmm1[95:64] = xmm1[9 5:64] − xmm2/m128[95:64]; xmm1[127:96] = xmm1[127:96 ] + xmm2/m128 [127:96]; Intel C/C + + Compiler Intrinsic Equivalent ADDSUBPS __m128 ...

  • Intel 253666-024US - page 97

    Vol. 2A 3-51 INSTRUCTION SE T REF ERENCE, A-M ADDSUBPS—Packed Single-FP Add/S ubtract #XM For an unmasked Streaming SIMD E xtensions numeric excep- tion, CR4.OSXMMEXCPT[bit 10] = 1. #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric excep- tion (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID. 01H:ECX.SSE3 ...

  • Intel 253666-024US - page 98

    3-52 Vol. 2A ADDSUBPS—Packed Single-FP Add/Subtract INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 99

    Vol. 2A 3-53 INSTRUCTION SE T REF ERENCE, A-M AND—Logical AND AND—Logical AND Opcode Instruction 64-Bit Mode Comp/Leg Mode Descript ion 24 ib AND AL, imm8 Val i d Va l i d AL A N D imm8. 25 iw AND AX, imm16 Va l i d Va l i d A X A N D i mm16. 25 id AND EAX, imm32 Va l i d Va l i d E A X A N D imm32. REX.W + 25 id AND RAX, imm32 Val i d N . E . ...

  • Intel 253666-024US - page 100

    3-54 Vol. 2A AND—Logical AND INSTRUCTION SE T REF ERENCE, A-M Descripti on Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register , or a memory location; the destination operand can be a register or a mem ...

  • Intel 253666-024US - page 101

    Vol. 2A 3-55 INSTRUCTION SE T REF ERENCE, A-M AND—Logical AND #UD If the LOCK prefix is used b u t the destination is not a memory operand. Virtual-8086 Mode Excep tions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. # ...

  • Intel 253666-024US - page 102

    3-56 Vol. 2A ANDPD—Bitwise Logical AND of Packed Do uble-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M ANDPD—Bitwise Logical AND o f Pack ed Double-Precision Floating- Point V al ues Descripti on Performs a bitwise logical AND of the two packed double-precision floating-point values from the source oper and (second op erand) ...

  • Intel 253666-024US - page 103

    Vol. 2A 3-57 INSTRUCTION SE T REF ERENCE, A-M ANDPD—Bitwise Logical AND of Packed Do uble-Precision Floating-Point Values Real-Address Mode Ex ceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary , regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = ...

  • Intel 253666-024US - page 104

    3-58 Vol. 2A ANDPS—Bitwise Logical AND of Packed Si ngle-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M ANDPS—Bitwise Logical AND o f Pack ed Single-Precision Floating-Poin t Va l u e s Descripti on Performs a bitwise logical AND of the four packed single-precision floating-point values from the source oper and (second op eran ...

  • Intel 253666-024US - page 105

    Vol. 2A 3-59 INSTRUCTION SE T REF ERENCE, A-M ANDPS—Bitwise Logical AND of Packed Si ngle -Precision Floating-Point Values Real-Address Mode Ex ceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary , regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] ...

  • Intel 253666-024US - page 106

    3-60 Vol. 2A ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M ANDNPD—Bitwise Logical AND NO T of Pack ed Double-Precision Floating-Poin t V alues Descripti on Inverts the bits of the two packed double-pre cision floating-point v alues in the desti- nation operand (first oper and), ...

  • Intel 253666-024US - page 107

    Vol. 2A 3-61 INSTRUCTION SE T REF ERENCE, A-M ANDNPD—Bitwise Logical AND NOT of Packed Dou ble-Precision Floating-Point Values #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Ex ceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary , regardles ...

  • Intel 253666-024US - page 108

    3-62 Vol. 2A ANDNPS —Bitwise Logical AND NOT of Packed Single-Precision Floating-P oint Values INSTRUCTION SE T REF ERENCE, A-M ANDNPS—Bitwise Logical AND NO T of P ack ed Single-Precision Floating-Poin t V alues Descripti on Inverts the bits of the four packed single-precision floating-point values in the desti- nation operand (first oper and) ...

  • Intel 253666-024US - page 109

    Vol. 2A 3-63 INSTRUCTION SE T REF ERENCE, A-M ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values Real-Address Mode Ex ceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary , regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit ...

  • Intel 253666-024US - page 110

    3-64 Vol. 2A ARPL—Adjust RPL Field of Segment Selector INSTRUCTION SE T REF ERENCE, A-M ARPL —Adjust RPL Field o f Segmen t Selector Descripti on Compares the RPL fields of two segment selectors. The first operand (the destination operand) contains one segment selector and the second operand (source operand) contains the other . (The RPL field ...

  • Intel 253666-024US - page 111

    Vol. 2A 3-65 INSTRUCTION SE T REF ERENCE, A-M ARPL—Adjust RPL Field of Segment Selector ELSE ZF ← 0; FI; FI; Flags A ffected The ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise, it is set to 0. Pr otected Mode Ex ceptions #GP(0) If the destination is located in a non- writable s ...

  • Intel 253666-024US - page 112

    3-66 Vol. 2A BOUND—Check Array Index Against Bounds INSTRUCTION SE T REF ERENCE, A-M BOUND—Check Arra y In dex Agains t Bounds Descripti on BOUND determines if the first operand (arra y index) is within the bounds of an array specified the second operand (bounds operand). The array index is a signed integer located in a register . The bounds op ...

  • Intel 253666-024US - page 113

    Vol. 2A 3-67 INSTRUCTION SE T REF ERENCE, A-M BOUND—Check Array Index Against Bounds Flags A ffected None. Pr otected Mode Ex ceptions #BR If the bounds test fails. #UD If second operand is not a memory location. If the LOCK prefix is used. #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. If the D ...

  • Intel 253666-024US - page 114

    3-68 Vol. 2A BOUND—Check Array Index Against Bounds INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #UD If in 64-bit mode. ...

  • Intel 253666-024US - page 115

    Vol. 2A 3-69 INSTRUCTION SE T REF ERENCE, A-M BSF—Bit Scan Forward BSF—Bit Scan F orward Description Searches the source operand (second operand) for the least significant set bit (1 bit). If a least significant 1 bit is found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a memory l ...

  • Intel 253666-024US - page 116

    3-70 Vol. 2A BSF—Bit Scan Forward INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) If a memory oper and effectiv e address is outsid e the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector . #SS(0) If a memory oper and effective add ress is outside the S S segment limit. #PF ...

  • Intel 253666-024US - page 117

    Vol. 2A 3-71 INSTRUCTION SE T REF ERENCE, A-M BSR—Bit Scan Reverse BSR—Bit Scan Re verse Description Searches the source operand (second operand) for the most significant set bit (1 bit). If a most significant 1 bit is found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a memory loc ...

  • Intel 253666-024US - page 118

    3-72 Vol. 2A BSR—Bit Scan R everse INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) If a memory oper and effectiv e address is outsid e the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector . #SS(0) If a memory oper and effective add ress is outside the S S segment limit. #P ...

  • Intel 253666-024US - page 119

    Vol. 2A 3-73 INSTRUCTION SE T REF ERENCE, A-M BSWAP—Byte Swap BSW AP—Byte S wap Description R everses the byte order of a 32-bit or 64-bit (de stination) register . This instruction is provided for converting little-endian values to big-endian format and vice versa. T o swap bytes in a word value (16-bit regist er), use the XCHG instruction. Wh ...

  • Intel 253666-024US - page 120

    3-74 Vol. 2A BSWAP—Byte S wap INSTRUCTION SE T REF ERENCE, A-M DEST[15:8] ← TEMP[23:16]; DEST[23:16] ← TEMP[15:8]; DEST[31:24] ← TEMP[7:0]; FI; Flags A ffected None. Exc eptions (All Oper ating Modes) #UD If the LOCK prefix is used. ...

  • Intel 253666-024US - page 121

    Vol. 2A 3-75 INSTRUCTION SE T REF ERENCE, A-M BT—Bit Test BT—Bit T est Description Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offs et (specified by the second operand) and stores the value of the bit in the CF flag. The bit base operand can be a register or a ...

  • Intel 253666-024US - page 122

    3-76 Vol. 2A BT—Bit Test INSTRUCTION SE T REF ERENCE, A-M Or , it may access 2 bytes starting from the memory address for a 16-bit oper and, using this relationship: Effective Address + (2 ∗ (BitOffset DIV 16)) It may do so ev en when only a single byte needs to be accessed to reach the given bit. When using this bit addressing mech anism, soft ...

  • Intel 253666-024US - page 123

    Vol. 2A 3-77 INSTRUCTION SE T REF ERENCE, A-M BT—Bit Test Virtual-8086 Mode Excep tions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled an ...

  • Intel 253666-024US - page 124

    3-78 Vol. 2A BTC—Bit Test and Complement INSTRUCTION SE T REF ERENCE, A-M BT C—Bit T est and Complemen t Descripti on Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit o ffset oper and (second operand), stores the value of the bit in the CF flag, and compleme nts th ...

  • Intel 253666-024US - page 125

    Vol. 2A 3-79 INSTRUCTION SE T REF ERENCE, A-M BTC—Bit Test and Complement prefix in the form of REX. W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation CF ← Bit(BitBase, BitOffset); Bit(BitBase, BitOffset) ← NOT Bit(BitBase, BitOffset); Flags A ffected The CF flag co ...

  • Intel 253666-024US - page 126

    3-80 Vol. 2A BTC—Bit Test and Complement INSTRUCTION SE T REF ERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used but the destination is not a memory operand. Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory a ...

  • Intel 253666-024US - page 127

    Vol. 2A 3-81 INSTRUCTION SE T REF ERENCE, A-M BTR—Bit Test and Reset BTR —B it T e st a nd Re set DESCRIPTION Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit of fset operand (second oper and), stores the value of the bit in the CF flag, and clears the selected bit ...

  • Intel 253666-024US - page 128

    3-82 Vol. 2A BTR—Bit Test and Reset INSTRUCTION SE T REF ERENCE, A-M prefix in the form of REX.W promotes oper ation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operat ion CF ← Bit(Bit Base, BitOffset); Bit(BitBase, BitOffset) ← 0; Flags A ffected The CF flag contains the v alue of the sele ...

  • Intel 253666-024US - page 129

    Vol. 2A 3-83 INSTRUCTION SE T REF ERENCE, A-M BTR—Bit Test and Reset #AC(0) If alignment checking is enabled and an unaligned memory referen ce is made. #UD If the LOCK prefix is used b u t the destination is not a memory operand. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory a ddr ...

  • Intel 253666-024US - page 130

    3-84 Vol. 2A BTS—Bit Test and Set INSTRUCTION SE T REF ERENCE, A-M BTS —B it T e st an d S et Descripti on Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit o ffset oper and (second operand), stores the value of the bit in the CF flag, and sets the selected bit in t ...

  • Intel 253666-024US - page 131

    Vol. 2A 3-85 INSTRUCTION SE T REF ERENCE, A-M BTS—Bit Test and Set prefix in the form of REX. W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation CF ← Bit(BitBase, BitOffset); Bit(BitBase, BitOffset) ← 1; Flags A ffected The CF flag contains the value of the selected ...

  • Intel 253666-024US - page 132

    3-86 Vol. 2A BTS—Bit Test and Set INSTRUCTION SE T REF ERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used but the destination is not a memory operand. Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address ...

  • Intel 253666-024US - page 133

    Vol. 2A 3-87 INSTRUCTION SE T REF ERENCE, A-M CALL—Call Procedure CA LL —Call Proc edure Description Saves procedure linking information on th e stack and bran ches to the called proce- dure specified using the target operand. Th e target operand specifies the address of Opcode Instruction 64-Bit Mode Compat/ Leg Mode Descrip tion E8 cw CALL re ...

  • Intel 253666-024US - page 134

    3-88 Vol. 2A CALL—Call Procedure INSTRUCTION SE T REF ERENCE, A-M the first instruction in the called procedure. The operand can be an immediate value, a general-purpose register , or a memory location. This instruction can be used to execute four types of calls: • Near Call — A call to a procedure in the current code segment (the segment cur ...

  • Intel 253666-024US - page 135

    Vol. 2A 3-89 INSTRUCTION SE T REF ERENCE, A-M CALL—Call Procedure or 64 bits). In 64-bit mode the target operand will alw ays be 64-bits because the operand size is forced to 64-bits for near branches. Far Calls in Real-Address or Virtual-8086 Mod e. When executing a far call in real- address or virtual-8086 mode, the processor pushes the current ...

  • Intel 253666-024US - page 136

    3-90 Vol. 2A CALL—Call Procedure INSTRUCTION SE T REF ERENCE, A-M segment selector for the new code segment and the new instruction pointer (offset) from the call gate descriptor . (The offset from the target oper and is ignored when a call gate is used.) On inter-privilege-level calls, the processor switches to the stack for the privilege level ...

  • Intel 253666-024US - page 137

    Vol. 2A 3-91 INSTRUCTION SE T REF ERENCE, A-M CALL—Call Procedure Far Calls in Compatibility Mode. When the processor is operating in compatibility mode, the CALL instruction can be used to perform the following types of far calls: • F ar call to the same privilege level, remaining in compatibility mode • F ar call to the same privilege level ...

  • Intel 253666-024US - page 138

    3-92 Vol. 2A CALL—Call Procedure INSTRUCTION SE T REF ERENCE, A-M pushes the segment selector and stack po inter for the calling procedure’ s stack and the segment selector and instruction po inter for the calling procedure’ s code segment. (Par ameter copy is not supporte d in IA-32e m ode.) Finally , the processor branches to the address of ...

  • Intel 253666-024US - page 139

    Vol. 2A 3-93 INSTRUCTION SE T REF ERENCE, A-M CALL—Call Procedure Note that when using a call gate to perform a far call to a segment at the same priv- ilege level, an implicit stack switch occurs as a result of entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use a segment base of 0x0, the limit is ignored, and the ...

  • Intel 253666-024US - page 140

    3-94 Vol. 2A CALL—Call Procedure INSTRUCTION SE T REF ERENCE, A-M THEN tempRIP ← DEST; (* DEST is r/m64 *) IF stack not lar ge enough for a 8-byte re turn address THEN #SS(0); FI ; Push(RIP); RIP ← tempRIP; FI; IF OperandSize = 32 THEN tempEIP ← DEST; (* DEST is r/m32 *) IF tempEIP is not within code segment limit THEN #GP(0); FI; IF stack ...

  • Intel 253666-024US - page 141

    Vol. 2A 3-95 INSTRUCTION SE T REF ERENCE, A-M CALL—Call Procedure Push(IP); CS ← DEST[31:16]; (* DEST is ptr1 6:16 or [ m16:16 ] *) EIP ← DEST[15:0]; (* DEST i s ptr16:16 or [ m16: 16 ]; clear upper 16 bits *) FI; FI; IF far call and (PE = 1 and V M = 0) (* Protected mode or IA-32e Mode, not virtual-8086 mode*) THEN IF segment selector in tar ...

  • Intel 253666-024US - page 142

    3-96 Vol. 2A CALL—Call Procedure INSTRUCTION SE T REF ERENCE, A-M tempEIP ← tempEIP AND 0000FFFFH; FI; (* Clear upper 1 6 bits *) IF (EFER.LMA = 0 or targe t mode = Compatibility mode) and (tem pEIP outside new code segment limit) THEN #GP(0) ; FI; IF tempEIP is non-cano nical THEN #GP(0) ; FI; IF OperandSize = 32 THEN Push(CS); (* Padd ed with ...

  • Intel 253666-024US - page 143

    Vol. 2A 3-97 INSTRUCTION SE T REF ERENCE, A-M CALL—Call Procedure tempEIP ← DEST(Offset); IF OperandS ize = 16 THEN tempEIP ← tempEIP AND 0000FFFFH; FI; (* Clear uppe r 16 bits *) IF (EFER.LM A = 0 or target mode = Com patibility mode) and (te mpEIP outside new cod e segment limit) THEN #GP(0); FI; IF tempEIP is non-cano nical THEN #GP(0); FI ...

  • Intel 253666-024US - page 144

    3-98 Vol. 2A CALL—Call Procedure INSTRUCTION SE T REF ERENCE, A-M THEN #GP(code segment selector); FI; Read code segment descri ptor; IF code-segment segme nt descriptor does not indicate a cod e segment or code-segment segment de scriptor DPL > CPL THEN #GP(code segment selector); FI; IF IA32_EFER.LMA = 1 AND (code-seg ment segment descriptor ...

  • Intel 253666-024US - page 145

    Vol. 2A 3-99 INSTRUCTION SE T REF ERENCE, A-M CALL—Call Procedure or stack segment DPL ≠ DPL of code segment or stack segment is not a writable data s egment) THEN #TS(SS selector); FI IF IA32_EFER.LMA = 0 and stack segment not present THEN #SS(SS selector); FI; IF CallGateSize = 32 THEN IF stack does no t have room for parameters plu s 16 byte ...

  • Intel 253666-024US - page 146

    3-100 Vol. 2A CALL—Call Procedure INSTRUCTION SE T REF ERENCE, A-M (* Segment des criptor information al so loaded *) Push(oldSS:oldESP); (* From calling procedure *) Push(oldCS:oldEIP); (* Return address to calling procedure *) FI; FI; CPL ← CodeSegment(DPL) CS(RPL) ← CPL END; SAME-PRIVI LEGE: IF CallGateSize = 3 2 THEN IF stack does not hav ...

  • Intel 253666-024US - page 147

    Vol. 2A 3-101 INSTRUCTION SE T REF ERENCE, A-M CALL—Call Procedure THEN #GP(task gate selector); FI; IF task gate not present THEN #NP(task gate selector); FI; Read the TS S segment selector in the task-gate descriptor; IF TSS segment select or local/global bi t is set to local or index not w ithin GDT limits THEN #GP(TSS s elector); FI; Access T ...

  • Intel 253666-024US - page 148

    3-102 Vol. 2A CALL—Call Procedure INSTRUCTION SE T REF ERENCE, A-M #GP(selector) If a code segment or gate or TSS selector index is outside descriptor table limit s. If the segment descriptor pointed to by the segment selector in the destination operand is not for a conforming-code segment, nonconforming-code segment, call gate, task gate, or tas ...

  • Intel 253666-024US - page 149

    Vol. 2A 3-103 INSTRUCTION SE T REF ERENCE, A-M CALL—Call Procedure If the RPL of the new stack segment selector in the TSS is not equal to the DPL of the code segment being accessed. If DPL of the stack segment descriptor for the new stack segment is not equal to the DPL of the code segment descriptor . If the new stack segment is not a writable ...

  • Intel 253666-024US - page 150

    3-104 Vol. 2A CALL—Call Procedure INSTRUCTION SE T REF ERENCE, A-M If code segment or 64 -bit call gate overlaps non-canonical space. If the segment descriptor pointed to by the segment selector in the destination operand is not for a conforming-code segment, nonconforming-code segment, or 64-bit call gate. If the segment descriptor pointed to by ...

  • Intel 253666-024US - page 151

    Vol. 2A 3-105 INSTRUCTION SE T REF ERENCE, A-M CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Double- word to Quadword CBW/CWDE/CDQE—Con vert Byte to W ord/Con vert W ord to Do ubl eword /C onvert Dou ble word to Qu adwo rd Description Double the size of the source operand by means of sign extension. Th e CBW (convert byt ...

  • Intel 253666-024US - page 152

    3-106 Vol. 2A CLC—Clear Carry Flag INSTRUCTION SE T REF ERENCE, A-M CLC—Clear Carry Flag Descripti on Clears the CF flag in the EFLAGS register . Operation is the same in all non-64-bit modes and 64-bit mode. Operat ion CF ← 0; Flags A ffected The CF flag is set to 0. The OF , ZF , SF , AF , and PF flags are unaffected. Exc eptions (All Oper ...

  • Intel 253666-024US - page 153

    Vol. 2A 3-107 INSTRUCTION SE T REF ERENCE, A-M CLD—Clear Direction Flag CLD—Clear Direction Flag Description Clears the DF flag in the EFL AGS register . When the DF flag is set to 0, string ope r a- tions increment the index registers (ESI an d/or EDI). Oper ation is the same in all non-64-bit modes an d 64-bit mode. Operation DF ← 0; Flags ...

  • Intel 253666-024US - page 154

    3-108 Vol. 2A CLFLUSH—Flush Cache Line INSTRUCTION SE T REF ERENCE, A-M CLFL USH—Flush Cache Line Descripti on Inv alidates the cache line that contains th e linear address specified with the source operand from all levels of the processor cache hier archy (data and instruction). The invalidation is broadcast througho ut the cache coherence dom ...

  • Intel 253666-024US - page 155

    Vol. 2A 3-109 INSTRUCTION SE T REF ERENCE, A-M CLFLUSH—Flush Cache Line Operation Flush_Cache_Line(S RC); Intel C/C + + Compiler Intrinsi c Equivalent s CLFLUSH void _mm_clflush(void cons t *p) Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in ...

  • Intel 253666-024US - page 156

    3-110 Vol. 2A CLI — Clear Interrupt Flag INSTRUCTION SE T REF ERENCE, A-M CLI — Clear Interrup t Flag Descripti on If protected-mode virtual interrupts are not enabled, CLI clears the IF flag in the EFLAGS register . No other flags are affe cted. Clearing the IF flag causes the processor to ignore maskable external in terrupts. The IF flag and ...

  • Intel 253666-024US - page 157

    Vol. 2A 3-111 INSTRUCTION SE T REF ERENCE, A-M CLI — Clear Interrupt Flag THEN IF IOPL ← CPL THEN IF ← 0; (* Reset Interrupt Flag *) ELSE IF ((IOPL < CPL) and (CPL = 3) and (PVI = 1)) THEN VIF ← 0; (* Reset Virtual Inte rrupt Flag *) ELSE #GP(0); FI; FI; ELSE (* VM = 1 *) IF IOPL = 3 THEN IF ← 0; (* Reset Interrupt Flag *) ELSE IF (IOP ...

  • Intel 253666-024US - page 158

    3-112 Vol. 2A CLI — Clear Interrupt Flag INSTRUCTION SE T REF ERENCE, A-M Virtual-8086 Mode E xc eptions #GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure. #UD If the LOCK prefix is used. Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #GP(0) If the C ...

  • Intel 253666-024US - page 159

    Vol. 2A 3-113 INSTRUCTION SE T REF ERENCE, A-M CLTS—Clear Task-Switched Flag in CR0 CL TS—Clear T ask-Switched Flag in CR0 Description Clears the task -switche d (TS) flag in the CR 0 register . This instruction is intended for use in operating-system procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allo ...

  • Intel 253666-024US - page 160

    3-114 Vol. 2A CLTS—Clear Task-Switched Flag in CR0 INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #GP(0) If the CPL is greater than 0. #UD If the LOCK prefix is used. ...

  • Intel 253666-024US - page 161

    Vol. 2A 3-115 INSTRUCTION SE T REF ERENCE, A-M CMC—Complement Carry Flag CMC—Complement Carry Flag Description Complements the CF flag in the EFLAGS re gister . CMC operation is the same in non- 64-bit modes and 64-bit mode. Operation EFLAGS.CF[bit 0] ← NOT EFLAGS.CF[bit 0]; Flags A ffected The CF flag contains the complement of its original ...

  • Intel 253666-024US - page 162

    3-116 Vol. 2A CMOVcc—Conditional Move INSTRUCTION SE T REF ERENCE, A-M CMO V cc —Conditional Mo ve Opcode Instruction 64-Bit Mode Compat/ Leg M ode Descript ion 0F 47 /r CMO V A r16, r/m16 Va lid V alid Move if abov e (CF=0 and ZF=0). 0F 47 /r CMO V A r32, r/m32 Va lid V alid Move if abov e (CF=0 and ZF=0). REX.W + 0F 47 /r CMOV A r64, r/m64 Va ...

  • Intel 253666-024US - page 163

    Vol. 2A 3-117 INSTRUCTION SE T REF ERENCE, A-M CMOVcc—Conditional Move Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 4D /r CMOVGE r32, r/m32 V alid Valid Move if grea ter or equa l (SF=OF). REX.W + 0F 4D /r CMOVGE r64, r/m64 Valid N.E. Mov e if greater or equal (SF=OF). 0F 4C /r CMOVL r16, r/m16 V alid Valid Mo ve if less (SF ≠ ...

  • Intel 253666-024US - page 164

    3-118 Vol. 2A CMOVcc—Conditional Move INSTRUCTION SE T REF ERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg M ode Descript ion 0F 43 /r CMO VNC r16, r/m16 V alid V alid Mov e if not carry (CF=0 ). 0F 43 /r CMO VNC r32, r/m32 V alid V alid Mov e if not ca rry (CF=0). REX.W + 0F 43 /r CMOVNC r64, r/m64 V alid N.E. Move if not carry (CF=0). 0F ...

  • Intel 253666-024US - page 165

    Vol. 2A 3-119 INSTRUCTION SE T REF ERENCE, A-M CMOVcc—Conditional Move Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description REX.W + 0F 4B /r CMOVNP r64, r/m64 Va l i d N . E . M ov e i f n o t p a r i t y (PF=0). 0F 49 /r CMOVNS r16, r/m16 V alid V alid Move if no t sign (SF=0). 0F 49 /r CMOVNS r32, r/m32 V alid V alid Move if no t sign (S ...

  • Intel 253666-024US - page 166

    3-120 Vol. 2A CMOVcc—Conditional Move INSTRUCTION SE T REF ERENCE, A-M Descripti on The CMOV cc instructions check the state of one or more of the status flags in the EFLAGS register (CF , OF , PF , SF , and ZF) and perform a mov e operation if the flags are in a specified state (or condition). A condition code ( cc ) is associated with each inst ...

  • Intel 253666-024US - page 167

    Vol. 2A 3-121 INSTRUCTION SE T REF ERENCE, A-M CMOVcc—Conditional Move DEST ← temp; FI; FI; Flags A ffected None. Pr otected Mode Ex ceptions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector . #SS(0) If a memory operand effective ...

  • Intel 253666-024US - page 168

    3-122 Vol. 2A CMOVcc—Conditional Move INSTRUCTION SE T REF ERENCE, A-M 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory referenc ...

  • Intel 253666-024US - page 169

    Vol. 2A 3-123 INSTRUCTION SE T REF ERENCE, A-M CMP—Compare Two Operands CMP—Compare T wo Operands Opcode Instruction 6 4-Bit Mode Compat/ Leg Mode Description 3C ib CMP AL, imm8 Valid V alid Compare imm8 with AL. 3D iw CMP AX, imm16 Valid V alid Compare imm16 with AX. 3D id CMP EAX, imm32 Valid V alid Compare imm32 with EAX. REX.W + 3D id CMP R ...

  • Intel 253666-024US - page 170

    3-124 Vol. 2A CMP—Compare Two Operands INSTRUCTION SE T REF ERENCE, A-M Descripti on Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results. The comparison is performed by subtracting the second operan d from the first operand and then setting the status flags in ...

  • Intel 253666-024US - page 171

    Vol. 2A 3-125 INSTRUCTION SE T REF ERENCE, A-M CMP—Compare Two Operands Virtual-8086 Mode Excep tions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking ...

  • Intel 253666-024US - page 172

    3-126 Vol. 2A CMPPD—Compare Packed Double-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M CMPPD—Compare P acked Double-Pr ecision Floating-Point V alues Descripti on Performs a SIMD compare of the two pack ed double-precision floating-point values in the source operand (second oper and) and the destination operand (first opera ...

  • Intel 253666-024US - page 173

    Vol. 2A 3-127 INSTRUCTION SE T REF ERENCE, A-M CMPPD—Compare Packed Double-Precision Floating-Point Values The unordered relationship is true when at least one of the two source operands being compared is a NaN; the ordered relationship is true when neither source operand is a NaN. A subsequent computational instruction that uses the mask result ...

  • Intel 253666-024US - page 174

    3-128 Vol. 2A CMPPD—Compare Packed Double-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M The greater-than relations that the processor does not implement require more than one instruction to emulate in software an d therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the ...

  • Intel 253666-024US - page 175

    Vol. 2A 3-129 INSTRUCTION SE T REF ERENCE, A-M CMPPD—Compare Packed Double-Precision Floating-Point Values CMPPD for inequality __m128d _mm_cmpneq_pd(__m 128d a, __m128d b) CMPPD for not-less-than __m128d _mm_cmpnlt_pd(__m128d a, __m128d b) CMPPD for not-greater-than __m128d _mm_cmpngt_pd(__m128d a, __m1 28d b) CMPPD for not-greater-tha n-or-equa ...

  • Intel 253666-024US - page 176

    3-130 Vol. 2A CMPPD—Compare Packed Double-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. Virtual-8086 Mode E xc eptions Same excep ...

  • Intel 253666-024US - page 177

    Vol. 2A 3-131 INSTRUCTION SE T REF ERENCE, A-M CMPPS—Compare Packed Single-Precision Floating-Point Values CMPPS—Compare P acked Single-Pr ecision Floating-Poin t V alues Description Performs a SIMD compare of the four packed single-precision floating-point values in the source operand (second oper and) and the destination operand (first operan ...

  • Intel 253666-024US - page 178

    3-132 Vol. 2A CMPPS—Compare Packed Single-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M The greater-than relations not impl emented by the processor require m ore than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corr ...

  • Intel 253666-024US - page 179

    Vol. 2A 3-133 INSTRUCTION SE T REF ERENCE, A-M CMPPS—Compare Packed Single-Precision Floating-Point Values THEN DEST95:6 4] ← FFFFFFFFH; ELSE DEST[95:64] ← 00000000H; FI; IF CMP3 = TRUE THEN DEST[127:96] ← FFFFFFFFH; ELSE DEST[127:96] ← 00000000H; FI; Intel C/C + + Compiler Intrinsi c Equivalent s CMPPS for equality __m128 _mm_cmpeq_ps(__ ...

  • Intel 253666-024US - page 180

    3-134 Vol. 2A CMPPS—Compare Packed Single-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Real-Addr ess Mode Exc eptions #GP(0) If a memory operand is not aligned on a 16-byte boundary , regardless of segment. If any part of the operand lies outside the effective addr ...

  • Intel 253666-024US - page 181

    Vol. 2A 3-135 INSTRUCTION SE T REF ERENCE, A-M CMPPS—Compare Packed Single-Precision Floating-Point Values #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 182

    3-136 Vol. 2A CMPS/CMP SB/CMPSW/CMP SD/CMPSQ—Com pare String O perands INSTRUCTION SE T REF ERENCE, A-M CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compar e S tring Operands Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description A6 CMPS m8, m8 V alid V alid For legacy mode, compar e byte at address DS:(E)SI with byte a t address ES:(E)DI; For 64-bit mode ...

  • Intel 253666-024US - page 183

    Vol. 2A 3-137 INSTRUCTION SE T REF ERENCE, A-M CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands Description Compares the byte, word, doubleword, or qu adword specified with the first source operand with the byte, word, doubleword, or quadword specified with the second source operand and sets the status flags in the EFLAGS register according t ...

  • Intel 253666-024US - page 184

    3-138 Vol. 2A CMPS/CMP SB/CMPSW/CMP SD/CMPSQ—Com pare String O perands INSTRUCTION SE T REF ERENCE, A-M RDI) registers are assumed by the processo r to specify the location of the source operands. The size of the source operands is selected with the mnemonic: CMPSB (byte comparison), CMPSW (word comparis on), CMPSD (doublew ord comparison), or CM ...

  • Intel 253666-024US - page 185

    Vol. 2A 3-139 INSTRUCTION SE T REF ERENCE, A-M CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands (R|E)DI ← (R|E)DI – 2; FI; ELSE IF (Doubleword compa rison) THEN IF DF = 0 THEN (R|E)SI ← (R|E)SI + 4; (R|E)DI ← (R|E)DI + 4; ELSE (R|E)S I ← (R|E)SI – 4; (R|E)DI ← (R|E)DI – 4; FI; ELSE (* Quadword comparison *) THEN IF DF = 0 (R|E ...

  • Intel 253666-024US - page 186

    3-140 Vol. 2A CMPS/CMP SB/CMPSW/CMP SD/CMPSQ—Com pare String O perands INSTRUCTION SE T REF ERENCE, A-M (E)SI ← (E)SI – 4; (E)DI ← (E)DI – 4; FI; FI; FI; Flags A ffected The CF , OF , SF , ZF , AF , and PF flags are set according to the temporary result of the comparison. Pro tected Mode Ex ceptions #GP(0) If a memory oper and effectiv e ...

  • Intel 253666-024US - page 187

    Vol. 2A 3-141 INSTRUCTION SE T REF ERENCE, A-M CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands 64-Bit Mode Exc eptions #SS(0) If a memory a ddress referenc ing the SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled a ...

  • Intel 253666-024US - page 188

    3-142 Vol. 2A CMPSD—Compare Scalar Double-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M CMPSD—Compare Scalar Double-Pr ecision Floating-Point V alues Descripti on Compares the low double-precision floating-point values in the source operand (second operand) and the destin ation operan d (first operand) and returns the result ...

  • Intel 253666-024US - page 189

    Vol. 2A 3-143 INSTRUCTION SE T REF ERENCE, A-M CMPSD—Compare Scalar Double-Precisi on Floating-Point Values The greater-than relations not implemented in the processor require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the progr ammer sh ould reverse the operands of the corr ...

  • Intel 253666-024US - page 190

    3-144 Vol. 2A CMPSD—Compare Scalar Double-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M CMPSD for greater-than-or-equal__m128d _mm_cmpge_sd(__m12 8d a, __m128d b) CMPSD for inequality __m128d _mm_cm pneq_ sd(__m128d a, __m128d b) CMPSD for not-less-than __m128d _mm_cmpnlt_sd(__m 128d a, __m128d b) CMPSD for not-greater-than __ ...

  • Intel 253666-024US - page 191

    Vol. 2A 3-145 INSTRUCTION SE T REF ERENCE, A-M CMPSD—Compare Scalar Double-Precisi on Floating-Point Values If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Virtual-8086 Mode Excep tions Same exceptions as in real address mode. #PF(fault -code) For a page fault. #AC(0) If alignment checking is enabled and ...

  • Intel 253666-024US - page 192

    3-146 Vol. 2A CMPSS—Compare Scalar Single-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M CMPSS—Compare Scalar Single-Pr e cision Floating-Poin t V alues Descripti on Compares the low single-precision floating-point values in the source operand (second operand) and the destin ation operan d (first operand) and returns the resul ...

  • Intel 253666-024US - page 193

    Vol. 2A 3-147 INSTRUCTION SE T REF ERENCE, A-M CMPSS—Compare Scalar Single-Pre cision Floating-Point Values The greater-than relations not implemented in the processor require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the progr ammer sh ould reverse the operands of the corr ...

  • Intel 253666-024US - page 194

    3-148 Vol. 2A CMPSS—Compare Scalar Single-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M CMPSS for less-than __m128 _mm_ cmplt_ss(__m128 a, __m128 b) CMPSS for less-than-or-equal __m128 _mm_cmple_ss(__m1 28 a, __m128 b) CMPSS for greater-than __m128 _mm_cmpgt_ss(__m1 28 a, __m128 b) CMPSS for greater-than-or- equal__m128 _mm_cmp ...

  • Intel 253666-024US - page 195

    Vol. 2A 3-149 INSTRUCTION SE T REF ERENCE, A-M CMPSS—Compare Scalar Single-Pre cision Floating-Point Values #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode Excep tions Same exceptions ...

  • Intel 253666-024US - page 196

    3-150 Vol. 2A CMPXCHG—Compare and Exchange INSTRUCTION SE T REF ERENCE, A-M CMP X CHG—Compare and Ex change Descripti on Compares the value in the AL, AX, EAX, or RAX register with the first oper and (desti- nation operand). If the two v alues are equa l, the second operand (source operand) is loaded into the destination operand. Othe rwise, th ...

  • Intel 253666-024US - page 197

    Vol. 2A 3-151 INSTRUCTION SE T REF ERENCE, A-M CMPXCHG—Compare and Exchange In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional regi sters (R8-R1 5). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the b eginning of this section for encoding da ...

  • Intel 253666-024US - page 198

    3-152 Vol. 2A CMPXCHG—Compare and Exchange INSTRUCTION SE T REF ERENCE, A-M Real-Addr ess Mode Exc eptions #GP If a memory operand effectiv e address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used but the destination is not a memory oper ...

  • Intel 253666-024US - page 199

    Vol. 2A 3-153 INSTRUCTION SE T REF ERENCE, A-M CMPXCHG8B/CMPXCHG16B—Compa re and Exchange Bytes CMP X CHG8B/CMP X CHG16B—Compare and Ex change Bytes Description Compares the 64-bit value in EDX:EAX (o r 128-bit value in RDX:RAX if oper and size is 128 bits) with the operand (destination operand). If the v alues are equal, the 64-bit value in EC ...

  • Intel 253666-024US - page 200

    3-154 Vol. 2A CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes INSTRUCTION SE T REF ERENCE, A-M Operat ion IF (64-Bit Mode and OperandSize = 64) THEN IF (RDX:RAX = DEST) ZF ← 1; DEST ← RCX:RBX; ELSE ZF ← 0; RDX:RAX ← DEST; FI ELSE IF (EDX:EAX = DEST) ZF ← 1; DEST ← ECX:EBX; ELSE ZF ← 0; EDX:EAX ← DEST; FI; FI; Flags A ffected The Z ...

  • Intel 253666-024US - page 201

    Vol. 2A 3-155 INSTRUCTION SE T REF ERENCE, A-M CMPXCHG8B/CMPXCHG16B—Compa re and Exchange Bytes #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Excep tions #UD If the destination operand is not a memory location. #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segmen ...

  • Intel 253666-024US - page 202

    3-156 Vol. 2A COMISD—Compare Scalar Ordered Double-Pre cision Floating-Point Values and Set EFLAGS INSTRUCTION SE T REF ERENCE, A-M CO MISD—Compare Scalar Or dered Do uble-Pr ecision Floating-Poin t V alues and Set EFLA GS Descripti on Compares the double-precision floating-point values in the low quadwords of operand 1 (first operand) and oper ...

  • Intel 253666-024US - page 203

    Vol. 2A 3-157 INSTRUCTION SE T REF ERENCE, A-M COMISD—Compare Scalar Ordered Double-Pre cision Floating-Point Values and Set EFLAGS int _mm_comile_sd (__m1 28d a, __m128d b) int _mm_comigt_sd (__m12 8d a, __m128d b) int _mm_comige_sd (__m 128d a, __m128d b) int _mm_comineq_sd (__m12 8d a, __m128d b) SIMD Floating-Point Ex ceptions Inv alid (if SN ...

  • Intel 253666-024US - page 204

    3-158 Vol. 2A COMISD—Compare Scalar Ordered Double-Pre cision Floating-Point Values and Set EFLAGS INSTRUCTION SE T REF ERENCE, A-M Virtual-8086 Mode E xc eptions Same exceptions as in real address mode. #PF(fault-code) F or a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is ...

  • Intel 253666-024US - page 205

    Vol. 2A 3-159 INSTRUCTION SE T REF ERENCE, A-M COMISS—Compare Scalar Ordered Single-Preci sion Floating-Point Values and Set EFLAGS COMISS—Compare Scalar Or dered Si ngle-Pr ecision Floating-Point V alues and Set EFLAGS Description Compares the single-precision floating-point values in the low doublewords of operand 1 (first oper and) and opera ...

  • Intel 253666-024US - page 206

    3-160 Vol. 2A COMISS—Compare Scalar Ordered Single-Pre cisi on Floating-Point Values and Set EFLAGS INSTRUCTION SE T REF ERENCE, A-M int _mm_comile_ss (__m128 a, __m128 b) int _mm_comigt_ss (_ _m128 a, __m128 b) int _mm_comige_ss (__ m128 a, __m128 b) int _mm_comineq_ss (__m128 a, __m1 28 b) SIMD Floating-Poin t Ex ceptions Inv alid (if SNaN or Q ...

  • Intel 253666-024US - page 207

    Vol. 2A 3-161 INSTRUCTION SE T REF ERENCE, A-M COMISS—Compare Scalar Ordered Single-Preci sion Floating-Point Values and Set EFLAGS Virtual-8086 Mode Excep tions Same exceptions as in real address mode. #PF(fault -code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory referen ce is made. Compatibility Mode Ex cept ...

  • Intel 253666-024US - page 208

    3-162 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification Descripti on The ID flag (bit 21) in the EFLAGS register in dicates support for the CPUID instruc- tion. If a software procedure can set and clear this flag, the processor e xecuting the procedure supports the CPUID instruction. This instruction ope ...

  • Intel 253666-024US - page 209

    Vol. 2A 3-163 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification See also: “Serializing Instructions” in Chapter 7, “Multiple-Processor Management, ” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A AP-485, Intel Processor Identification and the CPUID In struction (Order Number 241618) T able 3-12. ...

  • Intel 253666-024US - page 210

    3-164 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M CPUID lea ves > 3 < 800000 00 are visible on ly when IA32_MISC_ENABLES.BOO T_NT4 [bit 22] = 0 (de fault). Deterministic Cache Par a me ters Leaf 04H NO TES : 04H output depends o n the initial value in ECX . See also: “INPUT EAX = 4: Return s De terministic Ca che Par ...

  • Intel 253666-024US - page 211

    Vol. 2A 3-165 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification MONIT OR/MWAIT L eaf 5H EAX Bits 15-00: Sm allest monitor-line size in bytes (de fault is process or's monito r granula rity) Bits 31-16: Rese rved = 0 EBX Bits 15-00: Largest monit or-line si ze in bytes (default is pr ocessor's monito r granula rity) Bits 31-16: R ...

  • Intel 253666-024US - page 212

    3-166 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M 0AH EAX Bit s 07 - 00: V ersion ID of architectural performance monitoring Bits 15- 08: Numb er of gener al-purpose perf ormance monit oring coun ter per logical processor Bits 23 - 16 : Bit width of general-purpose , performance monitoring co unt e r Bits 31 - 24: Length of ...

  • Intel 253666-024US - page 213

    Vol. 2A 3-167 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification EDX Bits 10-0: Reserv ed Bit 11: S YSCAL L/SY SRET av ailable (when in 64-bit mod e) Bits 19-12: Rese rved = 0 Bit 20: Execute Disable Bit available Bits 28-21: Rese rved = 0 Bit 29: Intel ® 64 T echnology available = 1 Bits 31-30: Rese rved = 0 80000002H EAX EBX ECX EDX Pro ...

  • Intel 253666-024US - page 214

    3-168 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M INPUT EAX = 0: R eturns CPUID’ s Highest V a lue for Basic Pr ocessor In formation and the V e ndor Iden tification String When CPUID executes with EAX set to 0, the processor returns the highest v alue the CPUID recognizes for returning basic processo r information. The va ...

  • Intel 253666-024US - page 215

    Vol. 2A 3-169 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification IA32_BIOS_SIGN _ID R eturns Mi crocode Update Signatur e For processors that support the microcode update facility , the IA32_BIOS_SIGN_ID MSR is loaded with the update signature whenever CPUID executes. The signature is returned in the upper DWORD . For details, see Chapter ...

  • Intel 253666-024US - page 216

    3-170 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M See T able 3-14 for available processor type v alues. Stepping IDs are provided as needed. NO TE See AP -485, Intel Processor Id entifica tion and the CPUID Instruction (Order Number 241618) and Chapter 14 in the Intel® 64 and IA-32 Architectures Software Developer’s Manua ...

  • Intel 253666-024US - page 217

    Vol. 2A 3-171 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification (* Right justify and ze ro-extend 4-bit field. *) FI; (* Show Display_Family as HEX fiel d. *) The Extended Model ID needs to be examined only when the F amily ID is 06H or 0FH. Integrate the field into a display using the following rule: IF (Family_ID = 06H or Family_ID = 0F ...

  • Intel 253666-024US - page 218

    3-172 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M Figur e 3-6. F eature In formatio n R eturned in the ECX R egister OM16524 b CNXT-ID — L1 Context ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ECX TM2 — Thermal Monitor 2 EST — Enhanced Intel SpeedStep® Technology DS-CPL — ...

  • Intel 253666-024US - page 219

    Vol. 2A 3-173 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification T able 3-15. F eature Inf ormation Returned in the ECX Register Bit # Mnemonic Description 0 SSE3 S treaming SIMD Exte nsions 3 (SSE3) . A value o f 1 indicates the pro cessor supports this technology. 1-2 Res erved Reserv ed 3 MONITOR MONITOR/MWAIT . A value o f 1 in dicates ...

  • Intel 253666-024US - page 220

    3-174 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M 21 - 22 Re se rved Reser ved 23 POPCNT A value of 1 indicates tha t the processo r supp orts the PO PCNT instruction. 31 - 24 Re se rved Reser ved Figure 3-7 . F eature In formation R eturned in the ED X Regist er T able 3-15. F eature In formation R etu rned in the ECX Regis ...

  • Intel 253666-024US - page 221

    Vol. 2A 3-175 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification T able 3-16. More on F eature Inf ormation Returned in the EDX R egister Bit # Mnemonic Descrip tion 0 FPU Floating P oint Unit On-Chip. The pr ocessor c ontains an x87 FPU. 1 VME Virtual 8086 Mode Enhance ments. Virtual 8086 mode enhancements, in clu di ng C R4 .VM E for con ...

  • Intel 253666-024US - page 222

    3-176 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M 13 PGE PTE Global Bit. The global bit in page dir ectory entri es (PDEs) and page table entries (PT Es) is supported, indicati ng TLB entries that are c ommon to differen t processes an d need not be flushed. The CR4. PGE bit con trols this feat u re. 14 MCA Machine Check Ar ...

  • Intel 253666-024US - page 223

    Vol. 2A 3-177 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification INPUT EAX = 2: Cache and TLB In formatio n R eturned in EAX, EBX, ECX, ED X When CPUID executes with EAX set to 2, the processor returns inform ation about the processor’s internal caches and TLBs in the EAX, E BX, ECX, an d EDX registers. The encoding is as follows: • Th ...

  • Intel 253666-024US - page 224

    3-178 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M T able 3-17 . Encodi ng of Cache and T LB Descriptor s Descriptor V alue Cache or TLB Description 00H Null descriptor 01H Instructio n TLB: 4 KByte pages, 4-way se t associativ e, 32 entries 02H Instructio n TLB: 4 MByte pages, 4-way se t associative, 2 en tries 03H Data TLB: ...

  • Intel 253666-024US - page 225

    Vol. 2A 3-179 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification 56H Data TLB 0: 4 MByte pages, 4-way se t associat ive, 16 en tries 57H Data TLB 0: 4 KByte pages, 4-way associ ative, 16 entries 5BH Data TLB: 4 KByte and 4 MByte pag es, 64 entries 5CH Da ta TLB: 4 KByte and 4 MByte pages,128 en tries 5DH Dat a TLB: 4 KByte and 4 MByte page ...

  • Intel 253666-024US - page 226

    3-180 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M Example 3-1. Example o f Cache and TLB Interpre tation The first member of the family of Pentium 4 processors returns the following informa- tion about caches and TLBs when the CP UID executes with an input v alue of 2: EAX 66 5B 50 01H EBX 0H ECX 0H EDX 00 7A 70 00H Which me ...

  • Intel 253666-024US - page 227

    Vol. 2A 3-181 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification query maximum number of cores per physical package by executi ng CPUID with EAX=4 and ECX=0. INPUT EAX = 5: Returns MONIT OR and MWAIT F eatures When CPUID executes with EAX set to 5, the processor returns information about features available to MONIT OR/MWAIT instructions. T ...

  • Intel 253666-024US - page 228

    3-182 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M This method (introduced with P entium 4 processors) returns an ASCII br and identifi- cation string and the maximum operating frequency of the processor to the EAX, EBX, ECX, and EDX registers. How Brand Strings Work T o use the brand string method, execute CPUID with EAX inp ...

  • Intel 253666-024US - page 229

    Vol. 2A 3-183 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification T able 3-18 shows the brand string that is returned by the first processor in the Pentium 4 processor family . Ext racting th e Maximum Proc essor Freq uency from Br and Strings Figure 3-9 provides an algorithm which software can use to extract the maximum processor operating ...

  • Intel 253666-024US - page 230

    3-184 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M The Proc essor Brand Inde x Method The br and index method (introduced with P entium ® III Xe on ® processors) provides an entry point into a brand identification table that is maintained in memory by system software and is accessible from system- and user-lev el code. In t ...

  • Intel 253666-024US - page 231

    Vol. 2A 3-185 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification do not support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03 H, br and inde x method is no longer supported. Use brand string method instead. T able 3-19 shows bran d indices that have identification strings associated with th ...

  • Intel 253666-024US - page 232

    3-186 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M IA-32 Architecture Compat ibility CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the Intel486 processor . Operat ion IA32_BIOS_SIGN_ID MSR ← Update with installed mi crocode revision n umber; CASE (EAX) OF EAX = 0: EA ...

  • Intel 253666-024US - page 233

    Vol. 2A 3-187 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification BREAK EAX = 4H: EAX ← Deterministic Cache Para meters Leaf; (* See Table 3-12. *) EBX ← Deterministic Cach e Parameters Leaf; ECX ← Deterministic C ache Parameters Le af; EDX ← Deterministic Cac he Parameters Lea f; BREAK; EAX = 5H: EAX ← MONITOR/MWAIT Leaf; ( * See ...

  • Intel 253666-024US - page 234

    3-188 Vol. 2A CPUID—CPU Identification INSTRUCTION SE T REF ERENCE, A-M EAX = 80000002H: EAX ← Processor Brand String ; EBX ← Processor Brand St ring, continued; ECX ← Processor Brand String, continued; EDX ← Processor Brand String, continued; BREAK; EAX = 80000003H: EAX ← Processor Brand St ring, continued; EBX ← Processor Brand St r ...

  • Intel 253666-024US - page 235

    Vol. 2A 3-189 INSTRUCTION SE T REF ERENCE, A-M CPUID—CPU Identification EAX ← Reserved; (* Information ret urned for highest basic information leaf. *) EBX ← Reserved; (* Information ret urned for highest basic information leaf. *) ECX ← Reserved; (* Information retu rned for highest basic information le af. *) EDX ← Reserved; (* Informat ...

  • Intel 253666-024US - page 236

    3-190 Vol. 2A CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating- Point V alues INSTRUCTION SE T REF ERENCE, A-M CVTDQ2PD—Con vert P ack ed Doubleword In tegers to P ack ed Double- Precision Floating-P oint V alues Descripti on Converts two pack ed signed doubleword integers in the source operan d (second operand) t ...

  • Intel 253666-024US - page 237

    Vol. 2A 3-191 INSTRUCTION SE T REF ERENCE, A-M CVTDQ2PD—Convert Packed Doubleword Intege rs to Packed Double-Precision Floating- Point Values If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Ex ...

  • Intel 253666-024US - page 238

    3-192 Vol. 2A CVTDQ2PS—Convert Packed Doubleword Intege rs to Packed Sin gle-Precision Floating- Point V alues INSTRUCTION SE T REF ERENCE, A-M CVTDQ2PS—Conv ert Pack ed Doubleword In tegers to P acke d Single- Precision Floating-P oint V alues Descripti on Converts four packed signed doubleword integers in the source operand (second operand) t ...

  • Intel 253666-024US - page 239

    Vol. 2A 3-193 INSTRUCTION SE T REF ERENCE, A-M CVTDQ2PS—Convert Packed Doubleword Integers to Packed Si ngle-Precision Floating- Point Values #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bi ...

  • Intel 253666-024US - page 240

    3-194 Vol. 2A CVTDQ2PS—Convert Packed Doubleword Intege rs to Packed Sin gle-Precision Floating- Point V alues INSTRUCTION SE T REF ERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bi ...

  • Intel 253666-024US - page 241

    Vol. 2A 3-195 INSTRUCTION SE T REF ERENCE, A-M CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Double- word Integers CVTPD2DQ—Con vert P ack ed Double-Pre cision Floating-Poin t V alues to Pac ked Do u bl ew or d I nte g er s Description Converts two packed double-precision floating-point v alues in the source oper and ...

  • Intel 253666-024US - page 242

    3-196 Vol. 2A CVTPD2DQ—Conv ert Packed Double-Precision Floating-Point Values to Packed Double- word Integers INSTRUCTION SE T REF ERENCE, A-M If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) F or a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unm ...

  • Intel 253666-024US - page 243

    Vol. 2A 3-197 INSTRUCTION SE T REF ERENCE, A-M CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Double- word Integers #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary , regardless of segment. #PF(fault -code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If a ...

  • Intel 253666-024US - page 244

    3-198 Vol. 2A CVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed Double- word Integers INSTRUCTION SE T REF ERENCE, A-M CVTPD2PI—Con vert P ack ed Double-Pre cision Floating-Poin t V alues to Pa cked Do u bl ew ord I nte ge r s Descripti on Converts two pack ed double-precision floating-point values in the source operand ( ...

  • Intel 253666-024US - page 245

    Vol. 2A 3-199 INSTRUCTION SE T REF ERENCE, A-M CVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed Double- word Integers Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #SS ...

  • Intel 253666-024US - page 246

    3-200 Vol. 2A CVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed Double- word Integers INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory addres ...

  • Intel 253666-024US - page 247

    Vol. 2A 3-201 INSTRUCTION SE T REF ERENCE, A-M CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single- Precision Floating-Point Values CVTPD2PS—Con vert P acked Dou ble-Pre cision Floating-Poin t V alues to Pa ck ed Single-Precision Floating-P oint V alues Description Converts two packed double-precision floating-point ...

  • Intel 253666-024US - page 248

    3-202 Vol. 2A CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single- Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) F or a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] ...

  • Intel 253666-024US - page 249

    Vol. 2A 3-203 INSTRUCTION SE T REF ERENCE, A-M CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single- Precision Floating-Point Values 64-Bit Mode Exc eptions #SS(0) If a memory a ddress referenc ing the SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is n ...

  • Intel 253666-024US - page 250

    3-204 Vol. 2A CVTPI2PD—Convert Packed Doubleword Integers to P acked Double-Precision Floating- Point V alues INSTRUCTION SE T REF ERENCE, A-M CVTPI2PD—Con vert P ack ed Doubleword In tegers to P ack ed Double- Precision Floating-P oint V alues Descripti on Converts two pack ed signed doubleword integers in the source operan d (second operand) ...

  • Intel 253666-024US - page 251

    Vol. 2A 3-205 INSTRUCTION SE T REF ERENCE, A-M CVTPI2PD—Convert Packed Doubleword Intege rs to Packed Double-Precision Floating- Point Values Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault -code) For a page fault. # ...

  • Intel 253666-024US - page 252

    3-206 Vol. 2A CVTPI2PD—Convert Packed Doubleword Integers to P acked Double-Precision Floating- Point V alues INSTRUCTION SE T REF ERENCE, A-M #MF If there is a pending x87 FPU ex ception. #UD I f CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enable ...

  • Intel 253666-024US - page 253

    Vol. 2A 3-207 INSTRUCTION SE T REF ERENCE, A-M CVTPI2PS—Convert Packed Doubleword Integers to Packed Single -Precision Floating- Point Values CVTPI2PS—Con vert P ack ed Doublewor d Integers to P acked Single- Precision Floating-P oint V alues Description Converts two packed signed doubleword integers in the source oper and (second operand) to t ...

  • Intel 253666-024US - page 254

    3-208 Vol. 2A CVTPI2PS—Convert Packed Doubleword Intege rs to Packed Single-Precision Floating- Point V alues INSTRUCTION SE T REF ERENCE, A-M #PF(fault-code) F or a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU ex ception. #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmas ...

  • Intel 253666-024US - page 255

    Vol. 2A 3-209 INSTRUCTION SE T REF ERENCE, A-M CVTPI2PS—Convert Packed Doubleword Integers to Packed Single -Precision Floating- Point Values 64-Bit Mode Exc eptions #SS(0) If a memory a ddress referenc ing the SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault -code) For a page fault. #NM I ...

  • Intel 253666-024US - page 256

    3-210 Vol. 2A CVTPS2DQ—Convert Packed Single-Precision Floating-Poi nt Values to Packed Double- word Integers INSTRUCTION SE T REF ERENCE, A-M CVTPS2DQ—Conv ert Pack ed Single-Precision Floating-Point V alues to Pa cked Do u bl ew ord I nte ge r s Descripti on Converts four packed single-precision floating-point v alues in the source operand (s ...

  • Intel 253666-024US - page 257

    Vol. 2A 3-211 INSTRUCTION SE T REF ERENCE, A-M CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Double- word Integers #SS(0) For an illegal address in the SS segment. #PF(fault -code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an un ...

  • Intel 253666-024US - page 258

    3-212 Vol. 2A CVTPS2DQ—Convert Packed Single-Precision Floating-Poi nt Values to Packed Double- word Integers INSTRUCTION SE T REF ERENCE, A-M If memory oper and is not aligned on a 16-byte boundary , regardless of segment. #PF(fault-code) F or a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM- ...

  • Intel 253666-024US - page 259

    Vol. 2A 3-213 INSTRUCTION SE T REF ERENCE, A-M CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double- Precision Floating-Point Values CVTPS2PD—Con vert Pa cked Single-Pr ecision Floating-Poin t V alues to Pa ck ed Double-Precision Floating-P oint V alues Description Converts two packed single-precision floating-point v ...

  • Intel 253666-024US - page 260

    3-214 Vol. 2A CVTPS2PD—Convert Packed Single-Prec ision Floating-Point Values to Packed Double- Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK pref ...

  • Intel 253666-024US - page 261

    Vol. 2A 3-215 INSTRUCTION SE T REF ERENCE, A-M CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double- Precision Floating-Point Values #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix i ...

  • Intel 253666-024US - page 262

    3-216 Vol. 2A CVTPS 2PI—Convert Packed Single-Precision Floating-Point Values to Packed Double- word Integers INSTRUCTION SE T REF ERENCE, A-M CVTPS2PI—Con vert P ack ed Single-Precision Floating-P oint V alues to Pa cked Do u bl ew ord I nte ge r s Descripti on Converts two pack ed single-precision floating-point values in the source operand ( ...

  • Intel 253666-024US - page 263

    Vol. 2A 3-217 INSTRUCTION SE T REF ERENCE, A-M CVTPS2PI—Convert Packed Single-Precision Floating-Point Values to Packe d Double- word Integers Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault -code) For a page fault. ...

  • Intel 253666-024US - page 264

    3-218 Vol. 2A CVTPS 2PI—Convert Packed Single-Precision Floating-Point Values to Packed Double- word Integers INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory addre ...

  • Intel 253666-024US - page 265

    Vol. 2A 3-219 INSTRUCTION SE T REF ERENCE, A-M CVTSD2SI—Convert Scalar Double-Precision Fl oating-Point Value to Doubleword Integer CVTSD2SI—Con vert Scalar Double-Pre cision Floating-P oint V alue to Doublewor d Integer Description Converts a double-precision floating-point value in the source operand (second operand) to a signed doubleword in ...

  • Intel 253666-024US - page 266

    3-220 Vol. 2A CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer INSTRUCTION SE T REF ERENCE, A-M SIMD Floating-Poin t Ex ceptions Invalid, Precision. Pro tected Mode Ex ceptions #GP(0) For an illegal memory oper and effective address in the CS, DS, ES, FS or GS segm ents. #SS(0) For an illegal address in the SS s ...

  • Intel 253666-024US - page 267

    Vol. 2A 3-221 INSTRUCTION SE T REF ERENCE, A-M CVTSD2SI—Convert Scalar Double-Precision Fl oating-Point Value to Doubleword Integer Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory a ddress referenc ing the SS segment is in a non- canonical form. #GP(0) If the memory address is in a n ...

  • Intel 253666-024US - page 268

    3-222 Vol. 2A CVTSD2SS—Convert Scalar Double-Precision Floa ting-Point Value to Scalar Singl e-Preci- sion Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M CVTSD2SS—Conv ert Scalar Double-Precision Floating-Poin t V alue to Scalar Single-Precision Floating-P oint V alue Descripti on Converts a double-precision floating-poi nt v alue in the ...

  • Intel 253666-024US - page 269

    Vol. 2A 3-223 INSTRUCTION SE T REF ERENCE, A-M CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Singl e-Preci- sion Floating-Point Value #XM If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1 ...

  • Intel 253666-024US - page 270

    3-224 Vol. 2A CVTSD2SS—Convert Scalar Double-Precision Floa ting-Point Value to Scalar Singl e-Preci- sion Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. ...

  • Intel 253666-024US - page 271

    Vol. 2A 3-225 INSTRUCTION SE T REF ERENCE, A-M CVTSI2SD—Convert Doubleword Integer to Scalar Double-P recision Floating-Point Value CVTSI2SD—Con vert Doublewor d Integer to Scalar Double-Precision Floating-Poin t V alue Description Converts a signed doubleword integer (or si gned quadword integer if operand size is 64 bits) in the source operan ...

  • Intel 253666-024US - page 272

    3-226 Vol. 2A CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Poin t Value INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) For an illegal memory oper and effective address in the CS, DS, ES, FS or GS segm ents. #SS(0) For an illegal address in the SS segment. #PF(fault-code) F or a page fault. #NM If CR ...

  • Intel 253666-024US - page 273

    Vol. 2A 3-227 INSTRUCTION SE T REF ERENCE, A-M CVTSI2SD—Convert Doubleword Integer to Scalar Double-P recision Floating-Point Value 64-Bit Mode Exc eptions #SS(0) If a memory a ddress referenc ing the SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault -code) For a page fault. #NM If CR0.TS[b ...

  • Intel 253666-024US - page 274

    3-228 Vol. 2A CVTSI2SS—Convert Doubleword In teger to Scalar Single-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M CVTSI2SS—Con vert Doublew ord In teger to Scalar Single-Precisi on Floating-Poin t V alue Descripti on Converts a signed doubleword integer (or si gned quadword integer if operand size is 64 bits) in the source ope ...

  • Intel 253666-024US - page 275

    Vol. 2A 3-229 INSTRUCTION SE T REF ERENCE, A-M CVTSI2SS—Convert Doubleword Integer to Scalar Single-Prec ision Floating-Point Value SIMD Floating-Point Ex ceptions Precision. Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF ...

  • Intel 253666-024US - page 276

    3-230 Vol. 2A CVTSI2SS—Convert Doubleword In teger to Scalar Single-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a ...

  • Intel 253666-024US - page 277

    Vol. 2A 3-231 INSTRUCTION SE T REF ERENCE, A-M CVTSS2SD—Convert Scalar Single-Pre cision Fl oating-Point Value to S calar Double-Preci- sion Floating-Point Value CVTSS2SD—Con vert Scalar Single- Pre cision Floating-Poin t V alue to Scalar Double-Precision Floating-Poin t V alue Description Converts a single-precision floating-point v alue in th ...

  • Intel 253666-024US - page 278

    3-232 Vol. 2A CVTSS2SD—Convert Scalar Single-Precision Fl oating-Point Value to Scalar Double-Preci- sion Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefi ...

  • Intel 253666-024US - page 279

    Vol. 2A 3-233 INSTRUCTION SE T REF ERENCE, A-M CVTSS2SD—Convert Scalar Single-Pre cision Fl oating-Point Value to S calar Double-Preci- sion Floating-Point Value #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX ...

  • Intel 253666-024US - page 280

    3-234 Vol. 2A CVTSS2SI—Convert Scalar Single-Precis ion Floating-Point Value to Doubleword Integer INSTRUCTION SE T REF ERENCE, A-M CVTSS2SI—Conv ert Scalar Single-Precision Floating-Poin t V alue to Doublewor d Integer Descripti on Converts a single-precision floating-point v alue in the source operand (second operand) to a signed doubleword i ...

  • Intel 253666-024US - page 281

    Vol. 2A 3-235 INSTRUCTION SE T REF ERENCE, A-M CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer SIMD Floating-Point Ex ceptions Inv alid, Precision. Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS seg ...

  • Intel 253666-024US - page 282

    3-236 Vol. 2A CVTSS2SI—Convert Scalar Single-Precis ion Floating-Point Value to Doubleword Integer INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a ...

  • Intel 253666-024US - page 283

    Vol. 2A 3-237 INSTRUCTION SE T REF ERENCE, A-M CVTTPD2PI—Convert with Truncation Packed Do uble-Precision Floating-Point Values to Packed Doubleword Integers CVTTPD2PI—Con vert with T runcati on Pack ed Double-Precision Floating-Poin t V alues to Pack ed Doublewor d Integers Description Converts two packed double-precision floating-point v alue ...

  • Intel 253666-024US - page 284

    3-238 Vol. 2A CVTTPD2PI—Convert with Truncation Packed Double-Preci sion Floating-Point Values to Packed Doubleword Integers INSTRUCTION SE T REF ERENCE, A-M If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) F or a page fault. #MF If there is a pendin ...

  • Intel 253666-024US - page 285

    Vol. 2A 3-239 INSTRUCTION SE T REF ERENCE, A-M CVTTPD2PI—Convert with Truncation Packed Do uble-Precision Floating-Point Values to Packed Doubleword Integers 64-Bit Mode Exc eptions #SS(0) If a memory a ddress referenc ing the SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not ...

  • Intel 253666-024US - page 286

    3-240 Vol. 2A CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers INSTRUCTION SE T REF ERENCE, A-M CVTTPD2DQ—Con vert with T runcati on P ack ed Double-Precision Floating-Poin t V alues to Pack ed Doublewor d Integers Descripti on Converts two pack ed double-precision floating-point valu ...

  • Intel 253666-024US - page 287

    Vol. 2A 3-241 INSTRUCTION SE T REF ERENCE, A-M CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault -code) For a page fault. #NM If CR0.TS[bit 3] = 1. ...

  • Intel 253666-024US - page 288

    3-242 Vol. 2A CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers INSTRUCTION SE T REF ERENCE, A-M #GP(0) If the memory address is in a non-canonical form. If memory oper and is not aligned on a 16-byte boundary , regardless of segment. #PF(fault-code) F or a page fault. #NM If CR0.TS[bit ...

  • Intel 253666-024US - page 289

    Vol. 2A 3-243 INSTRUCTION SE T REF ERENCE, A-M CVTTPS2DQ—Convert with Truncation Packed Si ngle-Precision Floating-P oint Values to Packed Doubleword Integers CVTTPS2DQ—Conv ert with Truncation P acked Single-Pr ecision Floating-Poin t V alues to Pack ed Doublewor d Integers Description Converts four packed single-precision floating-point value ...

  • Intel 253666-024US - page 290

    3-244 Vol. 2A CVTTPS2DQ—Convert with Truncation Packed Si ngle-Precision Floating-Point Values to Packed Doubleword Integers INSTRUCTION SE T REF ERENCE, A-M #PF(fault-code) F or a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point excepti ...

  • Intel 253666-024US - page 291

    Vol. 2A 3-245 INSTRUCTION SE T REF ERENCE, A-M CVTTPS2DQ—Convert with Truncation Packed Si ngle-Precision Floating-P oint Values to Packed Doubleword Integers #PF(fault -code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating -point exce ...

  • Intel 253666-024US - page 292

    3-246 Vol. 2A CVTTPS2PI—Convert with Truncation Packed Single-P recision Floating-Point Values to Packed Doubleword Integers INSTRUCTION SE T REF ERENCE, A-M CVTTPS2PI—Con vert with T runcation Pack ed Single-Precision Floating-Poin t V alues to Pack ed Doublewor d Integers Descripti on Converts two pack ed single-precision floating-point value ...

  • Intel 253666-024US - page 293

    Vol. 2A 3-247 INSTRUCTION SE T REF ERENCE, A-M CVTTPS2PI—Convert with Truncation Packed Single-P recision Floating-Point Values to Packed Doubleword Integers Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault -code) For ...

  • Intel 253666-024US - page 294

    3-248 Vol. 2A CVTTPS2PI—Convert with Truncation Packed Single-P recision Floating-Point Values to Packed Doubleword Integers INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If t ...

  • Intel 253666-024US - page 295

    Vol. 2A 3-249 INSTRUCTION SE T REF ERENCE, A-M CVTTSD2SI—Convert with Truncation Scalar Do uble-Precision Floating-Point Value to Signed Doubleword Integer CVTTSD2SI—Con vert with T runcation Scalar Double-Pr ecision Floating- Poin t V alue to Signed Doubleword Integer Description Converts a double-precision floating-point value in the source o ...

  • Intel 253666-024US - page 296

    3-250 Vol. 2A CVTTSD2SI—Convert with Truncatio n Scalar Double-Precision Floating-Point Value to Signed Doub leword Intege r INSTRUCTION SE T REF ERENCE, A-M Intel C/C + + Compiler Intrinsic Equivalent int _mm_cvttsd_ si32(__m128d a) SIMD Floating-Poin t Ex ceptions Invalid, Precision. Pro tected Mode Ex ceptions #GP(0) For an illegal memory oper ...

  • Intel 253666-024US - page 297

    Vol. 2A 3-251 INSTRUCTION SE T REF ERENCE, A-M CVTTSD2SI—Convert with Truncation Scalar Do uble-Precision Floating-Point Value to Signed Doubleword Integer #AC(0) If alignment checking is enabled and an unaligned memory referen ce is made. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a mem ...

  • Intel 253666-024US - page 298

    3-252 Vol. 2A CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer INSTRUCTION SE T REF ERENCE, A-M CVTTSS2SI—Con vert with T runcation S calar Single-Pr ecision Floating- Poin t V alue to Doublew ord Integer Descripti on Converts a single-precision floating-point v alue in the source operand (sec ...

  • Intel 253666-024US - page 299

    Vol. 2A 3-253 INSTRUCTION SE T REF ERENCE, A-M CVTTSS2SI—Convert with Truncation Scalar Singl e-Precision Floating-Point Value to Doubleword Integer Intel C/C + + Compiler Intrinsi c Equivalent int _mm_cvttss_si32(__m128d a) SIMD Floating-Point Ex ceptions Inv alid, Precision. Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effec ...

  • Intel 253666-024US - page 300

    3-254 Vol. 2A CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer INSTRUCTION SE T REF ERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory add ...

  • Intel 253666-024US - page 301

    Vol. 2A 3-255 INSTRUCTION SE T REF ERENCE, A-M CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword CWD/CDQ/C QO—Conv ert Wor d to Doubleword /Conv ert Doublewor d to Quadwor d Description Doubles the size of the operand in regist er AX, EAX, or RAX (depending on the operand size) by means of sign extension an d stores the resu ...

  • Intel 253666-024US - page 302

    3-256 Vol. 2A CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword INSTRUCTION SE T REF ERENCE, A-M RDX ← SignExtend(RA X); FI; FI; Flags A ffected None. Exc eptions (All Oper ating Modes) #UD If the LOCK prefix is used. ...

  • Intel 253666-024US - page 303

    Vol. 2A 3-257 INSTRUCTION SE T REF ERENCE, A-M DAA—Decimal Adjust AL after Addition DAA—Decimal Adjust A L after Addition Description Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand. The DAA instruction is only useful when it follows an ADD instruction that ad ...

  • Intel 253666-024US - page 304

    3-258 Vol. 2A DAA—Decimal Adjust AL after Addition INSTRUCTION SE T REF ERENCE, A-M Example ADD AL, BL Before : AL = 79H BL = 35H EFLAGS(OSZAP C) = XXXXXX After: AL = AEH BL = 35H EFLAGS(0SZAPC) = 110000 DAA Before: A L = AEH BL = 35H EFLAGS(O SZAPC) = 110000 After: AL = 14H BL = 35H EFLAGS(0S ZAPC) = X00111 DAA Before: A L = 2EH BL = 35H EF LAGS ...

  • Intel 253666-024US - page 305

    Vol. 2A 3-259 INSTRUCTION SE T REF ERENCE, A-M DAS—Decimal Adjust AL after Subtraction DAS—Decimal Adjust A L after Subtr action Description Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the implie d source and destination operand. The DAS instruction is only useful when it foll ...

  • Intel 253666-024US - page 306

    3-260 Vol. 2A DAS—Decimal Adjust AL after Subtraction INSTRUCTION SE T REF ERENCE, A-M Example SUB AL, BL Before : AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111 DAA Before: A L = EEH, BL = 47H, EFLAGS(OS ZAPC) = 010111 After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111 Flags A ffected The CF and AF ...

  • Intel 253666-024US - page 307

    Vol. 2A 3-261 INSTRUCTION SE T REF ERENCE, A-M DEC—Decrement by 1 DEC—Decremen t by 1 Description Subtracts 1 from the destination operand, wh ile preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be update d without disturbing the CF flag. (T o perform ...

  • Intel 253666-024US - page 308

    3-262 Vol. 2A DEC—Decrement by 1 INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) If the destination operand is located in a non-writable segment. If a memory oper and effective address is outside the CS , DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector . #SS(0) If a memory op ...

  • Intel 253666-024US - page 309

    Vol. 2A 3-263 INSTRUCTION SE T REF ERENCE, A-M DEC—Decrement by 1 #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used b u t the destination is not a memory operand. ...

  • Intel 253666-024US - page 310

    3-264 Vol. 2A DIV—Unsigned Divide INSTRUCTION SE T REF ERENCE, A-M DIV—Unsigned Divide Descripti on Divides unsigned the v alue in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (divi- dend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, o r RDX:RAX registers. The source operand can be a general- purpose ...

  • Intel 253666-024US - page 311

    Vol. 2A 3-265 INSTRUCTION SE T REF ERENCE, A-M DIV—Unsigned Divide Operation IF SRC = 0 THEN #DE; FI; (* Divide Error *) IF OperandSiz e = 8 (* Word/Byte Operation *) THEN temp ← AX / SRC; IF temp > FFH THEN #DE; (* Divide error *) ELSE AL ← temp; AH ← AX MOD SRC; FI; ELSE IF Op erandSize = 16 (* Doubleword/word ope ration *) THEN temp ? ...

  • Intel 253666-024US - page 312

    3-266 Vol. 2A DIV—Unsigned Divide INSTRUCTION SE T REF ERENCE, A-M ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword /quadword operation *) THEN temp ← RDX:RAX / SRC; IF temp > FFFFFFFFFFFFFFFFH THEN #DE; (* Divide error *) ELSE RAX ← temp; RDX ← RDX:RAX MO D SRC; FI; FI; FI; Flags A ffected The CF , OF , SF , ZF , AF , and PF f ...

  • Intel 253666-024US - page 313

    Vol. 2A 3-267 INSTRUCTION SE T REF ERENCE, A-M DIV—Unsigned Divide Virtual-8086 Mode Excep tions #DE If the source operand (divisor) is 0. If the quotient is too large for the designated register . #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outsid ...

  • Intel 253666-024US - page 314

    3-268 Vol. 2A DIVPD—Divide Packed Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M DIVPD—Divide Pack ed Double-Precision Floating-P oint V alues Descripti on Performs a SIMD divide of the two packed double-precision floating-point values in the destination operand (first operand) by the two packed double-precision floatin ...

  • Intel 253666-024US - page 315

    Vol. 2A 3-269 INSTRUCTION SE T REF ERENCE, A-M DIVPD—Divide Packed Double-Precision Floating-Poin t Values #XM If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bi ...

  • Intel 253666-024US - page 316

    3-270 Vol. 2A DIVPD—Divide Packed Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[b ...

  • Intel 253666-024US - page 317

    Vol. 2A 3-271 INSTRUCTION SE T REF ERENCE, A-M DIVPS—Divide Packed Single-Precision Floatin g-Point Values DIVPS—Divide Pack ed Single-Precision Floating-Poin t V alues Description Performs a SIMD divide of the four packed single-precision floating-point values in the destination operand (first operand) by the four packed single-pre cision floa ...

  • Intel 253666-024US - page 318

    3-272 Vol. 2A DIVPS—Divide Packed Single-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. ...

  • Intel 253666-024US - page 319

    Vol. 2A 3-273 INSTRUCTION SE T REF ERENCE, A-M DIVPS—Divide Packed Single-Precision Floatin g-Point Values #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. ...

  • Intel 253666-024US - page 320

    3-274 Vol. 2A DIVSD—Divide Scalar Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M DIVSD—Divide Scal ar Double-Precision Floating-P oint V alues Descripti on Divides the low double-precision floating-poi nt value in the destination operand (first operand) by the low double-precision floa ting-point value in the source ope ...

  • Intel 253666-024US - page 321

    Vol. 2A 3-275 INSTRUCTION SE T REF ERENCE, A-M DIVSD—Divide Scalar Double-Precision Floating-P oint Values If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Ad ...

  • Intel 253666-024US - page 322

    3-276 Vol. 2A DIVSD—Divide Scalar Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. ...

  • Intel 253666-024US - page 323

    Vol. 2A 3-277 INSTRUCTION SE T REF ERENCE, A-M DIVSS—Divide Scalar Single-Precision Floating-Point Values DIVSS—Divide Scalar Single-Pre cision Floating-Poin t V alues Description Divides the low single-precision floating-point value in the destination operand (first operand) by the low single-precision floating-point value in the source operan ...

  • Intel 253666-024US - page 324

    3-278 Vol. 2A DIVSS—Divide Scalar Single-P recision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Ad ...

  • Intel 253666-024US - page 325

    Vol. 2A 3-279 INSTRUCTION SE T REF ERENCE, A-M DIVSS—Divide Scalar Single-Precision Floating-Point Values If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. ...

  • Intel 253666-024US - page 326

    3-280 Vol. 2A EMMS—Empty MMX Technology State INSTRUCTION SE T REF ERENCE, A-M EMMS—Emp ty MMX T echnology S tate Descripti on Sets the v alues of all the tags in the x87 FPU tag word to empty (all 1s). This oper a- tion marks the x87 FPU data registers (which are aliased to the MMX technology registers) as available for use by x87 FPU floating ...

  • Intel 253666-024US - page 327

    Vol. 2A 3-281 INSTRUCTION SE T REF ERENCE, A-M EMMS—Empty MMX Technology State Virtual-8086 Mode Excep tions Same exceptions as in protected mode. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 328

    3-282 Vol. 2A ENTER—Make Stack Frame for Procedure Parameters INSTRUCTION SE T REF ERENCE, A-M EN TER—Mak e Stack Fr ame f or Proc edure P arame ters Descripti on Creates a stack frame for a procedure. The first operand (size operand ) specifies the size of the stack fr ame (that is, the number of bytes of dynamic storage allocated on the stack ...

  • Intel 253666-024US - page 329

    Vol. 2A 3-283 INSTRUCTION SE T REF ERENCE, A-M ENTER—Make Stack Frame for Procedure Parameters Operation NestingL evel ← NestingLevel M OD 32 IF 64-Bit Mode (StackSize = 64) THEN Push(RBP); FrameTemp ← RSP; ELSE IF StackSize = 32 THEN Push(EBP); FrameTemp ← ESP; FI; ELSE (* StackSize = 16 *) Push(BP); FrameTemp ← SP; FI; IF NestingLevel = ...

  • Intel 253666-024US - page 330

    3-284 Vol. 2A ENTER—Make Stack Frame for Procedure Parameters INSTRUCTION SE T REF ERENCE, A-M FI; FI; OD; FI; IF 64-Bit Mode (StackSize = 64) THEN Push(FrameTemp); (* Quadword push *) ELSE IF Operan dSize = 32 THEN Push(FrameTemp); FI; (* Doubleword push *) ELSE (* OperandS ize = 16 *) Push(FrameTemp); (* Word push *) FI; CONTINUE: IF 64-Bit Mod ...

  • Intel 253666-024US - page 331

    Vol. 2A 3-285 INSTRUCTION SE T REF ERENCE, A-M ENTER—Make Stack Frame for Procedure Parameters Real-Address Mode Ex ceptions #SS(0) If the new value of the SP or ESP register is outside the stack segment limit. #UD If the LOCK prefix is used. Virtual-8086 Mode Excep tions #SS(0) If the new value of the SP or ESP register is outside the stack segm ...

  • Intel 253666-024US - page 332

    3-286 Vol. 2A F2XM1—Compute 2x–1 INSTRUCTION SE T REF ERENCE, A-M F2XM1—Compute 2 x –1 Descripti on Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in register ST(0 ) and the result is also stored in ST(0). The value of the source operand must lie in the range –1.0 to + 1.0. If ...

  • Intel 253666-024US - page 333

    Vol. 2A 3-287 INSTRUCTION SE T REF ERENCE, A-M F2XM1—Compute 2x–1 #U Result is too small for destination format. #P V alue cannot be represented exactly in destination format. Pr otected Mode Ex ceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Real-Address Mode Ex ceptions Same exceptions as in protected mode. Vi ...

  • Intel 253666-024US - page 334

    3-288 Vol. 2A FABS—A bsolute V alue INSTRUCTION SE T REF ERENCE, A-M F ABS—Absolute V alue Descripti on Clears the sign bit of ST(0) to create the absolute value of the operand. Th e following table shows the results obtained when creating the absolute value of v arious classes of numbers. This instruction’s oper ation is the same in non-64-b ...

  • Intel 253666-024US - page 335

    Vol. 2A 3-289 INSTRUCTION SE T REF ERENCE, A-M FABS—Absolute Value Real- Address Mod e Exc eptions Same exceptions as in protected mode. Virtual-8086 Mo de Ex ceptions Same exceptions as in protected mode. Compatibility Mode Exc eptions Same exceptions as in protected mode. 64-Bit Mode Ex cep tions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 336

    3-290 Vol. 2A FADD/FADDP/FIADD—Add INSTRUCTION SE T REF ERENCE, A-M F ADD/F ADDP/FIADD—Add Descripti on Adds the destination and source operands an d stores the sum in the destination loca- tion. The destination operand is alw ays an FPU register; the source operand can be a register or a memory location. Source operan ds in memory can be in si ...

  • Intel 253666-024US - page 337

    Vol. 2A 3-291 INSTRUCTION SE T REF ERENCE, A-M FADD/FADDP/FIADD—Add The table on the following page shows the results obtained wh en adding various classes of numbers, assuming that neither ov erflow nor underflow occurs. When the sum of two operands with opposite signs is 0, the result is + 0, except for the round toward − ∞ mode, in which c ...

  • Intel 253666-024US - page 338

    3-292 Vol. 2A FADD/FADDP/FIADD—Add INSTRUCTION SE T REF ERENCE, A-M FPU Flags A ffected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Poin t Ex cept ions #IS Stack underflow occurred. #IA Operand is an SNaN v alue or unsupported format. Operands are infinities of unlik e s ...

  • Intel 253666-024US - page 339

    Vol. 2A 3-293 INSTRUCTION SE T REF ERENCE, A-M FADD/FADDP/FIADD—Add #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory referen ce is made. #UD If the LOCK prefix is used. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Ex ...

  • Intel 253666-024US - page 340

    3-294 Vol. 2A FBLD—Load Binary Coded Decimal INSTRUCTION SE T REF ERENCE, A-M FBLD—Load Binary Coded Decimal Descripti on Converts the BCD source oper and into do uble extended-precision floating-point format and pushes the v alue onto the FP U stack. The source operand is loaded without rounding errors. The sign of the source operand is preser ...

  • Intel 253666-024US - page 341

    Vol. 2A 3-295 INSTRUCTION SE T REF ERENCE, A-M FBLD—Load Binary Coded Decimal Real-Address Mode Ex ceptions #GP If a memory operand effective address is outside the CS, DS , ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used ...

  • Intel 253666-024US - page 342

    3-296 Vol. 2A FBSTP—Store BCD Integer and Pop INSTRUCTION SE T REF ERENCE, A-M FBSTP—S tor e BCD Integer and P op Descripti on Converts the v alue in the ST(0) register to an 18-digit packed BCD integer , stores the result in the destination ope r and, and pops th e register stack. If the source v alue is a non-integral v alue, it is rounded to ...

  • Intel 253666-024US - page 343

    Vol. 2A 3-297 INSTRUCTION SE T REF ERENCE, A-M FBSTP—Store BCD Integer and Pop nation operand. If the in valid-oper ation exception is mask ed, the packed BCD indef- inite value is stored in memory . This instruction’ s oper ation is the same in non-64-bit modes and 64-bit mode. Operation DEST ← BCD(ST(0)); PopRegisterStack; FPU Flags Affecte ...

  • Intel 253666-024US - page 344

    3-298 Vol. 2A FBSTP—Store BCD Integer and Pop INSTRUCTION SE T REF ERENCE, A-M #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode E xc eptions #GP(0) If a memory operand effe ctive address is outside the CS, DS , ES, FS, or GS segment limit. #SS(0) If a memory oper and effective add ress is outside the S S s ...

  • Intel 253666-024US - page 345

    Vol. 2A 3-299 INSTRUCTION SE T REF ERENCE, A-M FCHS—Change Sign FCHS—Change Sign Description Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magnitude or vice versa. The following table shows the results obtained when changing the sign of v arious classes of numbers. This instruction’ ...

  • Intel 253666-024US - page 346

    3-300 Vol. 2A FCHS—Change Sign INSTRUCTION SE T REF ERENCE, A-M Real-Addr ess Mode Exc eptions Same exceptions as in protected mode. Virtual-8086 Mode E xce ptions Same exceptions as in protected mode. Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 347

    Vol. 2A 3-301 INSTRUCTION SE T REF ERENCE, A-M FCLEX/FNCLEX—Clear Exceptions FCLEX/FNCL EX —Clear Exc eptions Description Clears the floating-point exception flags (P E, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the stack fault flag (SF), and the busy flag (B) in the FPU status word. The FCLEX instruction checks for and h ...

  • Intel 253666-024US - page 348

    3-302 Vol. 2A FCLEX/FNCLEX—Clear Exceptions INSTRUCTION SE T REF ERENCE, A-M FPU Flags A ffected The PE, UE, OE, ZE , DE, IE, ES, SF , and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are undefined. Floating-Poin t Ex cept ions None. Pro tected Mode Ex ceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK pr ...

  • Intel 253666-024US - page 349

    Vol. 2A 3-303 INSTRUCTION SE T REF ERENCE, A-M FCMOVcc—Floating-Point Conditional Move FCMO V cc —Floating-Point Conditional Mo ve Description T ests the status flags in the EFLAGS registe r and moves the sou rce oper and (second operand) to the destination oper and (first op erand) if the given test condition is true. The condition for each mn ...

  • Intel 253666-024US - page 350

    3-304 Vol. 2A FCMOVcc—Floating-Point Conditio nal Move INSTRUCTION SE T REF ERENCE, A-M Operat ion IF condition TR UE THEN ST(0) ← ST(i); FI; FPU Flags A ffected C1 Set to 0 if stack underflow occurred. C0, C2, C3 Undefined. Floating-Poin t Ex cept ions #IS Stack underflow occurred. Integer F lags A ffected None. Pro tected Mode Ex ceptions #NM ...

  • Intel 253666-024US - page 351

    Vol. 2A 3-305 INSTRUCTION SE T REF ERENCE, A-M FCMOVcc—Floating-Point Conditional Move FC OM/FCOMP/FC OMPP—Compare Floa ting Poin t V a lues Description Compares the contents of register ST(0) and source v alue and sets condition code flags C0, C2, and C3 in the FPU status word according to the results (see the table below). The source operand ...

  • Intel 253666-024US - page 352

    3-306 Vol. 2A FCMOVcc—Floating-Point Conditio nal Move INSTRUCTION SE T REF ERENCE, A-M The FCOMP instruction pops the register stack following the comparison operation and the FCOMPP in struction pops the regist er stack twice following the comparison operation. T o pop the register stack, the processor marks the ST(0) register as empty and incr ...

  • Intel 253666-024US - page 353

    Vol. 2A 3-307 INSTRUCTION SE T REF ERENCE, A-M FCMOVcc—Floating-Point Conditional Move Floating-Point Excep tions #IS Stack underflow occurred. #IA One or both oper ands are NaN values or have unsupported formats. R egister is mark ed empty . #D One or both operands are denormal v alues. Pr otected Mode Ex ceptions #GP(0) If a memory op er and ef ...

  • Intel 253666-024US - page 354

    3-308 Vol. 2A FCMOVcc—Floating-Point Conditio nal Move INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0 ...

  • Intel 253666-024US - page 355

    Vol. 2A 3-309 INSTRUCTION SE T REF ERENCE, A-M FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS FC OMI/FCOMIP/ FUC OMI/FUC OMIP—Compare Floating Poin t V alues and Set EFLAGS Description Performs an unordered comparison of the contents o f registers ST(0) and ST(i) and sets the status flags ZF , PF , and CF in the EFLAG ...

  • Intel 253666-024US - page 356

    3-310 Vol. 2A FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS INSTRUCTION SE T REF ERENCE, A-M If the operation results in an invalid-ari th metic-operand ex ception being r aised, the status flags in the EFLAGS register ar e set only if the exception is masked. The FCOMI/FCOMIP and FUCOMI/FUCOMIP in structions clear the ...

  • Intel 253666-024US - page 357

    Vol. 2A 3-311 INSTRUCTION SE T REF ERENCE, A-M FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS ZF, PF, CF ← 111; FI; FI; FI; IF Instruction is FCOMIP or FUCOMIP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred; otherwise, set to 0. C0, C2, C3 Not affected. Floating-Point Excep tions ...

  • Intel 253666-024US - page 358

    3-312 Vol. 2A FCOS—Cosine INSTRUCTION SE T REF ERENCE, A-M FCOS—Cosine Descripti on Computes the cosine of the source operand in register ST (0) and stores the result in ST(0). The source operand must be given in r adians and must be within the range − 2 63 to + 2 63 . The following table shows the results obtained when taking the cosine of v ...

  • Intel 253666-024US - page 359

    Vol. 2A 3-313 INSTRUCTION SE T REF ERENCE, A-M FCOS—Cosine ST(0) ← cosine(ST(0)); ELSE (* Source op erand is out-of-ran ge *) C2 ← 1; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined if C2 is 1. C2 Set to 1 if outside range ( − 2 63 < source operand < + 2 63 ); ...

  • Intel 253666-024US - page 360

    3-314 Vol. 2A FDECSTP—Decrement Stack-Top Pointer INSTRUCTION SE T REF ERENCE, A-M FDECSTP—Decremen t S tack-T op P ointer Descripti on Subtracts one from the T OP field of the FPU status word (decrements the top-of- stack pointer). If the T OP field contains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one posi ...

  • Intel 253666-024US - page 361

    Vol. 2A 3-315 INSTRUCTION SE T REF ERENCE, A-M FDECSTP—Decrement Stack-Top Pointer Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 362

    3-316 Vol. 2A FDIV/FDIVP/FIDIV—Divide INSTRUCTION SE T REF ERENCE, A-M FDIV /FDIVP/FIDIV—Divide Descripti on Divides the destination operand by the source operand and stores th e result in the destination location. The destination operand (dividend) is alwa ys in an FPU register; the source operand (divisor) can be a register or a memory locati ...

  • Intel 253666-024US - page 363

    Vol. 2A 3-317 INSTRUCTION SE T REF ERENCE, A-M FDIV/FDIVP/FIDIV—Divide If an unmasked divide-by -zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the appropriate sign is stored in the destination operand. The following table shows the results obtained when dividing v arious classes of numbers, assuming ...

  • Intel 253666-024US - page 364

    3-318 Vol. 2A FDIV/FDIVP/FIDIV—Divide INSTRUCTION SE T REF ERENCE, A-M IF Instruction = FDIVP THEN PopRegisterStack; FI; FPU Flags A ffected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Poin t Ex cept ions #IS Stack underflow occurred. #IA Operand is an SNaN v alue or uns ...

  • Intel 253666-024US - page 365

    Vol. 2A 3-319 INSTRUCTION SE T REF ERENCE, A-M FDIV/FDIVP/FIDIV—Divide Virtual-8086 Mode Excep tions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault -code) If a page fau ...

  • Intel 253666-024US - page 366

    3-320 Vol. 2A FDIVR/FDIVRP/FIDIVR—Reverse Divide INSTRUCTION SE T REF ERENCE, A-M FDIVR/FDIVRP/FIDIVR—Re verse Divide Descripti on Divides the source operand by the destination operand and stores the result in the destination location. The destination operand (divisor) is alwa ys in an FPU register; the source operand (dividend) can be a regist ...

  • Intel 253666-024US - page 367

    Vol. 2A 3-321 INSTRUCTION SE T REF ERENCE, A-M FDIVR/FDIVRP/FIDIVR—Reverse Divide The FIDIVR instructions convert an integer source oper and to double extended-preci- sion floating-point format before performing the division. If an unmasked divide-by -zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the ...

  • Intel 253666-024US - page 368

    3-322 Vol. 2A FDIVR/FDIVRP/FIDIVR—Reverse Divide INSTRUCTION SE T REF ERENCE, A-M DEST ← SRC / DEST; FI; FI; IF Instruction = FDIVRP THEN PopRegisterStack; FI; FPU Flags A ffected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Poin t Ex cept ions #IS Stack underflow occur ...

  • Intel 253666-024US - page 369

    Vol. 2A 3-323 INSTRUCTION SE T REF ERENCE, A-M FDIVR/FDIVRP/FIDIVR—Reverse Divide #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Excep tions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segme ...

  • Intel 253666-024US - page 370

    3-324 Vol. 2A FFREE—Free Floating-Point Register INSTRUCTION SE T REF ERENCE, A-M FFR EE—Free Floating-P oint R egister Descripti on Sets the tag in the FPU tag register associated with register ST(i) to empty (11B). The contents of ST(i) and the FPU stack -top pointer (T OP) are not affected. This instruction’s oper ation is the same in non- ...

  • Intel 253666-024US - page 371

    Vol. 2A 3-325 INSTRUCTION SE T REF ERENCE, A-M FICOM/FICOMP—Compare Integer FICO M/FICOMP—Compar e Integer Description Compares the value in ST(0) with an inte ger source operand and sets th e condition code flags C0, C2, and C3 in the FPU sta tus word according to the results (see table below). The integer value is con verted to double extende ...

  • Intel 253666-024US - page 372

    3-326 Vol. 2A FICOM/FICOMP—Compare Integer INSTRUCTION SE T REF ERENCE, A-M ESAC; IF Instruction = FICOMP THEN PopRegisterStack; FI; FPU Flags A ffected C1 Set to 0 if stack underflow occurred; otherwise, set to 0. C0, C2, C3 See table on previous page. Floating-Poin t Ex cept ions #IS Stack underflow occurred. #IA One or both operan ds are NaN v ...

  • Intel 253666-024US - page 373

    Vol. 2A 3-327 INSTRUCTION SE T REF ERENCE, A-M FICOM/FICOMP—Compare Integer #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory referen ce is made. #UD If the LOCK prefix is use ...

  • Intel 253666-024US - page 374

    3-328 Vol. 2A FILD—Load Integer INSTRUCTION SE T REF ERENCE, A-M FILD—Load In teger Descripti on Converts the signed-integer source operand into double extended-precision floating- point format and pushes the v alue onto the FPU register stack. The source oper and can be a word, doubleword, or quadword inte ger . It is loaded without rounding e ...

  • Intel 253666-024US - page 375

    Vol. 2A 3-329 INSTRUCTION SE T REF ERENCE, A-M FILD—Load Integer #UD If the LOCK prefix is used. Real-Address Mode Ex ceptions #GP If a memory operand effective address is outside the CS, DS , ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the ...

  • Intel 253666-024US - page 376

    3-330 Vol. 2A FINCSTP—Increment Stack-Top Pointer INSTRUCTION SE T REF ERENCE, A-M FINCSTP—Incremen t S tack-T op Pointer Descripti on Adds one to the TOP field of the FPU st atus word (increments the top-of -stack pointer). If the TOP field contains a 7, it is se t to 0. The effect of this instruction is to rotate the stack by one position. Th ...

  • Intel 253666-024US - page 377

    Vol. 2A 3-331 INSTRUCTION SE T REF ERENCE, A-M FINCSTP—Increment Stack-Top Pointer Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 378

    3-332 Vol. 2A FINIT/FNINIT—Initialize Floating-Point Unit INSTRUCTION SE T REF ERENCE, A-M FINIT /FNINIT—Initializ e Floating-Point Unit Descripti on Sets the FPU control, status, tag, instruction pointer , and data pointer registers to their default states. The FPU control word is set to 037FH (round to nearest, all exceptions masked, 64-bit p ...

  • Intel 253666-024US - page 379

    Vol. 2A 3-333 INSTRUCTION SE T REF ERENCE, A-M FINIT/FNINIT—Initialize Floating-Point Unit Operation FPUControlW ord ← 037FH; FPUStatus Word ← 0; FPUTagWo rd ← FFFFH; FPUDataPoin ter ← 0; FPUInstructionPoin ter ← 0; FPULastInstructionOpcode ← 0; FPU Flags Affected C0, C1, C2, C3 set to 0. Floating-Point Excep tions None. Pr otected Mo ...

  • Intel 253666-024US - page 380

    3-334 Vol. 2A FIST/FISTP—Store Integer INSTRUCTION SE T REF ERENCE, A-M FIST /FISTP—S tore In teger Descripti on The FIST instruction converts the value in the ST(0) reg ister to a signed integer and stores the result in the de stination oper and. V alues can be stored in word or double - word integer format. The destination oper and specifies ...

  • Intel 253666-024US - page 381

    Vol. 2A 3-335 INSTRUCTION SE T REF ERENCE, A-M FIST/FISTP—Store Integer If the source value is a non-integral value, it is rounded to an integer value, according to the rounding mode spe cified by th e RC field of the FPU control word. If the converted v alue is too large for the de stination format, or if the source operand is an ∞ , SNaN, QNA ...

  • Intel 253666-024US - page 382

    3-336 Vol. 2A FIST/FISTP—Store Integer INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) If the destination is located in a non-writable segment. If a memory oper and effective address is outside the CS , DS, ES, FS, or GS segment limit. If the DS, ES, FS , or GS register is used to access memory and it contains a NULL segment s ...

  • Intel 253666-024US - page 383

    Vol. 2A 3-337 INSTRUCTION SE T REF ERENCE, A-M FIST/FISTP—Store Integer #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pend ing x87 FPU exception. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is u ...

  • Intel 253666-024US - page 384

    3-338 Vol. 2A FISTTP—Store Integer with Truncation INSTRUCTION SE T REF ERENCE, A-M FISTTP—S tor e Integer with T runcation Descripti on FISTTP conv erts the value in ST into a si gned integer using truncation (chop) as rounding mode, transfers the result to the destination, and pop ST . F IST TP accepts word, short integer , and long integer d ...

  • Intel 253666-024US - page 385

    Vol. 2A 3-339 INSTRUCTION SE T REF ERENCE, A-M FISTTP—Store Integer with Truncation Numeric Ex ceptions Inv alid, Stack Invalid (stack underflow), Precision. Pr otected Mode Ex ceptions #GP(0) If the destination is in a nonwritable segment. For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal ...

  • Intel 253666-024US - page 386

    3-340 Vol. 2A FISTTP—Store Integer with Truncation INSTRUCTION SE T REF ERENCE, A-M 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU ex ception. #PF(fault-cod ...

  • Intel 253666-024US - page 387

    Vol. 2A 3-341 INSTRUCTION SE T REF ERENCE, A-M FLD—Load Floating Point Value FLD—Load Floating P oint V alue Description Pushes the source operand onto the FPU register stack. The source operand can be in single-precision, double-precision, or do uble extended-precision floating-point format. If the source oper and is in single-p recision or do ...

  • Intel 253666-024US - page 388

    3-342 Vol. 2A FLD—Load Floating Point Value INSTRUCTION SE T REF ERENCE, A-M #IA Source op er and is an SNaN. D oes not occur if the source operand is in double extended-p recision floating-point format (FLD m80fp or FLD ST(i)). #D Source operand is a denormal value. Does not occur if the source operand is in double ex tended-precision floating-p ...

  • Intel 253666-024US - page 389

    Vol. 2A 3-343 INSTRUCTION SE T REF ERENCE, A-M FLD—Load Floating Point Value Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory a ddress referenc ing the SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = ...

  • Intel 253666-024US - page 390

    3-344 Vol. 2A FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant INSTRUCTION SE T REF ERENCE, A-M FLD1/FLDL2T /FLDL2E/FLDPI/FLDL G2/FLDLN2/FLDZ—Load Constan t Descripti on Push one of seven commonly used constant s (in double extended-precision floating- point format) onto the FPU register stack. The constants that can be loaded with the ...

  • Intel 253666-024US - page 391

    Vol. 2A 3-345 INSTRUCTION SE T REF ERENCE, A-M FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant Floating-Point Excep tions #IS Stack ov erflow occurred. Pr otected Mode Ex ceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pend ing x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Ex ceptions Same excep ...

  • Intel 253666-024US - page 392

    3-346 Vol. 2A FLDCW—Load x87 FPU Control Word INSTRUCTION SE T REF ERENCE, A-M FLDCW—Load x87 FPU Con trol W ord Descripti on Loads the 16-bit source operand into the FPU control word. The source operand is a memory location. This instruction is typica lly used to establish or change the FPU’ s mode of operation. If one or more exception flag ...

  • Intel 253666-024US - page 393

    Vol. 2A 3-347 INSTRUCTION SE T REF ERENCE, A-M FLDCW—Load x87 FPU Control Word #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Address Mode Ex ceptions #GP If a memory operand effective address is outside the CS, DS , ES, FS, or GS segme ...

  • Intel 253666-024US - page 394

    3-348 Vol. 2A FLDENV—Load x87 FPU Environment INSTRUCTION SE T REF ERENCE, A-M FLDENV—L oad x87 FPU Envir onment Descripti on Loads the comp lete x87 FPU oper ating envi ronm ent from memory into the FPU regis- ters. The source operand specifies the first byte of the oper ating-environment data in memory . This data is typically written to the ...

  • Intel 253666-024US - page 395

    Vol. 2A 3-349 INSTRUCTION SE T REF ERENCE, A-M FLDENV—Load x87 FPU Environment FPU Flags Affected The C0, C1, C2, C3 flags are loaded. Floating-Point Excep tions None; however , if an unma sked ex ception is lo aded in the status word, it is generated upon execution of the next “waiting” floating-point instruction. Pr otected Mode Ex ceptions ...

  • Intel 253666-024US - page 396

    3-350 Vol. 2A FLDENV—Load x87 FPU Environment INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3 ...

  • Intel 253666-024US - page 397

    Vol. 2A 3-351 INSTRUCTION SE T REF ERENCE, A-M FMUL/FMULP/FIMUL—Multiply FMUL/FMULP/FIMUL—Multiply Description Multiplies the destination and source operan ds and stores the product in the destina- tion location. The destination oper and is always an FPU data register; the source operand can be an FPU data register or a memory location. Source ...

  • Intel 253666-024US - page 398

    3-352 Vol. 2A FMUL /FMULP/FIMUL—Multiply INSTRUCTION SE T REF ERENCE, A-M The FIMUL instructions convert an intege r source oper and to double extended- precision floating-point format before performing the multiplication. The sign of the result is alw ays the exclusiv e-OR of the source signs, even if one or more of the values being multiplied i ...

  • Intel 253666-024US - page 399

    Vol. 2A 3-353 INSTRUCTION SE T REF ERENCE, A-M FMUL/FMULP/FIMUL—Multiply FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undef ined. Floating-Point Excep tions #IS Stack underflow occurred. #IA Operand is an SNaN v alue or unsupported format. One operand is ± 0 and the other ...

  • Intel 253666-024US - page 400

    3-354 Vol. 2A FMUL /FMULP/FIMUL—Multiply INSTRUCTION SE T REF ERENCE, A-M #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit M ...

  • Intel 253666-024US - page 401

    Vol. 2A 3-355 INSTRUCTION SE T REF ERENCE, A-M FNOP—No Operation FNOP—No Operation Description Performs no FPU oper ation. This instruc tio n takes up space in the instruction stream but does not affect the FPU or machin e context, except the EIP register . This instruction’ s oper ation is the same in non-64-bit modes and 64-bit mode. FPU Fl ...

  • Intel 253666-024US - page 402

    3-356 Vol. 2A FPATAN—Partial Arctangent INSTRUCTION SE T REF ERENCE, A-M FP A T AN—P artial Arctangen t Descripti on Computes the arctangent of the source op er and in register ST(1) divided by the source operand in register ST(0), stores the result in ST(1), and pops the FPU register stack. The result in re gister ST(0) has the same sign as th ...

  • Intel 253666-024US - page 403

    Vol. 2A 3-357 INSTRUCTION SE T REF ERENCE, A-M FPATAN—Partial Arctangent There is no restriction on the range of source operands that FP A T AN can accept. This instruction’ s oper ation is the same in non-64-bit modes and 64-bit mode. IA-32 Architectur e Compatibility The source operands for this instructio n are restricted for the 80287 math ...

  • Intel 253666-024US - page 404

    3-358 Vol. 2A FPATAN—Partial Arctangent INSTRUCTION SE T REF ERENCE, A-M Floating-Poin t Ex cept ions #IS Stack underflow occurred. #IA Source operand is an SNaN value or unsupported format. #D Source operand is a denormal value. #U Result is too small for destination format. #P V alue cannot be represented exactly in destination format. Pro tect ...

  • Intel 253666-024US - page 405

    Vol. 2A 3-359 INSTRUCTION SE T REF ERENCE, A-M FPREM—Partial Remainder FPR EM—Partial R emainder Description Computes the remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modu lus ), and stores the result in ST(0). The remainder represents the following value: Re ...

  • Intel 253666-024US - page 406

    3-360 Vol. 2A FPREM—Partial Remainder INSTRUCTION SE T REF ERENCE, A-M The FPREM instruction does not compute th e remainder specified in IEEE Std 754. The IEEE specified remainder can be computed with the FPREM1 instruction. The FPREM instruction is provided for compatib ility with the Intel 8087 and Intel287 math coprocessors. The FPREM instruc ...

  • Intel 253666-024US - page 407

    Vol. 2A 3-361 INSTRUCTION SE T REF ERENCE, A-M FPREM—Partial Remainder FPU Flags Affected C0 Set to bit 2 (Q2) of the quotient. C1 Set to 0 if stack underflow o ccurred; otherwise, set to least significant bit of quotient (Q0). C2 Set to 0 if reduction comple te; set to 1 if incomplete. C3 Set to bit 1 (Q1) of the quotient. Floating-Point Excep t ...

  • Intel 253666-024US - page 408

    3-362 Vol. 2A FPREM1—Partial Remainder INSTRUCTION SE T REF ERENCE, A-M FPR EM1—Partial R emainder Descripti on Computes the IEEE remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modulus ), and stores the result in ST(0). The remainde r represents the following va ...

  • Intel 253666-024US - page 409

    Vol. 2A 3-363 INSTRUCTION SE T REF ERENCE, A-M FPREM1—Partial Remainder The FPREM1 instruction computes the rema inder specified in IEEE Standard 754. This instruction operates differently from the FPREM instruction in the w ay that it rounds the quotient of ST(0) divide d by ST(1) to an integer (see the “Operation” section below). Like the F ...

  • Intel 253666-024US - page 410

    3-364 Vol. 2A FPREM1—Partial Remainder INSTRUCTION SE T REF ERENCE, A-M C2 Set to 0 if reduction complete; set to 1 if incomplete. C3 Set to bit 1 (Q1) of the quotient. Floating-Poin t Ex cept ions #IS Stack underflow occurred. #IA Source operand is an SNaN v alue, modulus (divisor) is 0, divi- dend is ∞ , or unsupported format. #D Source opera ...

  • Intel 253666-024US - page 411

    Vol. 2A 3-365 INSTRUCTION SE T REF ERENCE, A-M FPTAN—Partial Tangent F P TA N — P a r t i a l Ta n g e n t Description Computes the tangent of the source operand in register ST(0), stores the result in ST(0), and pushes a 1.0 onto the FPU re gister stack. The source operand must be given in radians and must be less than ±2 63 . The follow ing ...

  • Intel 253666-024US - page 412

    3-366 Vol. 2A FPTAN—Partial Tangent INSTRUCTION SE T REF ERENCE, A-M This instruction’s oper ation is the same in non-64-bit modes and 64-bit mode. Operat ion IF ST(0) < 2 63 THEN C2 ← 0; ST(0) ← tan(ST(0)); TOP ← TOP − 1; ST(0) ← 1.0; ELSE (* Source oper an d is out-o f-range *) C2 ← 1; FI; FPU Flags A ffected C1 Set to 0 if sta ...

  • Intel 253666-024US - page 413

    Vol. 2A 3-367 INSTRUCTION SE T REF ERENCE, A-M FPTAN—Partial Tangent Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 414

    3-368 Vol. 2A FRNDINT—Round to Integer INSTRUCTION SE T REF ERENCE, A-M FRNDIN T—Round t o Integer Descripti on Rounds the source v alue in the ST(0) register to the nearest integral value, depending on the current rounding mode (setting of the RC field of the FPU control word), and stores the result in ST(0). If the source value is ∞ , the v ...

  • Intel 253666-024US - page 415

    Vol. 2A 3-369 INSTRUCTION SE T REF ERENCE, A-M FRNDINT—Round to Integer Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 416

    3-370 Vol. 2A FRSTOR—Restore x87 FPU State INSTRUCTION SE T REF ERENCE, A-M FRST OR—Res tore x87 FPU S tate Descripti on Loads the FPU state (operating environmen t and register stack) from the memory area specified with the source operand. Th is state data is typically written to the specified memory location by a previous FSAVE/FNSA VE instru ...

  • Intel 253666-024US - page 417

    Vol. 2A 3-371 INSTRUCTION SE T REF ERENCE, A-M FRSTOR—Restore x87 FPU State ST(7) ← SRC[ST(7)]; FPU Flags Affected The C0, C1, C2, C3 flags are loaded. Floating-Point Excep tions None; however , this oper ation might unmask an existing exception that has been detected but not generated, because it was masked. Here, the exception is gener- ated ...

  • Intel 253666-024US - page 418

    3-372 Vol. 2A FRSTOR—Restore x87 FPU State INSTRUCTION SE T REF ERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a ...

  • Intel 253666-024US - page 419

    Vol. 2A 3-373 INSTRUCTION SE T REF ERENCE, A-M FSAVE/FNSAVE—Store x87 FPU State FSA V E/FNSA VE—S tore x87 FPU S tate Description Stores the current FPU state (operating en vironment and register stack) at the spe c- ified destination in memory , and then re-initializes the FPU. The FSAVE instruction checks for and handles pending unmask ed flo ...

  • Intel 253666-024US - page 420

    3-374 Vol. 2A FSAVE/FNSAVE—Store x87 FPU State INSTRUCTION SE T REF ERENCE, A-M instructions separately . If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception. This instruction’s oper ation is the same in non-64-bit modes and 64-bit mode. IA-32 Architecture Compat ibilit ...

  • Intel 253666-024US - page 421

    Vol. 2A 3-375 INSTRUCTION SE T REF ERENCE, A-M FSAVE/FNSAVE—Store x87 FPU State FPU Flags Affected The C0, C1, C2, and C3 flags are sa ved and then cleared. Floating-Point Excep tions None. Pr otected Mode Ex ceptions #GP(0) If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS , ES, FS, ...

  • Intel 253666-024US - page 422

    3-376 Vol. 2A FSAVE/FNSAVE—Store x87 FPU State INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc eptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] ...

  • Intel 253666-024US - page 423

    Vol. 2A 3-377 INSTRUCTION SE T REF ERENCE, A-M FSCALE—Scale FSCAL E—Scale Description T runcates the v alue in the source operand (toward 0) to an integral v alue and adds that value to the exponent of the destin ation operand. The destination and source operands are floating-point v alues located in registers ST(0) and ST(1), respectively . Th ...

  • Intel 253666-024US - page 424

    3-378 Vol. 2A FSCALE—Scale INSTRUCTION SE T REF ERENCE, A-M before the FXTRACT operation was performed. The FSTP ST(1) i nstruction overwrites the exponent (extracted by the FXTRACT inst ruction) with the recreated value, which returns the stack to its original state with only one register [ST(0)] occupied. This instruction’s oper ation is the ...

  • Intel 253666-024US - page 425

    Vol. 2A 3-379 INSTRUCTION SE T REF ERENCE, A-M FSIN—Sine FSIN—Sine Description Computes the sine of the source op er and in register ST(0) and stores the result in ST(0). The source operand must be given in radians and must be within the range − 2 63 to + 2 63 . The following table shows the results obtained when taking the sine of various cl ...

  • Intel 253666-024US - page 426

    3-380 Vol. 2A FSIN—Sine INSTRUCTION SE T REF ERENCE, A-M ST(0) ← sin(ST(0)); ELSE (* Source opera nd out of range *) C2 ← 1; FI; FPU Flags A ffected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C2 Set to 1 if outside range ( − 2 63 < source operand < + 2 63 ); other- wise, set to 0. C0, C3 ...

  • Intel 253666-024US - page 427

    Vol. 2A 3-381 INSTRUCTION SE T REF ERENCE, A-M FSINCOS—Sine and Cosine FSINC OS—Sine and Cosine Description Computes both the sine and the cosine of the source oper and in register ST(0), stores the sine in ST(0), and pushes the cosine onto the top of the FPU register stack. (This instruction is faster than executing the FSIN and FCOS instructi ...

  • Intel 253666-024US - page 428

    3-382 Vol. 2A FSINCOS—Sine and Cosine INSTRUCTION SE T REF ERENCE, A-M Operat ion IF ST(0) < 2 63 THEN C2 ← 0; TEMP ← cosine(ST(0)); ST(0) ← sine(ST(0)); TOP ← TOP − 1; ST(0) ← TEMP; ELSE (* Source opera nd out of range *) C2 ← 1; FI; FPU Flags A ffected C1 Set to 0 if stack underflow occurred; set to 1 of stack overflow occurs. ...

  • Intel 253666-024US - page 429

    Vol. 2A 3-383 INSTRUCTION SE T REF ERENCE, A-M FSINCOS—Sine and Cosine Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 430

    3-384 Vol. 2A FSQRT—Square Root INSTRUCTION SE T REF ERENCE, A-M FSQR T—Square R oot Descripti on Computes the square root of the source v alue in the ST(0) register and stores the result in ST(0). The following table shows the results obtained when taking the square root of various classes of numbers, assuming that neither overflow nor underfl ...

  • Intel 253666-024US - page 431

    Vol. 2A 3-385 INSTRUCTION SE T REF ERENCE, A-M FSQRT—Square Root Source operand is a negativ e valu e (except for − 0). #D Source operand is a denormal value. #P V alue cannot be represented exactly in destination format. Pr otected Mode Ex ceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pend ing x87 FPU exception. #UD If the ...

  • Intel 253666-024US - page 432

    3-386 Vol. 2A FST/FSTP—Store Floating Point Value INSTRUCTION SE T REF ERENCE, A-M FST /FSTP—Stor e Floating Poin t V alue Descripti on The FST instruction copies the value in the ST(0) register to the destination operand, which can be a memory location or another register in the FPU register stack. When storing the value in memory , the v alue ...

  • Intel 253666-024US - page 433

    Vol. 2A 3-387 INSTRUCTION SE T REF ERENCE, A-M FST/FSTP—Store Floating Point Value If the destination operand is a non-empt y register , the inv alid-ope r a tion exception is not generated. This instruction’ s oper ation is the same in non-64-bit modes and 64-bit mode. Operation DEST ← ST(0); IF Instruction = FSTP THEN PopRegisterStack; FI; ...

  • Intel 253666-024US - page 434

    3-388 Vol. 2A FST/FSTP—Store Floating Point Value INSTRUCTION SE T REF ERENCE, A-M Real-Addr ess Mode Exc eptions #GP If a memory operand effectiv e address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix i ...

  • Intel 253666-024US - page 435

    Vol. 2A 3-389 INSTRUCTION SE T REF ERENCE, A-M FSTCW/FNSTCW—Store x87 FPU Control Word FST CW/FNST CW—S tore x87 FPU Con tr ol W ord Description Stores the current value of the FPU contro l word at the specified destination in memory . The FST CW instruction checks for and handles pending unmasked floating- point exceptions before storing the c ...

  • Intel 253666-024US - page 436

    3-390 Vol. 2A FSTCW/FNSTCW—Store x87 FPU Control Word INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) If the destination is located in a non-writable segment. If a memory oper and effective address is outside the CS , DS, ES, FS, or GS segment limit. If the DS, ES, FS , or GS register is used to access memory and it contains a ...

  • Intel 253666-024US - page 437

    Vol. 2A 3-391 INSTRUCTION SE T REF ERENCE, A-M FSTCW/FNSTCW—Store x87 FPU Control Word #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pend ing x87 FPU exception. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the L ...

  • Intel 253666-024US - page 438

    3-392 Vol. 2A FSTENV/FNSTENV—Stor e x87 FPU Environment INSTRUCTION SE T REF ERENCE, A-M FST ENV /FNST ENV—S tore x87 FPU En vironmen t Descripti on Saves the current FPU oper ating environment at the memory location specified with the destination operand, and then masks al l floating-point exceptions. The FPU oper- ating environment consists o ...

  • Intel 253666-024US - page 439

    Vol. 2A 3-393 INSTRUCTION SE T REF ERENCE, A-M FSTENV/FNSTENV—Store x87 FPU Environment IA-32 Architectur e Compatibility When operating a P e ntium or Intel486 proces sor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an F NS TE NV instruction to be interrupted prior to being executed to handle a pending FPU excep ...

  • Intel 253666-024US - page 440

    3-394 Vol. 2A FSTENV/FNSTENV—Stor e x87 FPU Environment INSTRUCTION SE T REF ERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode E xc eptions #GP(0) If a memory operand effe ctive address is outside the CS, DS , ES, FS, or ...

  • Intel 253666-024US - page 441

    Vol. 2A 3-395 INSTRUCTION SE T REF ERENCE, A-M FSTSW/FNSTSW—Store x87 FPU Status Word FSTSW/FNSTS W—S tore x87 FPU S tatus Wor d Description Stores the current value of the x87 FPU stat us word in the destination location. The destination operand can be either a two-byte memory lo cation or the AX register . The FSTSW instruction checks for and ...

  • Intel 253666-024US - page 442

    3-396 Vol. 2A FSTSW/FNSTSW—Store x87 FPU Status Word INSTRUCTION SE T REF ERENCE, A-M IA-32 Architecture Compat ibility When operating a P entium or Intel486 proc essor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSTSW instruction to be interrupted prior to being executed to handle a pending FPU exception. S ...

  • Intel 253666-024US - page 443

    Vol. 2A 3-397 INSTRUCTION SE T REF ERENCE, A-M FSTSW/FNSTSW—Store x87 FPU Status Word Virtual-8086 Mode Excep tions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault -code ...

  • Intel 253666-024US - page 444

    3-398 Vol. 2A FSUB/FSUBP/FISUB—Subtract INSTRUCTION SE T REF ERENCE, A-M FSUB/FSUBP/FISUB—Subtr act Descripti on Subtracts the source oper and from the dest ination oper and and stores the difference in the destination location. The destination oper and is alwa ys an FPU data register; the source operand can be a register or a memory location. ...

  • Intel 253666-024US - page 445

    Vol. 2A 3-399 INSTRUCTION SE T REF ERENCE, A-M FSUB/FSUBP/FISUB—Subtract The FISUB instructions convert an integer source operand to double extended-preci- sion floating-point format before performing the subtraction. T able 3-43 shows the results obtained when subtracting various classes of numbers from one another , assuming that neither overfl ...

  • Intel 253666-024US - page 446

    3-400 Vol. 2A FSUB/FSUBP/FISUB—Subtract INSTRUCTION SE T REF ERENCE, A-M IF Instruction = FSUBP THEN PopRegisterStack; FI; FPU Flags A ffected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Poin t Ex cept ions #IS Stack underflow occurred. #IA Operand is an SNaN v alue or u ...

  • Intel 253666-024US - page 447

    Vol. 2A 3-401 INSTRUCTION SE T REF ERENCE, A-M FSUB/FSUBP/FISUB—Subtract Virtual-8086 Mode Excep tions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault -code) If a page f ...

  • Intel 253666-024US - page 448

    3-402 Vol. 2A FSUBR/FSUBRP/FISUBR—Reverse Subtract INSTRUCTION SE T REF ERENCE, A-M FSUBR/FSUBRP/FISUBR—Re verse Subtr act Descripti on Subtracts the destination oper and from the source operand and stores the difference in the destination location. The destination oper and is alwa ys an FPU register; the source operand can be a register or a m ...

  • Intel 253666-024US - page 449

    Vol. 2A 3-403 INSTRUCTION SE T REF ERENCE, A-M FSUBR/FSUBRP/FISUBR—Reverse Subtract the register stack being popped. In some assemblers, the mnemonic for this instruc- tion is FSUBR rather than FSUBRP . The FISUBR instructions convert an integer source operand to double extended- precision floating-point format be fore performing the subtraction. ...

  • Intel 253666-024US - page 450

    3-404 Vol. 2A FSUBR/FSUBRP/FISUBR—Reverse Subtract INSTRUCTION SE T REF ERENCE, A-M IF Instruction = FSUBRP THEN PopRegisterStack; FI; FPU Flags A ffected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Poin t Ex cept ions #IS Stack underflow occurred. #IA Operand is an SNaN ...

  • Intel 253666-024US - page 451

    Vol. 2A 3-405 INSTRUCTION SE T REF ERENCE, A-M FSUBR/FSUBRP/FISUBR—Reverse Subtract Virtual-8086 Mode Excep tions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault -code) ...

  • Intel 253666-024US - page 452

    3-406 Vol. 2A FTST—TEST INSTRUCTION SE T REF ERENCE, A-M FTST—T EST Descripti on Compares the value in the ST(0) register with 0.0 and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below). This instruction performs an “unordered co mparison. ” An unordered comparison also checks the ...

  • Intel 253666-024US - page 453

    Vol. 2A 3-407 INSTRUCTION SE T REF ERENCE, A-M FTST—TEST #IA The source oper and is a NaN v alue or is in an unsupported format. #D The source operand is a denormal v alue. Pr otected Mode Ex ceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pend ing x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Ex ceptions ...

  • Intel 253666-024US - page 454

    3-408 Vol. 2A FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values INSTRUCTION SE T REF ERENCE, A-M FUCOM /FUCOMP/FUC OMPP—Unorder ed Compar e Floating Poin t V alues Descripti on Performs an unordered comparison of the contents of register ST(0) and ST(i) and sets condition code flags C0, C2, and C3 in the FPU status word according to ...

  • Intel 253666-024US - page 455

    Vol. 2A 3-409 INSTRUCTION SE T REF ERENCE, A-M FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values The FUCOMP instruction pops the register stack following the comparison operation and the FUCOMPP instruction pops the regist er stack twice following the comparison operation. T o pop the register stack, the processor marks the ST(0) regis ...

  • Intel 253666-024US - page 456

    3-410 Vol. 2A FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values INSTRUCTION SE T REF ERENCE, A-M #IA One or both operan ds are SNaN values or have unsupported formats. Detection of a QNaN value in and of itself does not raise an invalid-operand ex ception. #D One or both operands are denormal values. Pro tected Mode Ex ceptions #NM CR0 ...

  • Intel 253666-024US - page 457

    Vol. 2A 3-411 INSTRUCTION SE T REF ERENCE, A-M FXAM—ExamineModR/M FXAM—ExamineModR/M Description Examines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word to indicate the class of v alue or number in the register (see the table below). . The C1 flag is set to the sign of the value in ST( ...

  • Intel 253666-024US - page 458

    3-412 Vol. 2A FXAM—ExamineModR/M INSTRUCTION SE T REF ERENCE, A-M FPU Flags A ffected C1 Sign of value in ST(0). C0, C2, C3 See T able 3-47. Floating-Poin t Ex cept ions None. Pro tected Mode Ex ceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU ex ception. #UD If the LOCK prefix is used. Real-Addr ess Mode Exc ept ...

  • Intel 253666-024US - page 459

    Vol. 2A 3-413 INSTRUCTION SE T REF ERENCE, A-M FXCH—Exchange Register Contents FX CH—Ex change Regis ter Contents Description Exchanges the contents of registers ST(0) an d ST(i). If no source operand is speci- fied, the contents of ST(0) and ST(1) are exchanged. This instruction provides a simple means of moving values in the FPU register stac ...

  • Intel 253666-024US - page 460

    3-414 Vol. 2A FXCH—Exchange Register Contents INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU ex ception. #UD If the LOCK prefix is used. Real-Addr ess Mode Exc eptions Same exceptions as in protected mode. Virtual-8086 Mode E xc eptions Same exceptions as in p ...

  • Intel 253666-024US - page 461

    Vol. 2A 3-415 INSTRUCTION SE T REF ERENCE, A-M FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR State FXRST OR—Rest ore x87 FPU, MMX , XMM, and MX CSR State Description Reloads the x87 FPU, MMX technology , XMM, and MXCSR registers from the 512-byte memory image specified in the source operan d. This data should have been written to memory previou ...

  • Intel 253666-024US - page 462

    3-416 Vol. 2A FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR State INSTRUCTION SE T REF ERENCE, A-M x87 FPU and SIMD Floating-Poin t Exc eptions None. Pro tected Mode Ex ceptions #GP(0) For an illegal memory oper and effective address in the CS, DS, ES, FS or GS segm ents. If a memory operand is not aligned on a 16-byte boundary , regardless of se ...

  • Intel 253666-024US - page 463

    Vol. 2A 3-417 INSTRUCTION SE T REF ERENCE, A-M FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR State Virtual-8086 Mode Excep tions Same exceptions as in real address mode. #PF(fault -code) For a page fault. #AC For unaligned memory reference. #UD If the LOCK prefix is used. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit ...

  • Intel 253666-024US - page 464

    3-418 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State INSTRUCTION SE T REF ERENCE, A-M FXSA V E—Save x87 FPU, MMX T echnology , SSE, and SSE2 S tate Descripti on Saves the current state of the x87 FPU, MMX technology , XMM, and MXCSR registers to a 512-byte memory location specified in the destination operand. The content layou ...

  • Intel 253666-024US - page 465

    Vol. 2A 3-419 INSTRUCTION SE T REF ERENCE, A-M FXSAVE—Save x87 FPU, MMX Technology, SSE, and SS E2 State The destination operand contains the first by te of the mem ory image, and it must be aligned on a 16-byte boundary . A misaligned desti nation oper and will result in a general-protection (#GP) exception being gener ated (or in some cases, an ...

  • Intel 253666-024US - page 466

    3-420 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State INSTRUCTION SE T REF ERENCE, A-M T able 3-49. Field Definitions Field Definition FC W x8 7 F P U Co nt rol Word ( 1 6 b i ts). See Figure 8-6 in the Int el® 64 and IA-32 Architectur es Softwar e Dev eloper’s Manual, V olume 1 , for the layout of the x87 FPU c ontr ol wor d. ...

  • Intel 253666-024US - page 467

    Vol. 2A 3-421 INSTRUCTION SE T REF ERENCE, A-M FXSAVE—Save x87 FPU, MMX Technology, SSE, and SS E2 State The FXSA VE instruction saves an abridged version of the x87 FPU tag word in the FTW field (unlike the FSAVE instruction, wh ich sa ves the complete tag word). The tag information is saved in physical register order (R0 through R7), rather tha ...

  • Intel 253666-024US - page 468

    3-422 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State INSTRUCTION SE T REF ERENCE, A-M Here, a 1 is saved for any valid, zero , or special tag, and a 0 i s sav ed for any empty tag. The operation of the FXSA VE instruction diff ers from that of the FS A VE instruction, the as follows: • FXSA VE instruction does not check for pe ...

  • Intel 253666-024US - page 469

    Vol. 2A 3-423 INSTRUCTION SE T REF ERENCE, A-M FXSAVE—Save x87 FPU, MMX Technology, SSE, and SS E2 State The J-bit is defined to be the 1-bit binary integer to the left o f the decimal place in the significand. The M-bit is defined to be the mo st significant bit of the fr actional portion of the significand (i.e. , the bit immediat ely to the ri ...

  • Intel 253666-024US - page 470

    3-424 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State INSTRUCTION SE T REF ERENCE, A-M XMM2 192 XMM3 208 XMM4 224 XMM5 240 XMM6 256 XMM7 272 XMM8 288 XMM9 304 XMM10 320 XMM11 336 XMM12 352 XMM13 368 XMM14 384 XMM15 400 Res er ve d 416 Res er ve d 432 Res er ve d 448 Res er ve d 464 Res er ve d 480 Res er ve d 496 T able 3-52. Lay ...

  • Intel 253666-024US - page 471

    Vol. 2A 3-425 INSTRUCTION SE T REF ERENCE, A-M FXSAVE—Save x87 FPU, MMX Technology, SSE, and SS E2 State Operation IF 64-Bit Mode THEN IF REX.W = 1 Res erve d ST 4/M M4 96 Res erve d ST 5/M M5 112 Res erve d ST 6/M M6 128 Res erve d ST 7 /M M7 144 XMM0 160 XMM1 176 XMM2 192 XMM3 208 XMM4 224 XMM5 240 XMM6 256 XMM7 272 XMM8 288 XMM9 304 XMM10 320 ...

  • Intel 253666-024US - page 472

    3-426 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State INSTRUCTION SE T REF ERENCE, A-M THEN DEST ← Save64BitPromote dFxsave(x87 FPU, MM X, XMM7-XMM0, MXCSR); ELSE DEST ← Save64BitDefa ultFxsave(x87 FP U, MMX, XMM7-XMM0, MXCSR); FI; ELSE DEST ← SaveLegacyFxsave (x87 FPU, MMX, XMM7-XMM0, MX CSR); FI; Pro tected Mode Ex ceptio ...

  • Intel 253666-024US - page 473

    Vol. 2A 3-427 INSTRUCTION SE T REF ERENCE, A-M FXSAVE—Save x87 FPU, MMX Technology, SSE, and SS E2 State #UD If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.FXSR[bit 24] = 0. If the LOCK prefix is used. Virtual-8086 Mode Excep tions Same exceptions as in real address mode. #PF(fault -code) For a page fault. #AC For unaligned memory reference. #UD If the L ...

  • Intel 253666-024US - page 474

    3-428 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State INSTRUCTION SE T REF ERENCE, A-M Implementation No te The order in which the processor signals general-protection (#GP) and page-fault (#PF) exceptions when they both occur on an instruction boundary is given in T able 5-2 in the Intel® 64 and IA-32 Architectures Software Dev ...

  • Intel 253666-024US - page 475

    Vol. 2A 3-429 INSTRUCTION SE T REF ERENCE, A-M FXTRACT—Extract Exponent and Significand FXTRA CT—Extr act Exponent and Significand Description Separates the source value in the ST(0) regi ster into its exponent and significand, stores the exponent in ST(0), and pushes the significand onto the register stack. Following this oper ation, the new t ...

  • Intel 253666-024US - page 476

    3-430 Vol. 2A FXTRACT—Extract Exponent and Significand INSTRUCTION SE T REF ERENCE, A-M #IA Source operand is an SNaN value or unsupported format. #Z ST(0) operand is ± 0. #D Source operand is a denormal value. Pro tected Mode Ex ceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU ex ception. #UD If the LOCK prefix ...

  • Intel 253666-024US - page 477

    Vol. 2A 3-431 INSTRUCTION SE T REF ERENCE, A-M FYL2X—Compute y * log2x FYL2X —Compute y ∗ log 2 x Description Computes (ST(1) ∗ log 2 (ST(0))), stores the result in resister ST(1), and pops the FPU register stack. The source operand in ST(0) must be a non-zero positive number . The following table shows the results obtained when taking the ...

  • Intel 253666-024US - page 478

    3-432 Vol. 2A FYL2X—Compute y * log2x INSTRUCTION SE T REF ERENCE, A-M Operat ion ST(1) ← ST(1) ∗ log 2 ST(0); PopRegisterStack; FPU Flags A ffected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Poin t Ex cept ions #IS Stack underflow occurred. #IA Either operan d is a ...

  • Intel 253666-024US - page 479

    Vol. 2A 3-433 INSTRUCTION SE T REF ERENCE, A-M FYL2XP1—Compute y * log2(x +1) FYL2XP1—Compute y ∗ log 2 (x + 1) Description Computes (ST(1) ∗ log 2 (ST(0 ) + 1.0)), stores the resul t in register ST(1), and pops the FPU register stack. The source operand in ST(0) must be in the range: The source operand in ST(1) can range from − ∞ to + ...

  • Intel 253666-024US - page 480

    3-434 Vol. 2A FYL2XP1—Compute y * log2(x +1) INSTRUCTION SE T REF ERENCE, A-M equation is used to calculate the scale factor for a particular logarithm base, where n is the logarithm base desired for th e result of the FYL2XP1 instruction: scale factor ← log n 2 This instruction’s oper ation is the same in non-64-bit modes and 64-bit mode. Op ...

  • Intel 253666-024US - page 481

    Vol. 2A 3-435 INSTRUCTION SE T REF ERENCE, A-M HADDPD—Packed Double-FP Horizontal Add HADDPD—Pack ed Double-FP Horizon tal Add Description Adds the double-precision floating-point values in the high and low quadwords of the destination operand and stores the result in the low quadword of the destination operand. Adds the double-precision floati ...

  • Intel 253666-024US - page 482

    3-436 Vol. 2A HADDPD—Packed Double-FP Horizontal Add INSTRUCTION SE T REF ERENCE, A-M Operat ion xmm1[63:0] = xmm1[63:0] + xmm1[1 27:64]; xmm1[127:64] = xmm2 /m128[63:0] + xmm2/m128[127:64]; Intel C/C + + Compiler Intrinsic Equivalent HADDPD __m128d _mm_hadd_pd (__m128d a, __m128d b) Exc e p tions When the source operand is a memory oper and, the ...

  • Intel 253666-024US - page 483

    Vol. 2A 3-437 INSTRUCTION SE T REF ERENCE, A-M HADDPD—Packed Double-FP Horizontal Add #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric excep- tion (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID. 01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. Virtual 8086 M ode Ex ceptions GP(0) If an y part of th ...

  • Intel 253666-024US - page 484

    3-438 Vol. 2A HADDPD—Packed Double-FP Horizontal Add INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID feature flag SSE3 is 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 485

    Vol. 2A 3-439 INSTRUCTION SE T REF ERENCE, A-M HADDPS—Packed Single-FP Hor izontal Add HADDPS—Pack ed Single-FP Horizon tal Add Description Adds the single-precision floating-point values in the first and second dwords of the destination operand and stores the result in the first dword of the destina tion operand. Adds single-precision floating ...

  • Intel 253666-024US - page 486

    3-440 Vol. 2A HADDPS—Packe d Single-FP Horizontal Add INSTRUCTION SE T REF ERENCE, A-M In 64-bit mode, use of the REX.R prefix perm its this instruction to access additional registers (XMM8- XMM15). Operat ion xmm1[31:0] = xmm1[31:0] + xmm1[6 3:32]; xmm1[63:32] = xmm1[95:64 ] + xmm1[127:96]; xmm1[95:64] = xmm2/m128[31:0] + xmm2/m 128[63:32]; xmm1 ...

  • Intel 253666-024US - page 487

    Vol. 2A 3-441 INSTRUCTION SE T REF ERENCE, A-M HADDPS—Packed Single-FP Hor izontal Add Real Addr ess Mode Exc eptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked St ...

  • Intel 253666-024US - page 488

    3-442 Vol. 2A HADDPS—Packe d Single-FP Horizontal Add INSTRUCTION SE T REF ERENCE, A-M #PF(fault-code) F or a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFX ...

  • Intel 253666-024US - page 489

    Vol. 2A 3-443 INSTRUCTION SE T REF ERENCE, A-M HLT—Ha lt HL T—Halt Description Stops instruction execution and places the proce ssor in a HAL T state. An enabled interrupt (including NMI and SMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume exec ution. If an interrupt (including NMI) is used to resum ...

  • Intel 253666-024US - page 490

    3-444 Vol. 2A HLT—Halt INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 491

    Vol. 2A 3-445 INSTRUCTION SE T REF ERENCE, A-M HSUBPD—Packed Double-FP Horizontal Subtract HSUBPD—Pack ed Double-FP Horizont al Subtr act Description The HSUBPD instruction subtracts horizonta lly the packed DP FP numbers of both operands. Subtracts the double-precision floating-point v alue in the high quadword of the desti- nation operand fro ...

  • Intel 253666-024US - page 492

    3-446 Vol. 2A HSUBPD—Packed Double-FP Horizontal Su btract INSTRUCTION SE T REF ERENCE, A-M Operat ion xmm1[63:0] = xmm1[63:0] − xmm1[127:64]; xmm1[127:64] = xmm2/m128[63:0] − xmm2/m128[12 7:64]; Intel C/C + + Compiler Intrinsic Equivalent HSUBPD __m1 28d _mm_hsub_pd(__m1 28d a, __m128d b) Exc e p tions When the source operand is a memory ope ...

  • Intel 253666-024US - page 493

    Vol. 2A 3-447 INSTRUCTION SE T REF ERENCE, A-M HSUBPD—Packed Double-FP Horizontal Subtract #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric excep- tion (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID. 01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. Virtual 8086 M ode Ex ceptions GP(0) If any part o ...

  • Intel 253666-024US - page 494

    3-448 Vol. 2A HSUBPD—Packed Double-FP Horizontal Su btract INSTRUCTION SE T REF ERENCE, A-M If CPUID feature flag SSE3 is 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 495

    Vol. 2A 3-449 INSTRUCTION SE T REF ERENCE, A-M HSUBPS—Packed Single-FP Horiz ontal Subtract HSUBPS—Pack ed Single-FP Horizon tal Subtract Description Subtracts the single-precision floating-point v alue in th e second d word of the desti- nation operand from th e first dword of the destination operand and stores the result in the first dword of ...

  • Intel 253666-024US - page 496

    3-450 Vol. 2A HSUBPS—Packed Single-FP Horizontal Su btract INSTRUCTION SE T REF ERENCE, A-M In 64-bit mode, use of the REX.R prefix perm its this instruction to access additional registers (XMM8- XMM15). Operat ion xmm1[31:0] = xmm1[31:0] − xmm1[63:32]; xmm1[63:32] = xmm1[95:64 ] − xmm1[127:9 6]; xmm1[95:64] = xmm2/m128 [31:0] − xmm2/m128[6 ...

  • Intel 253666-024US - page 497

    Vol. 2A 3-451 INSTRUCTION SE T REF ERENCE, A-M HSUBPS—Packed Single-FP Horiz ontal Subtract Numeric Ex ceptions Overflow , Underflow , Inv alid, Precision, Denormal. Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary , re ...

  • Intel 253666-024US - page 498

    3-452 Vol. 2A HSUBPS—Packed Single-FP Horizontal Su btract INSTRUCTION SE T REF ERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM For an unmask ed Streaming SIMD Extensions numeric excep- tion (CR4.OSXMMEXCPT[bit 10] = 1). #UD I f CR0.EM[bit 2] = 1. For an unmask ed Streaming SIMD Extensions numeric excep- tion (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR ...

  • Intel 253666-024US - page 499

    Vol. 2A 3-453 INSTRUCTION SE T REF ERENCE, A-M IDIV—Signed Divide IDIV—Signed Divide Description Divides the (signed) value in the AX, DX:A X, or EDX:EAX (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:A X, or EDX:EAX regis- ters. The source operand can be a general-purpose register or a memory location. T ...

  • Intel 253666-024US - page 500

    3-454 Vol. 2A IDIV—Signed Divide INSTRUCTION SE T REF ERENCE, A-M Operat ion IF SRC = 0 THEN #DE; (* Divide error *) FI; IF OperandS ize = 8 (* Word/byte opera tion *) THEN temp ← AX / SRC; (* Signed division *) IF (temp > 7FH) or (temp < 80H) (* If a positive result is greater than 7F H or a negative result is less than 80H *) THEN #DE; ...

  • Intel 253666-024US - page 501

    Vol. 2A 3-455 INSTRUCTION SE T REF ERENCE, A-M IDIV—Signed Divide THEN #DE; (* Divide error *) ELSE EAX ← temp; EDX ← EDXE:AX SignedModulus SRC; FI; FI; ELSE IF OperandSize = 64 (* Dou blequadword/quadword operation *) temp ← RDX:RAX / SRC; (* Signed division *) IF (temp > 7FFFFFFFFFFFH) or (tem p < 8000000000000000H) (* If a positive ...

  • Intel 253666-024US - page 502

    3-456 Vol. 2A IDIV—Signed Divide INSTRUCTION SE T REF ERENCE, A-M #GP If a memory operand effectiv e address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used. Virtual-8086 Mode E xc eptions #DE If the source operand (divisor) is 0. The sig ...

  • Intel 253666-024US - page 503

    Vol. 2A 3-457 INSTRUCTION SE T REF ERENCE, A-M IMUL—Signed Multiply IMUL —Signed Multiply Opcode Instruction 64-Bit Mode Compat/ Leg Mode Descript ion F6 /5 IMUL r/m8* Va l i d Va l id A X ← AL ∗ r/m byte. F7 /5 IMUL r/m16 Va l i d Val i d DX : A X ← AX ∗ r/m word. F7 /5 IMUL r/m32 Va l i d Val i d E DX : E A X ← EAX ∗ r/m 32. REX.W ...

  • Intel 253666-024US - page 504

    3-458 Vol. 2A IMUL—Signed Multiply INSTRUCTION SE T REF ERENCE, A-M Descripti on Performs a signed multiplication of two op er ands. This instruction has three forms, depending on the number of operands. • One-operand form — This form is identical to that used by the MUL instruction. Here, the source operand (in a general-purpo se register or ...

  • Intel 253666-024US - page 505

    Vol. 2A 3-459 INSTRUCTION SE T REF ERENCE, A-M IMUL—Signed Multiply signed or unsigned. The CF and OF flags, ho wever , cannot be used to determine if the upper half of the result is non-zero. In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional regi sters (R8-R1 5). Use of th ...

  • Intel 253666-024US - page 506

    3-460 Vol. 2A IMUL—Signed Multiply INSTRUCTION SE T REF ERENCE, A-M ELSE IF (NumberO fOperands = 2) THEN temp ← DEST ∗ SRC (* Signed multipli cation; temp is double DEST size *) DEST ← DEST ∗ SRC (* Signed multiplication *) IF temp ≠ DEST THEN CF ← 1; OF ← 1; ELSE CF ← 0; OF ← 0; FI; ELSE (* Number OfOperands = 3 *) DEST ← SRC ...

  • Intel 253666-024US - page 507

    Vol. 2A 3-461 INSTRUCTION SE T REF ERENCE, A-M IMUL—Signed Multiply #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used. Virtual-8086 Mode Excep tions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address ...

  • Intel 253666-024US - page 508

    3-462 Vol. 2A IN—Input from Port INSTRUCTION SE T REF ERENCE, A-M IN—Input fr om Port Descripti on Copies the value from the I/O port spec ified with the second operand (source operand) to the destination operand (first oper and). The source operand can be a byte-immediate or the DX register; the dest ination operand can be register AL, AX, or ...

  • Intel 253666-024US - page 509

    Vol. 2A 3-463 INSTRUCTION SE T REF ERENCE, A-M IN—Input from Port DEST ← SRC; (* Read from selected I/O port *) FI; ELSE (Real Mode or Pr otected Mode with CPL ≤ IOPL *) DEST ← SRC; (* Read from selected I/O port *) FI; Flags A ffected None. Pr otected Mode Ex ceptions #GP(0) If the CPL is greater than (has less privilege) the I/O privilege ...

  • Intel 253666-024US - page 510

    3-464 Vol. 2A INC—Increment by 1 INSTRUCTION SE T REF ERENCE, A-M INC—Incremen t by 1 Descripti on Adds 1 to the destination op er and, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without distur bing the CF flag. (Use a ADD instru ...

  • Intel 253666-024US - page 511

    Vol. 2A 3-465 INSTRUCTION SE T REF ERENCE, A-M INC—Increment by 1 Pr otected Mode Ex ceptions #GP(0) If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS , ES, FS, or GS segment limit. If the DS, ES, FS , or GS register is used to access memory and it contains a NULLsegment s ...

  • Intel 253666-024US - page 512

    3-466 Vol. 2A INC—Increment by 1 INSTRUCTION SE T REF ERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory operand. ...

  • Intel 253666-024US - page 513

    Vol. 2A 3-467 INSTRUCTION SE T REF ERENCE, A-M INS/INSB/INSW/INSD—Input from Port to String INS/INSB/INSW/INSD—Input from P ort to S tring Description Copies the data from the I/O port spec ified with the source operand (second operand) to the destination oper and (first operand). The source operand is an I/O port address (from 0 t o 65,535) th ...

  • Intel 253666-024US - page 514

    3-468 Vol. 2A INS/INSB/INSW/INSD—Input from Port to String INSTRUCTION SE T REF ERENCE, A-M destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct locati on . The location is always specified by the ES:(E)DI registers, which must be loaded correctly b ...

  • Intel 253666-024US - page 515

    Vol. 2A 3-469 INSTRUCTION SE T REF ERENCE, A-M INS/INSB/INSW/INSD—Input from Port to String IF (Byte transfer) THEN IF DF = 0 THEN (E)DI ← (E)DI + 1; ELSE (E)DI ← (E)DI – 1; FI; ELSE IF (Word transfer) THEN IF DF = 0 THEN (E)DI ← (E)DI + 2; ELSE (E)DI ← (E)DI – 2; FI; ELSE (* Doubleword tr ansfer *) THEN IF DF = 0 THEN (E)DI ← (E)DI ...

  • Intel 253666-024US - page 516

    3-470 Vol. 2A INS/INSB/INSW/INSD—Input from Port to String INSTRUCTION SE T REF ERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Addr ess Mode Exc eptions #GP If a memory operand effectiv e address is outside the CS, DS, ES, F ...

  • Intel 253666-024US - page 517

    Vol. 2A 3-471 INSTRUCTION SE T REF ERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure IN T n /INT O/INT 3—Call t o Interrup t Proc edure Description The INT n instruction generates a call to the in terrupt or exception handler specified with the destination operand (see the section titled “Interrupts and Exceptions” in Chapter 6 of th ...

  • Intel 253666-024US - page 518

    3-472 Vol. 2A INT n/INTO/INT 3—Call to Interrupt Procedure INSTRUCTION SE T REF ERENCE, A-M with the IRET instruction, which pops the EFLAGS information and return address from the stack. The interrupt vector number specifies an interrupt descriptor in the interrupt descriptor table (IDT); that is, it provides index into the ID T . The selected i ...

  • Intel 253666-024US - page 519

    Vol. 2A 3-473 INSTRUCTION SE T REF ERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure When the processor is executing in virt ual-8086 mode, the IOPL determines the action of the INT n instruction. If the IOPL is less than 3, the processor generates a #GP(selector) exception; if the IOPL is 3, the processor executes a protected mode interru ...

  • Intel 253666-024US - page 520

    3-474 Vol. 2A INT n/INTO/INT 3—Call to Interrupt Procedure INSTRUCTION SE T REF ERENCE, A-M CS ← IDT(Descriptor (vector _number ∗ 4), selector)); EIP ← IDT(Descriptor (vector_number ∗ 4), offset)); (* 16 bit offset AND 0000FF FFH *) END; PROTECTED-MODE: IF ((vector_number ∗ 8) + 7) is not within IDT limits or selected IDT descriptor is ...

  • Intel 253666-024US - page 521

    Vol. 2A 3-475 INSTRUCTION SE T REF ERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure or index not w ithin GDT limits THEN #GP(TSS s elector); FI; Access TSS descriptor in GDT; IF TSS descriptor specifies that the TSS is busy (low-o rder 5 bits set to 00001) THEN #GP(TSS s elector); FI; IF TSS not presen t THEN #NP(TSS selector); FI; SWITCH ...

  • Intel 253666-024US - page 522

    3-476 Vol. 2A INT n/INTO/INT 3—Call to Interrupt Procedure INSTRUCTION SE T REF ERENCE, A-M IF VM = 1 THEN #GP(new code segment selector); FI; IF code segment is confor ming or code se gment DPL = CPL THEN GOTO INTRA-PRIVILEGE-LEVEL-INTERRUPT; ELSE #GP(CodeSegmentS elector + EXT); (* PE = 1, interrupt or trap gate, nonconformin g code segment, DP ...

  • Intel 253666-024US - page 523

    Vol. 2A 3-477 INSTRUCTION SE T REF ERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure or stack segment does not indica te writable data segment THEN #TS(SS sele ctor + EXT); FI; IF stack segment not present THEN #SS(SS selector + EX T); FI; FI IF 32-bit gate THEN IF new stack does not have room for 24 bytes (error code pushed) or 20 bytes ( ...

  • Intel 253666-024US - page 524

    3-478 Vol. 2A INT n/INTO/INT 3—Call to Interrupt Procedure INSTRUCTION SE T REF ERENCE, A-M FI; IF 32-bit gate THEN Push(far pointer to old stack); (* Old SS and ESP, 3 words padded to 4 *) Push(EFLAGS); Push(far pointer to return instru ction); (* Old CS and EIP, 3 words padded to 4 *) Push(ErrorCode); (* If needed, 4 bytes *) ELSE IF 16-bit gat ...

  • Intel 253666-024US - page 525

    Vol. 2A 3-479 INSTRUCTION SE T REF ERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure NewESP ← stack address; ELSE (* TSS is 16-bit *) TSSstackAddress ← (n ew code segment DPL ∗ 4) + 2; IF (TSSstackAddress + 4) > TSS limit THEN #TS(current TSS selector); FI; NewESP ← TSSstackAddress; NewSS ← TSSstackAddress + 2; FI; IF segment ...

  • Intel 253666-024US - page 526

    3-480 Vol. 2A INT n/INTO/INT 3—Call to Interrupt Procedure INSTRUCTION SE T REF ERENCE, A-M TempSS ← SS; TempESP ← ESP; SS:ESP ← TS S(SS0:ESP0); (* Change to level 0 stack segment *) (* Following pushes are 16 b its for 16-bit gate and 32 bits for 32-bit gates; Segment selector pushe s in 32-bit mode are pa dded to two words *) Push(GS); Pu ...

  • Intel 253666-024US - page 527

    Vol. 2A 3-481 INSTRUCTION SE T REF ERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure IF instruction pointer no t within code segment limit THEN #GP(0); FI; IF 32-bit gate THEN Push (EFLAG S); Push (far pointer to retu rn instru ction); (* 3 words padd ed to 4 *) CS:EIP ← Gate (CS:EIP); (* Segment descri ptor informatio n also loaded *) P ...

  • Intel 253666-024US - page 528

    3-482 Vol. 2A INT n/INTO/INT 3—Call to Interrupt Procedure INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) If the instruction pointer in the IDT or in the interrupt-, tr ap-, or task gate is beyond the code segment limits. #GP(selector) If the segment selector in th e interrupt-, tr ap-, or task gate is NULL. If an interrupt-, ...

  • Intel 253666-024US - page 529

    Vol. 2A 3-483 INSTRUCTION SE T REF ERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure Real-Address Mode Ex ceptions #GP If a memory operand effective address is outside the CS, DS , ES, FS, or GS segment limit. If the interrupt vector number is outside the IDT limits. #SS If stack limit violation on push. If pushing the return address, flag ...

  • Intel 253666-024US - page 530

    3-484 Vol. 2A INT n/INTO/INT 3—Call to Interrupt Procedure INSTRUCTION SE T REF ERENCE, A-M If the stack segment for the TS S is not a writable data segment. If segment-selector index for stack segment is outside descriptor table limit s. #PF(fault-code) If a page fault occurs. #BP If the INT 3 instruction is executed. #OF If the INTO instruction ...

  • Intel 253666-024US - page 531

    Vol. 2A 3-485 INSTRUCTION SE T REF ERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure #TS(selector) If an attempt to load RSP from the TSS causes an access to non- canonical space. If the RSP from the TSS is outside descriptor ta ble limits. #PF(fault -code) If a page fault occurs. #UD If the LOCK prefix is used. ...

  • Intel 253666-024US - page 532

    3-486 Vol. 2A INVD—Invalidate Internal Caches INSTRUCTION SE T REF ERENCE, A-M INVD —Inv alidate In ternal Caches Descripti on Inv alidates (flushes) the processor’s internal caches and issues a special-function bus cycle that directs external caches to also flush themselves. Data held in internal caches is not written back to main memory . A ...

  • Intel 253666-024US - page 533

    Vol. 2A 3-487 INSTRUCTION SE T REF ERENCE, A-M INVD—Invalidate Internal Caches Pr otected Mode Ex ceptions #GP(0) If the current privilege level is not 0. #UD If the LOCK prefix is used. Real- Address Mod e Exc eptions #UD If the LOCK prefix is used. Virtual-8086 Mo de Ex ceptions #GP(0) The INVD instruction cannot b e executed in virtual-8086 mo ...

  • Intel 253666-024US - page 534

    3-488 Vol. 2A INVLPG—Invalidate TLB Entry INSTRUCTION SE T REF ERENCE, A-M INVLPG—In validate TLB En try Descripti on Invalidates (flushes) the tr anslation lookas ide buffer (TLB) entry specified with the source operand. The source operand is a memory address. The processor determines the page that contains that address and flushes the TLB ent ...

  • Intel 253666-024US - page 535

    Vol. 2A 3-489 INSTRUCTION SE T REF ERENCE, A-M INVLPG—Invalidate TLB Entry Real-Address Mode Ex ceptions #UD Operand is a register . If the LOCK prefix is used. Virtual-8086 Mode Excep tions #GP(0) The INVLPG instruction cannot be executed at the virtual-8086 mode. 64-Bit Mode Exc eptions #GP(0) If the current privilege level is not 0. #UD Operan ...

  • Intel 253666-024US - page 536

    3-490 Vol. 2A IRET/IRETD—Interrupt Return INSTRUCTION SE T REF ERENCE, A-M IR ET /IR ETD—Interrupt Re turn Descripti on Returns pro gram control from an exception or interrupt handler to a program or procedure that was interrupted by an exception, an external interrupt, or a software- generated i nterrupt. These instructi ons are also used to p ...

  • Intel 253666-024US - page 537

    Vol. 2A 3-491 INSTRUCTION SE T REF ERENCE, A-M IRET/IRETD—Interrupt Return As with a real-address mode interrupt retu rn, the IRET instruction pops the return instruction pointer , return code segment selector , and EFLAGS image from the stack to the EIP , CS, and EFLAGS registers, respectively , and then resumes execution of the interrupted prog ...

  • Intel 253666-024US - page 538

    3-492 Vol. 2A IRET/IRETD—Interrupt Return INSTRUCTION SE T REF ERENCE, A-M EFLAGS ← (tempEFLAGS AND 257FD5H) OR (EFLAGS AND 1A0000H); ELSE (* OperandSize = 16 *) IF top 6 bytes of stack are not within stack limits THEN #SS; FI; EIP ← Pop(); (* 16-bit pop; clear upper 16 bi ts *) CS ← Pop(); (* 16-bit pop *) EFLAGS[15:0] ← Pop(); FI; END; ...

  • Intel 253666-024US - page 539

    Vol. 2A 3-493 INSTRUCTION SE T REF ERENCE, A-M IRET/IRETD—Interrupt Return ELSE IF OperandSize = 32 THEN IF top 12 bytes of stack not within stack limits THEN #SS(0); FI; tempEIP ← Pop(); tempCS ← Pop(); tempEFLAGS ← Pop(); ELSE IF Op erandSize = 16 THEN IF top 6 bytes of stack ar e not withi n stack limits THEN #SS(0); FI; tempEIP ← Pop( ...

  • Intel 253666-024US - page 540

    3-494 Vol. 2A IRET/IRETD—Interrupt Return INSTRUCTION SE T REF ERENCE, A-M THEN #GP(0) ; FI; EIP ← Pop(); EIP ← EIP AND 0000FFFFH; CS ← Pop(); (* 16-bit pop *) EFLAGS[15:0] ← Pop(); (* IOPL in EFLAGS not modified by pop *) FI; ELSE #GP(0); (* Trap to virtual-8086 monito r: PE = 1, VM = 1, IOPL < 3 *) FI; END; RETURN-T O-VIRTUAL-808 6-M ...

  • Intel 253666-024US - page 541

    Vol. 2A 3-495 INSTRUCTION SE T REF ERENCE, A-M IRET/IRETD—Interrupt Return IF EIP is not within code segment limit THEN #GP(0); FI; END; PROTECTED-MODE-RETUR N: (* PE = 1 *) IF return code segm ent selector is NULL THEN GP(0); FI; IF return code segment selector addresses descriptor beyond descriptor table limit THEN GP(selec tor); FI; Read segme ...

  • Intel 253666-024US - page 542

    3-496 Vol. 2A IRET/IRETD—Interrupt Return INSTRUCTION SE T REF ERENCE, A-M EFLAGS(IOPL) ← tempEFLAGS; IF OperandSiz e = 32 or OperandSize = 64 THEN EFLAGS (VIF, VIP) ← tempEFLAGS; FI; FI; END; RETURN-TO-OUTER-PRIVIL EGE-LEVEL: IF OperandSize = 32 THEN IF top 8 bytes on stack are not within limits THEN #SS(0); FI ; ELSE (* Operan dSize = 16 *) ...

  • Intel 253666-024US - page 543

    Vol. 2A 3-497 INSTRUCTION SE T REF ERENCE, A-M IRET/IRETD—Interrupt Return IF CPL = 0 THEN EFLAGS(IOPL) ← tempEFLAGS; IF OperandS ize = 32 THEN EFLAGS(VM, VIF, VIP) ← tempEFLAGS; FI; IF OperandS ize = 64 THEN EFLAGS(VIF, VIP) ← tempEFLAGS; F I; FI; CPL ← RPL of the return co de segment selector; FOR each of segment re gister (ES, FS, GS, ...

  • Intel 253666-024US - page 544

    3-498 Vol. 2A IRET/IRETD—Interrupt Return INSTRUCTION SE T REF ERENCE, A-M Flags A ffected All the flags and fields in the EFLAGS regi ster are potentially modified, depending on the mode of operation of the processor . If performing a return from a nested task to a previous task, the EFLAGS register will be modified according to the EFLAGS image ...

  • Intel 253666-024US - page 545

    Vol. 2A 3-499 INSTRUCTION SE T REF ERENCE, A-M IRET/IRETD—Interrupt Return Virtual-8086 Mode Excep tions #GP(0) If the return instruction pointer is not within the return code segment limit. IF IOPL not equal to 3. #PF(fault -code) If a page fault occurs. #SS(0) If the top bytes of stack are not within stack limits. #AC(0) If an unaligned memory ...

  • Intel 253666-024US - page 546

    3-500 Vol. 2A IRET/IRETD—Interrupt Return INSTRUCTION SE T REF ERENCE, A-M If the stack segment selector RPL is not equal to the RPL of the return code segment selector . #SS(0) If an attempt to pop a value off the stack violates the SS limit. If an attempt to pop a value off the stack causes a non-canonical address to be referenced. #NP(selector ...

  • Intel 253666-024US - page 547

    Vol. 2A 3-501 INSTRUCTION SE T REF ERENCE, A-M Jcc—Jump if Condition Is Met J cc —Jump if Condition Is Met Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 77 cb JA rel 8 Valid V alid Jump sh ort if abov e (CF=0 a nd ZF=0). 73 cb JAE re l8 Va lid Valid Jump short if above or equal (CF=0). 72 cb JB rel 8 V alid V alid Jump short if be ...

  • Intel 253666-024US - page 548

    3-502 Vol. 2A Jcc—Jump if Condition Is Met INSTRUCTION SE T REF ERENCE, A-M 75 cb JNZ rel 8 V alid V alid Jump short if not z ero (ZF=0). 70 cb JO rel 8 Val id Vali d J um p sh or t if over flow (O F=1 ). 7A cb JP re l8 Va lid Valid Jump short if parity (PF=1). 7A cb JPE rel 8 V alid Valid Jump short if par ity e ven (PF=1). 7B cb JPO rel 8 V ali ...

  • Intel 253666-024US - page 549

    Vol. 2A 3-503 INSTRUCTION SE T REF ERENCE, A-M Jcc—Jump if Condition Is Met 0F 8C cw JL rel 16 N.S. V alid Jump near if less (SF ≠ OF). No t supported in 64-bit mode . 0F 8C cd JL rel 32 Va lid Va lid Jump near if les s (SF ≠ OF). 0F 8E cw JLE rel1 6 N.S. Valid Jump near if less or equa l (ZF=1 or SF ≠ OF). Not supported in 64-bit mode. 0F ...

  • Intel 253666-024US - page 550

    3-504 Vol. 2A Jcc—Jump if Condition Is Met INSTRUCTION SE T REF ERENCE, A-M 0F 8C cd JNGE rel 32 Valid V alid Jump near if not gr eater or equal (SF ≠ OF). 0F 8D cw JNL rel 16 N .S. Valid Jum p near if not less (SF=OF). Not supported i n 64-bit mode. 0F 8D cd JNL rel 32 Valid V alid Jump near if not less (SF=OF). 0F 8F cw JNLE rel 16 N.S. Valid ...

  • Intel 253666-024US - page 551

    Vol. 2A 3-505 INSTRUCTION SE T REF ERENCE, A-M Jcc—Jump if Condition Is Met Description Checks the state of one or more of the status flags in the EFLAGS register (CF , OF , PF , SF , and ZF) and, if the flags are in the spec ified state (condition), performs a jump to the target instruction specified by the destination operand. A condition code ...

  • Intel 253666-024US - page 552

    3-506 Vol. 2A Jcc—Jump if Condition Is Met INSTRUCTION SE T REF ERENCE, A-M checked is determined by the address-size attribute. These instructions are useful when used at the beginning of a loop that terminates with a conditional loop instruc- tion (such as LOOPNE). They can be used to prevent an instruction sequence from entering a loop when RC ...

  • Intel 253666-024US - page 553

    Vol. 2A 3-507 INSTRUCTION SE T REF ERENCE, A-M Jcc—Jump if Condition Is Met Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Ex cep tions #GP(0) If the memory address is in a non-canonical form. #UD If the LOCK prefix is used. ...

  • Intel 253666-024US - page 554

    3-508 Vol. 2A JMP—Jump INSTRUCTION SE T REF ERENCE, A-M JMP—Jump Descripti on T r ansfers progr am control to a different point in the instruction stream without recording return information. The destinat ion (target) oper and specifies the address of the instruction being jumped to. This operand can be an immediate value, a general-purpose reg ...

  • Intel 253666-024US - page 555

    Vol. 2A 3-509 INSTRUCTION SE T REF ERENCE, A-M JMP—Jump • Short jump—A near jump where the jump range is limited to –128 to + 127 from the current EIP v alue. • F ar jump— A jump to an instruction located in a different segment than the current code segment but at the same privilege le vel, sometimes referred to as an intersegment jump. ...

  • Intel 253666-024US - page 556

    3-510 Vol. 2A JMP—Jump INSTRUCTION SE T REF ERENCE, A-M • A task switch. (The JMP instruction cannot be used to perform inter-privilege-level far jumps.) In protected mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GD T or LDT . The descriptor type (code segment, call ga ...

  • Intel 253666-024US - page 557

    Vol. 2A 3-511 INSTRUCTION SE T REF ERENCE, A-M JMP—Jump and save the previous task link information, allowing a return to the calling task with an IRET instruction. In 64-Bit Mode — The instruction’ s operation size is fixed at 64 bits. If a selector points to a gate, then RIP equals the 64-bit displacement taken from gate; else RIP equals th ...

  • Intel 253666-024US - page 558

    3-512 Vol. 2A JMP—Jump INSTRUCTION SE T REF ERENCE, A-M FI; IF far jump and (PE = 0 or (PE = 1 AND VM = 1)) (* Real-address or virtual-8086 mode *) THEN tempEIP ← DEST(Offset); (* DEST is ptr16:32 or [ m16:32 ] *) IF tempEIP is beyond code segment li mit THEN #GP(0) ; FI; CS ← DEST(segment select or); (* DEST is ptr1 6:32 or [ m16:32 ] *) IF ...

  • Intel 253666-024US - page 559

    Vol. 2A 3-513 INSTRUCTION SE T REF ERENCE, A-M JMP—Jump THEN GP(new code se gment selector); FI; IF DPL > CPL THEN #GP(segment selector); FI; IF segment not presen t THEN #NP(segment selecto r); FI; tempEIP ← DEST(Offset); IF OperandS ize = 16 THEN tempEIP ← tempEIP AND 0000FFFFH; FI; IF (IA32_EFER.LMA = 0 or target mode = Compatibilit y m ...

  • Intel 253666-024US - page 560

    3-514 Vol. 2A JMP—Jump INSTRUCTION SE T REF ERENCE, A-M THEN #GP(0) ; FI; IF call gate code-segment selector index outside descriptor table li mits THEN #GP(code segment selector); FI; Read code segment descri ptor; IF code-segment segme nt descriptor does not indicate a cod e segment or code-segment segmen t descriptor is conforming and DPL > ...

  • Intel 253666-024US - page 561

    Vol. 2A 3-515 INSTRUCTION SE T REF ERENCE, A-M JMP—Jump or TSS DPL < TSS segment-selector RPL or TSS descri ptor indicates TSS not available THEN #GP(TSS s elector); FI; IF TSS is not prese nt THEN #NP(TSS selector); FI; SWITCH-TASKS to TSS ; IF EIP not within code segment limit THEN #GP(0); FI; END; Flags A ffected All flags are affected if a ...

  • Intel 253666-024US - page 562

    3-516 Vol. 2A JMP—Jump INSTRUCTION SE T REF ERENCE, A-M If the segment selector for a TSS has its local/global bit set for local. If a TSS segment descriptor specifies that the TSS is busy or not available. #SS(0) If a memory oper and effective add ress is outside the S S segment limit. #NP (selector) I f the code segment being accessed is not pr ...

  • Intel 253666-024US - page 563

    Vol. 2A 3-517 INSTRUCTION SE T REF ERENCE, A-M JMP—Jump If target offset in destination operand is non-canonical. If target offset in destination operand is beyond the new code segment limit. If the segment selector in the destination oper and is NULL. If the code segment selector in the 64-bit gate is NULL. #GP(selector) If the code segment or 6 ...

  • Intel 253666-024US - page 564

    3-518 Vol. 2A LAHF—Load Status Flags into AH Register INSTRUCTION SE T REF ERENCE, A-M LAHF—Load S tatus Flags into AH R egister Descripti on This instruction executes as described above in compatibilit y mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1. Operat ion IF 64-Bit Mode THEN IF CPUID.80 ...

  • Intel 253666-024US - page 565

    Vol. 2A 3-519 INSTRUCTION SE T REF ERENCE, A-M LAHF—Load Status Flags into AH Register 64-Bit Mode Ex cep tions #UD If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 566

    3-520 Vol. 2A LAR—Load Access Rights Byte INSTRUCTION SE T REF ERENCE, A-M LAR—Load Acc ess Rights Byte Descripti on Loads the access rights from the segment de scriptor specified by the second operand (source operand) into the first operand (destination oper and) and sets the ZF flag in the flag register . The source operand (which can be a re ...

  • Intel 253666-024US - page 567

    Vol. 2A 3-521 INSTRUCTION SE T REF ERENCE, A-M LAR—Load Access Rights Byte • If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to th e DPL of the segment selector). If the segment descriptor cannot ...

  • Intel 253666-024US - page 568

    3-522 Vol. 2A LAR—Load Access Rights Byte INSTRUCTION SE T REF ERENCE, A-M ZF = 0; ELSE IF SegmentDescriptor(Type) ≠ conforming code segment and (CPL > DPL) or (RPL > DPL) or segment type is not valid for instructi on THEN ZF ← 0 ELSE TEMP ← Read segment descriptor ; IF OperandSize = 64 THEN DEST ← (ACCESSRIGHTWORD(TEMP ) AND 000000 ...

  • Intel 253666-024US - page 569

    Vol. 2A 3-523 INSTRUCTION SE T REF ERENCE, A-M LAR—Load Access Rights Byte Virtual-8086 Mo de Ex ceptions #UD The LAR instruction cannot be executed in virtual-8086 mode. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If the memory operand effective address referencing the SS segment is in a no ...

  • Intel 253666-024US - page 570

    3-524 Vol. 2A LDDQU—Load Unaligned Integer 128 Bits INSTRUCTION SE T REF ERENCE, A-M LDDQU—Load Unaligned In teger 128 Bits Descripti on The instruction is functionally similar to MOVDQU xmm, m128 for loading from memory . That is: 16 bytes of data starting at an address specified by the source memory operand (second operand) are fetc hed from ...

  • Intel 253666-024US - page 571

    Vol. 2A 3-525 INSTRUCTION SE T REF ERENCE, A-M LDDQU—Load Unaligned Integer 128 Bits Intel C/C + + Compiler Intrinsi c Equivalent LDDQU __m128i _mm_lddqu_si128(__m128i const *p ) Numeric Ex ceptions None. Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal ...

  • Intel 253666-024US - page 572

    3-526 Vol. 2A LDDQU—Load Unaligned Integer 128 Bits INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #NM If CR0.TS[bit 3] = 1. # ...

  • Intel 253666-024US - page 573

    Vol. 2A 3-527 INSTRUCTION SE T REF ERENCE, A-M LDMXCSR—Load MXCSR Register LDMX CSR—Load MX CSR Register Description Loads the source operand into the MXCSR control/status register . The source operand is a 32-bit memory location. See “MXCSR Control and Status Register” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Devel ...

  • Intel 253666-024US - page 574

    3-528 Vol. 2A LDMXCSR—Load MXCSR Register INSTRUCTION SE T REF ERENCE, A-M If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real Add ress Mode Ex cep tions GP(0) If any part of the operand would lie outside of the ...

  • Intel 253666-024US - page 575

    Vol. 2A 3-529 INSTRUCTION SE T REF ERENCE, A-M LDS/LES/LFS/LGS/LSS—Load Far Pointer LDS/LES/LFS/L GS/LSS—Load F ar Poin ter Description Loads a far pointer (segment selector and offset) from the second operand (source operand) into a segment register and the first operand (destination oper and). The source operand specifies a 48-bit or a 32- bi ...

  • Intel 253666-024US - page 576

    3-530 Vol. 2A LDS/LES/LFS/LGS/LSS—Load Far Pointer INSTRUCTION SE T REF ERENCE, A-M If one of these instructions is executed in protected mode, additional information from the segment descriptor pointed to by the segment se lector in the source operand is loaded in the hidden part of the selected segment register . Also in protected mode, a NULL ...

  • Intel 253666-024US - page 577

    Vol. 2A 3-531 INSTRUCTION SE T REF ERENCE, A-M LDS/LES/LFS/LGS/LSS—Load Far Pointer FI; SegmentRegister ← SegmentSelector( SRC) ; SegmentRegister ← SegmentDescr iptor([SRC]); FI; ELSE IF FS, or GS is load ed with a NULL selector: THEN SegmentRegister ← NULLSelector; SegmentRegister(DescriptorV alidBit) ← 0; FI; (* Hidden flag; not accessi ...

  • Intel 253666-024US - page 578

    3-532 Vol. 2A LDS/LES/LFS/LGS/LSS—Load Far Pointer INSTRUCTION SE T REF ERENCE, A-M FI; DEST ← Offset(SRC); Real-Address or Virtual-8 086 Mode SegmentRegister ← Segmen tSelector(SRC); FI; DEST ← Offset(SRC); Flags A ffected None. Pro tected Mode Ex ceptions #UD If source operand is not a memory location. If the LOCK prefix is used. #GP(0) I ...

  • Intel 253666-024US - page 579

    Vol. 2A 3-533 INSTRUCTION SE T REF ERENCE, A-M LDS/LES/LFS/LGS/LSS—Load Far Pointer #SS If a memory operand effective address is outside the SS segment limit. #UD If source operand is not a memory location. If the LOCK prefix is used. Virtual-8086 Mode Excep tions #UD If source operand is not a memory location. If the LOCK prefix is used. #GP(0) ...

  • Intel 253666-024US - page 580

    3-534 Vol. 2A LDS/LES/LFS/LGS/LSS—Load Far Pointer INSTRUCTION SE T REF ERENCE, A-M #NP(selector) I f FS, or GS register is being loaded with a non-NULL segment selector and the segment is marked not present. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current ...

  • Intel 253666-024US - page 581

    Vol. 2A 3-535 INSTRUCTION SE T REF ERENCE, A-M LEA—Load Effective Address LEA—L oad Effective Addr ess Description Computes the effective address of the se cond oper and (the source oper and) and stores it in the first oper and (destination operand). The source operand is a memory address (offset part) specified with one of the processors addre ...

  • Intel 253666-024US - page 582

    3-536 Vol. 2A LEA—Load Effective Address INSTRUCTION SE T REF ERENCE, A-M Operat ion IF OperandS ize = 16 and AddressS ize = 16 THEN DEST ← EffectiveAddress(SRC ); (* 16-bit address *) ELSE IF Operan dSize = 16 and AddressSi ze = 32 THEN temp ← EffectiveAddress(SRC); (* 32-bit address *) DEST ← temp[0:15]; (* 16-bit addre ss *) FI; ELSE IF ...

  • Intel 253666-024US - page 583

    Vol. 2A 3-537 INSTRUCTION SE T REF ERENCE, A-M LEA—Load Effective Address DEST ← temp[0:1 5]; (* 16-bit address *) FI; ELSE IF OperandSize = 3 2 and AddressSize = 64 THEN temp ← EffectiveAddr ess(SRC); (* 64- bit address *) DEST ← temp[0:3 1]; (* 16-bit address *) FI; ELSE IF OperandSize = 6 4 and AddressSize = 64 THEN DEST ← EffectiveAdd ...

  • Intel 253666-024US - page 584

    3-538 Vol. 2A LEAVE—High Level Procedure Exit INSTRUCTION SE T REF ERENCE, A-M LEA V E—High Lev el Pr ocedure Exit Descripti on Releases the stack fr ame set up by an earlier ENTER instruction. The LEA VE instruc- tion copies the frame pointer (in the EBP register) into the stack pointer register (ESP), which releases the stack space allocated ...

  • Intel 253666-024US - page 585

    Vol. 2A 3-539 INSTRUCTION SE T REF ERENCE, A-M LEAVE—High Level Procedure Exit Flags A ffected None. Pr otected Mode Ex ceptions #SS(0) If the EBP register points to a location that is not within the limits of the current stack segment. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory refere ...

  • Intel 253666-024US - page 586

    3-540 Vol. 2A LFENCE—Load Fence INSTRUCTION SE T REF ERENCE, A-M LFENCE—Load F ence Descripti on Performs a serializing oper ation on all lo ad-from-memory instructions that were issued prior the LFENCE instruction. This serializing operation guar antees that every load instruction that precedes in program order the LFENCE instruction is global ...

  • Intel 253666-024US - page 587

    Vol. 2A 3-541 INSTRUCTION SE T REF ERENCE, A-M LGDT/LIDT—Load Global/Interrupt Descriptor Table Register L GDT /LIDT—L oad Global/Interrup t Descript or T able Register Description Loads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor table register (ID TR). The source operand speci- ...

  • Intel 253666-024US - page 588

    3-542 Vol. 2A LGDT/LIDT—Load Global/Interru pt Descriptor Table Register INSTRUCTION SE T REF ERENCE, A-M IDTR(Limit) ← SRC[0:15]; IDTR(Base) ← SRC[16:47]; FI; ELSE IF 64-bit Opera nd Si ze (* In 64-Bit Mode *) THEN IDTR(Limit) ← SRC[0:15]; IDTR(Base) ← SRC[16:79]; FI; FI; ELSE (* Instruction i s LGDT *) IF OperandSize = 16 THEN GDTR(Limi ...

  • Intel 253666-024US - page 589

    Vol. 2A 3-543 INSTRUCTION SE T REF ERENCE, A-M LGDT/LIDT—Load Global/Interrupt Descriptor Table Register Real-Address Mode Ex ceptions #UD If source operand is not a memory location. If the LOCK prefix is used. #GP If a memory operand effective address is outside the CS, DS , ES, FS, or GS segment limit. #SS If a memory operand effective address ...

  • Intel 253666-024US - page 590

    3-544 Vol. 2A LLDT—L oad Local Descriptor Table Register INSTRUCTION SE T REF ERENCE, A-M LLD T—Load L ocal Descriptor T able R egister Descripti on Loads the source operand into the segment selector field of the local descriptor table register (LDTR). The source oper and (a general-purpose register or a memory loca- tion) contains a segment se ...

  • Intel 253666-024US - page 591

    Vol. 2A 3-545 INSTRUCTION SE T REF ERENCE, A-M LLDT—Load Local Descriptor Table Register ELSE LDTR ← INVALID FI; Flags A ffected None. Pr otected Mode Ex ceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS , ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a ...

  • Intel 253666-024US - page 592

    3-546 Vol. 2A LLDT—L oad Local Descriptor Table Register INSTRUCTION SE T REF ERENCE, A-M #PF(fault-code) If a page fault occurs. #UD If the LOCK prefix is used. ...

  • Intel 253666-024US - page 593

    Vol. 2A 3-547 INSTRUCTION SE T REF ERENCE, A-M LMSW—Load Machine Status Word LMSW—L oad Machine S tatus Wor d Description Loads the source operand into the mach ine st atus word, bits 0 through 15 of register CR0. The source operand can be a 16-bit general-purpose register or a memory loca- tion. Only the low-order 4 bits of the source operand ...

  • Intel 253666-024US - page 594

    3-548 Vol. 2A LMSW—Load Machine Status Word INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) If the current privilege level is not 0. If a memory oper and effective address is outside the CS , DS, ES, FS, or GS segment limit. If the DS, ES, FS , or GS register is used to access memory and it contains a NULL segment selector . # ...

  • Intel 253666-024US - page 595

    Vol. 2A 3-549 INSTRUCTION SE T REF ERENCE, A-M LOCK—Assert LOCK# Signal Prefix LOCK —Assert L OCK# Signal Prefix Description Causes the processor’s LOCK# signal to be asserted during execution of the accom- panying instruction (turns the instruction in to an atomic instruction). In a multipro- cessor environment, the LOCK# signal insures that ...

  • Intel 253666-024US - page 596

    3-550 Vol. 2A LOCK—Assert LOCK# Signal Prefix INSTRUCTION SE T REF ERENCE, A-M Operat ion AssertLOCK#(Duration OfA ccompaningI nstruction); Flags A ffected None. Pro tected Mode Ex ceptions #UD If the LOCK prefix is used with an instruction not liste d: ADD , ADC, AND, BT C, BTR, B TS, CMPXCHG, CM PXCH8B, DEC, INC, NEG, NOT , OR, SBB, SUB, XOR, X ...

  • Intel 253666-024US - page 597

    Vol. 2A 3-551 INSTRUCTION SE T REF ERENCE, A-M LODS/LODS B/LODSW/LOD SD/LODSQ—Loa d String L ODS/L ODSB/L ODSW/L ODSD/LODSQ—L oad S tring Description Loads a byte, word, or doubleword from th e source operand into the AL, AX, or EAX register , respectively . The source oper and i s a memory location, the address of which is read from the DS:EDI ...

  • Intel 253666-024US - page 598

    3-552 Vol. 2A LODS/LODSB/LODSW/LODSD/LODSQ—Load String INSTRUCTION SE T REF ERENCE, A-M correct location . The location is always specifie d by the DS:(E)SI registers, which must be loaded correctly before the load string instruction is executed. The no-operands form pro vides “short fo rms” of the byte, word, and doubleword versions of the L ...

  • Intel 253666-024US - page 599

    Vol. 2A 3-553 INSTRUCTION SE T REF ERENCE, A-M LODS/LODS B/LODSW/LOD SD/LODSQ—Loa d String FI; FI; ELSE IF RAX ← SRC; (* Quad wo rd load *) THEN IF DF = 0 THEN (R)SI ← (R)SI + 8; ELSE (R)SI ← (R)SI – 8; FI; FI; FI; Flags A ffected None. Pr otected Mode Ex ceptions #GP(0) If a memory op er and effective address is outside the CS, DS, ES, F ...

  • Intel 253666-024US - page 600

    3-554 Vol. 2A LODS/LODSB/LODSW/LODSD/LODSQ—Load String INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a pag ...

  • Intel 253666-024US - page 601

    Vol. 2A 3-555 INSTRUCTION SE T REF ERENCE, A-M LOOP/LOOPcc—Loop According to ECX Counter L OOP/L OOP cc —Loop Ac cording to ECX Coun ter Description Performs a loop oper ation using the RCX, ECX or CX register as a counter (depending on whether address size is 64 bits, 32 bits, or 16 bits). Note that the LOOP instruction ignores REX.W ; but 64- ...

  • Intel 253666-024US - page 602

    3-556 Vol. 2A LOOP/LOOPcc—Loop According to ECX Counter INSTRUCTION SE T REF ERENCE, A-M IF (Instruction ← LOOPE) or (Instr uction ← LOOPZ) THEN IF (ZF = 1) and (Count ≠ 0) THEN BranchCon d ← 1; ELSE Branch Cond ← 0; FI; ELSE (Instruction = LOOPNE) or (Instruction = LOOPNZ) IF (ZF = 0 ) and (Count ≠ 0) THEN BranchCon d ← 1; ELSE Bra ...

  • Intel 253666-024US - page 603

    Vol. 2A 3-557 INSTRUCTION SE T REF ERENCE, A-M LOOP/LOOPcc—Loop According to ECX Counter Pr otected Mode Ex ceptions #GP(0) If the offset being jumped to is beyond the limits of the CS segment. #UD If the LOCK prefix is used. Real-Address Mode Ex ceptions #GP If the offset being jump ed to is beyond the limits of the CS segment or is outside of t ...

  • Intel 253666-024US - page 604

    3-558 Vol. 2A LSL—Load Segment Limit INSTRUCTION SE T REF ERENCE, A-M LSL —Load Segmen t Limit Descripti on Loads the unscrambled segment limit from the segment descriptor specified with the second oper and (source oper and) into the first oper and (destination operand) and sets the ZF flag in the EFLAGS register . The source oper and (which ca ...

  • Intel 253666-024US - page 605

    Vol. 2A 3-559 INSTRUCTION SE T REF ERENCE, A-M LSL—Load Segment Limit • Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are v alid for (can be accessed with) the LSL instruction. The valid special segment and gate descriptor types are given in the following table. • If the segment is not a ...

  • Intel 253666-024US - page 606

    3-560 Vol. 2A LSL—Load Segment Limit INSTRUCTION SE T REF ERENCE, A-M Read segment descriptor; IF SegmentDescriptor(Type) ≠ conforming code segment and (CPL > DPL) OR (RPL > DPL) or Segment type is no t valid for instruction THEN ZF ← 0; ELSE temp ← SegmentLimit([SRC]); IF (G ← 1) THEN temp ← ShiftLeft(12, temp) O R 00000FFFH; ELS ...

  • Intel 253666-024US - page 607

    Vol. 2A 3-561 INSTRUCTION SE T REF ERENCE, A-M LSL—Load Segment Limit Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If the memory operand effective address referencing the SS segment is in a non-canonical form. #GP(0) If the memory operand effective address is in a non-canonical form. #PF(faul ...

  • Intel 253666-024US - page 608

    3-562 Vol. 2A LTR—Load Task Register INSTRUCTION SE T REF ERENCE, A-M L TR—L oad T ask Register Descripti on Loads the source operand into the segment selector field of the task register . Th e source operand (a general-purpose register or a memory location) contains a segment selector that points to a task state segment (TSS). After the se gme ...

  • Intel 253666-024US - page 609

    Vol. 2A 3-563 INSTRUCTION SE T REF ERENCE, A-M LTR—Load Task Register Flags A ffected None. Pr otected Mode Ex ceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS , ES, FS, or GS segment limit. If the source operand contains a NULL segment selector . If the DS, ES, FS , or GS regist ...

  • Intel 253666-024US - page 610

    3-564 Vol. 2A LTR—Load Task Register INSTRUCTION SE T REF ERENCE, A-M #NP(selector) I f the TSS is marked not present. #PF(fault-code) If a page fault occurs. #UD If the LOCK prefix is used. ...

  • Intel 253666-024US - page 611

    Vol. 2A 3-565 INSTRUCTION SE T REF ERENCE, A-M MASKMOVDQU—Store Selected Bytes of Double Quadword MASKMO VDQU—S tore Se lected Bytes of Double Quadw ord Description Stores selected bytes from the source operand (first oper and) into an 128-bit memory location. The mask operand (second oper and) selects which bytes from the source operand are wr ...

  • Intel 253666-024US - page 612

    3-566 Vol. 2A MASKMOVDQU—Store Selected Bytes of D ouble Quadword INSTRUCTION SE T REF ERENCE, A-M In 64-bit mode, use of the REX.R prefix perm its this instruction to access additional registers (XMM8- XMM15). Operat ion IF (MASK[7] = 1) THEN DEST[DI/EDI] ← SRC[7:0] ELSE (* Memory location unchanged *); FI; IF (MASK[15] = 1) THEN DEST[DI/EDI + ...

  • Intel 253666-024US - page 613

    Vol. 2A 3-567 INSTRUCTION SE T REF ERENCE, A-M MASKMOVDQU—Store Selected Bytes of Double Quadword Virtual-8086 Mode Excep tions Same exceptions as in real address mode. #PF(fault-code) F or a page fault (implementation specific). #UD If the LOCK prefix is used. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc e ...

  • Intel 253666-024US - page 614

    3-568 Vol. 2A MASKMO VQ—Store Selected Bytes of Qu adword INSTRUCTION SE T REF ERENCE, A-M MASKMOV Q—S tore Selected Bytes o f Quadwor d Descripti on Stores selected bytes from the source operand (first oper and) into a 64-bit memory location. The mask operand (second operand) selects which bytes from the source operand are written to mem ory . ...

  • Intel 253666-024US - page 615

    Vol. 2A 3-569 INSTRUCTION SE T REF ERENCE, A-M MASKMOVQ—Store Select ed Bytes of Quadword The MASKMOVQ instruction can be used to improv e performance for algorithms that need to merge data on a byte-by-byte basi s. It should not cause a read for owner- ship; doing so generates unnecessary bandwidth since data is to be written directly using the ...

  • Intel 253666-024US - page 616

    3-570 Vol. 2A MASKMO VQ—Store Selected Bytes of Qu adword INSTRUCTION SE T REF ERENCE, A-M #MF If there is a pending FPU exception. #UD I f CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode E xc eptions Same exceptions as in real address mode. #PF(fault-code) F or a page ...

  • Intel 253666-024US - page 617

    Vol. 2A 3-571 INSTRUCTION SE T REF ERENCE, A-M MAXPD—Return Maximu m Packed Double -Precision Floating-Point Value s MAXPD—Re turn Maximum Pack ed Double-Precision Floating-Poin t Va l u e s Description Performs a SIMD compare of the packed doub le-precision floating-point v alues in the destination operand (first oper and) and the source opera ...

  • Intel 253666-024US - page 618

    3-572 Vol. 2A MAXPD—Return Maximum Packed Double -P recision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M ELSE SRC[127:64]; FI; FI; Intel C/C + + Compiler Intrinsic Equivalent MAXPD __m128d _mm_max_pd(__ m128d a, __m128d b) SIMD Floating-Poin t Ex ceptions Invalid (including QNaN source operand), Denormal. Pro tected Mode Ex ceptions #G ...

  • Intel 253666-024US - page 619

    Vol. 2A 3-573 INSTRUCTION SE T REF ERENCE, A-M MAXPD—Return Maximu m Packed Double -Precision Floating-Point Value s Virtual-8086 Mode Excep tions Same exceptions as in real address mode. #PF(fault -code) For a page fault. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory a ddress refe ...

  • Intel 253666-024US - page 620

    3-574 Vol. 2A MAXPS—Return Maximum Packed Single-Precision Floating-P oint Values INSTRUCTION SE T REF ERENCE, A-M MAXPS—Re turn Maximum Pack ed Single-Precision Floating-Poin t Va l u e s Descripti on Performs a SIMD compare of the packed sing le-precision floating-point v alues in the destination operand (first oper and) and the source operan ...

  • Intel 253666-024US - page 621

    Vol. 2A 3-575 INSTRUCTION SE T REF ERENCE, A-M MAXPS—Return Maximum Packed Single-Precis ion Floating-Point Values THEN DEST[127:96]; ELSE SRC[127:96]; FI; FI; Intel C/C + + Compiler Intrinsi c Equivalent MAXPS __m128d _mm_max_ps(__m1 28d a, __m128d b) SIMD Floating-Point Ex ceptions Inv alid (including QNaN source oper and), Denormal. Pr otected ...

  • Intel 253666-024US - page 622

    3-576 Vol. 2A MAXPS—Return Maximum Packed Single-Precision Floating-P oint Values INSTRUCTION SE T REF ERENCE, A-M If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode E xc eptions Same exceptions as in real address mode. #PF(fault-code) F or a page fault. Compatibility Mode Exc e p tions Same exceptions as in protected ...

  • Intel 253666-024US - page 623

    Vol. 2A 3-577 INSTRUCTION SE T REF ERENCE, A-M MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value MAXSD—Re turn Maximum Scalar Do uble-Precision Floating-Poin t Va l u e Description Compares the low double-precision floating -point values in the destination oper and (first operand) and the source oper and (second operand), and re ...

  • Intel 253666-024US - page 624

    3-578 Vol. 2A MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M Intel C/C + + Compiler Intrinsic Equivalent MAXSD __m128d _mm_max_sd(__m128d a, _ _m128d b) SIMD Floating-Poin t Ex ceptions Invalid (including QNaN source operand), Denormal. Pro tected Mode Ex ceptions #GP(0) For an illegal memory op ...

  • Intel 253666-024US - page 625

    Vol. 2A 3-579 INSTRUCTION SE T REF ERENCE, A-M MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value #PF(fault -code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory referen ce is made. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory a dd ...

  • Intel 253666-024US - page 626

    3-580 Vol. 2A MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M MAXSS—R eturn Maximum Scalar Single -Precision Floating-P oint V alue Descripti on Compares the low single-precision floating -point values in the destination operand (first operand) and the source oper and (second oper and), and ret ...

  • Intel 253666-024US - page 627

    Vol. 2A 3-581 INSTRUCTION SE T REF ERENCE, A-M MAXSS—Return Maximum Scalar Single-P recision Floating-Point Value SIMD Floating-Point Ex ceptions Inv alid (including QNaN source oper and), Denormal. Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand e ...

  • Intel 253666-024US - page 628

    3-582 Vol. 2A MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc eptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. # ...

  • Intel 253666-024US - page 629

    Vol. 2A 3-583 INSTRUCTION SE T REF ERENCE, A-M MFENCE—Memory Fence MFENCE—Memory F ence Description Performs a serializing operation on a ll load-from-memory and store-to-memory instructions that were issued prior the MFEN CE ins truction. This serializing operation guarantees that ev ery load and store instruction that precedes in program orde ...

  • Intel 253666-024US - page 630

    3-584 Vol. 2A MINPD—Return Minimum Packed Double-Precision Floating-P oint Values INSTRUCTION SE T REF ERENCE, A-M MINPD—R eturn Minimum P ack ed Double-Precision Floating-Poin t Va l u e s Descripti on Performs a SIMD compare of the packed doub le-precision floating-point values in the destination operand (first oper and) and the source operan ...

  • Intel 253666-024US - page 631

    Vol. 2A 3-585 INSTRUCTION SE T REF ERENCE, A-M MINPD—Return Minimum Packed Double-Precision Floating-Point Values THEN DEST[127:64] ELSE SRC[127:64]; FI; FI; Intel C/C + + Compiler Intrinsi c Equivalent MINPD __m128d _mm_min_pd(__m128d a , __m128d b) SIMD Floating-Point Ex ceptions Inv alid (including QNaN source oper and), Denormal. Pr otected M ...

  • Intel 253666-024US - page 632

    3-586 Vol. 2A MINPD—Return Minimum Packed Double-Precision Floating-P oint Values INSTRUCTION SE T REF ERENCE, A-M If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. Virtual-8086 Mode E xc eptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. Compatibility Mode Exc eptions Same exceptions as in protecte ...

  • Intel 253666-024US - page 633

    Vol. 2A 3-587 INSTRUCTION SE T REF ERENCE, A-M MINPS—Return Minimum Packed Single-Precisi on Floating-Point Values MINPS—Re turn Minimum Pack ed Single-Precision Floating-P oint Va l u e s Description Performs a SIMD compare of th e packed single-precision floating-point values in the destination operand (first oper and) and the source operand ...

  • Intel 253666-024US - page 634

    3-588 Vol. 2A MINPS—Return Minimum Packed Single-P recision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M THEN DEST[127:96] ELSE SRC[127:96]; FI; FI; Intel C/C + + Compiler Intrinsic Equivalent MINPS __m128d _mm_min_ps(__m128d a, __ m128d b) SIMD Floating-Poin t Ex ceptions Invalid (including QNaN source operand), Denormal. Pro tected Mo ...

  • Intel 253666-024US - page 635

    Vol. 2A 3-589 INSTRUCTION SE T REF ERENCE, A-M MINPS—Return Minimum Packed Single-Precisi on Floating-Point Values If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode Excep tions Same exceptions as in real address mode. #PF(fault -code) For a page fault. Compatibility Mode Ex ceptions Same exceptions as in protected m ...

  • Intel 253666-024US - page 636

    3-590 Vol. 2A MINSD—Return Minimum Scalar Double-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M MINSD—Re turn Minimum Scalar Double -Pr ecision Floating-Poin t V alue Descripti on Compares the low double-precision floating -point values in the destination operand (first operand) and the source oper and (second operand), and ret ...

  • Intel 253666-024US - page 637

    Vol. 2A 3-591 INSTRUCTION SE T REF ERENCE, A-M MINSD—Return Minimum Scalar Double-Prec ision Floating-Point Value SIMD Floating-Point Ex ceptions Inv alid (including QNaN source oper and), Denormal. Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand e ...

  • Intel 253666-024US - page 638

    3-592 Vol. 2A MINSD—Return Minimum Scalar Double-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc eptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. # ...

  • Intel 253666-024US - page 639

    Vol. 2A 3-593 INSTRUCTION SE T REF ERENCE, A-M MINSS—Return Minimum Scalar Single-Precision Float ing-Point Value MINSS—Re turn Minimum Scalar Single -Pr ecision Floating-Point V alue Description Compares the low single-precision floating-point v alues in the destination operand (first operand) and the source operan d (second operand), and retu ...

  • Intel 253666-024US - page 640

    3-594 Vol. 2A MINSS—Return Minimum Scalar Single-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M SIMD Floating-Poin t Ex ceptions Invalid (including QNaN source operand), Denormal. Pro tected Mode Ex ceptions #GP(0) For an illegal memory oper and effective address in the CS, DS, ES, FS or GS segm ents. #SS(0) If a memory oper and ...

  • Intel 253666-024US - page 641

    Vol. 2A 3-595 INSTRUCTION SE T REF ERENCE, A-M MINSS—Return Minimum Scalar Single-Precision Float ing-Point Value Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #SS(0) If a memory a ddress referenc ing the SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. ...

  • Intel 253666-024US - page 642

    3-596 Vol. 2A MONITO R—Set Up Monitor Address INSTRUCTION SE T REF ERENCE, A-M MONIT OR—Set Up Monitor Addr ess Descripti on The MONITOR instruction arms address monitoring hardw are using an address spec- ified in EAX (the address range that the monitoring hardware checks for store opera- tions can be determined by using CPUID). A store to an ...

  • Intel 253666-024US - page 643

    Vol. 2A 3-597 INSTRUCTION SE T REF ERENCE, A-M MONITOR—Set Up Monitor Address Operation MONITOR sets up an address r ange for the monitor hardware using the content of EAX as an effective address and puts the monitor hardware in armed state. Alw ays use memory of the write-back caching type . A store to the specified addre ss range will trigger t ...

  • Intel 253666-024US - page 644

    3-598 Vol. 2A MONITO R—Set Up Monitor Address INSTRUCTION SE T REF ERENCE, A-M 64-Bit Mode Exc eptions #GP(0) If the linear address of the operand in the CS, DS, ES, FS , or GS segment is in a non-canonical form. If RCX ← 0. #SS(0) If the linear address of the operand in the SS segment is in a non-canonical form. #PF(fault-code) F or a page fau ...

  • Intel 253666-024US - page 645

    Vol. 2A 3-599 INSTRUCTION SE T REF ERENCE, A-M MOV—Move MO V—Mov e Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 88 / r MOV r/m8,r8 Va l i d Va l i d M o v e r8 to r/m8. REX + 88 / r MOV r/m8 ***, r8 *** Va l i d N . E . M o ve r8 to r/m8. 89 / r MOV r/m16,r16 Va l i d Val i d M o ve r16 to r/m16. 89 / r MOV r/m32,r32 Va l i d Val ...

  • Intel 253666-024US - page 646

    3-600 Vol. 2A MOV—Move INSTRUCTION SE T REF ERENCE, A-M Descripti on Copies the second operand (source operand) to the first operand (destination operand ). The source operand can be an immediate v alue, general-purpose register , segment register , or memory location; the destination register can be a general- purpose register , segment register ...

  • Intel 253666-024US - page 647

    Vol. 2A 3-601 INSTRUCTION SE T REF ERENCE, A-M MOV—Move below). The segment descriptor data is obtained from the GD T or LD T entry for the specified segment selector . A NULL segment selector (values 0000-0003) can be load ed into the DS, ES, FS , and GS registers without causing a protection exception. However , any subsequent attempt to refere ...

  • Intel 253666-024US - page 648

    3-602 Vol. 2A MOV—Move INSTRUCTION SE T REF ERENCE, A-M Loading a segment register while in protec ted mode results in special checks and actions, as described in the following lis ting. These checks are performed on the segment selector and the segment descriptor to which it points. IF SS is loaded THEN IF segment selector is NULL THEN #GP(0) ; ...

  • Intel 253666-024US - page 649

    Vol. 2A 3-603 INSTRUCTION SE T REF ERENCE, A-M MOV—Move Pr otected Mode Ex ceptions #GP(0) If attempt is made to load S S register with NULL segment selector . If the destination operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS , ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contai ...

  • Intel 253666-024US - page 650

    3-604 Vol. 2A MOV—Move INSTRUCTION SE T REF ERENCE, A-M #SS(0) If a memory oper and effective add ress is outside the S S segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If attempt is made to load the CS register . If the LOCK prefix is used. Compatibili ...

  • Intel 253666-024US - page 651

    Vol. 2A 3-605 INSTRUCTION SE T REF ERENCE, A-M MOV—Move to/from Control Registers MO V—Mov e to/fr om Contr ol R egisters Description Moves the contents of a control regis ter (CR0, CR2, CR3, CR4, or CR8) to a general- purpose register or the contents of a gener al purpose register to a control register . The operand size for these instructions ...

  • Intel 253666-024US - page 652

    3-606 Vol. 2A MOV—Move to/from Control Registers INSTRUCTION SE T REF ERENCE, A-M and CR3 remain clear after any load of those registers; attempts to set them ha ve no impact. On Pentium 4, Intel X eon and P6 fa mily processors, CR0.ET remains set after any load of CR0; attempts to clear this bit hav e no impact. At the opcode level, the reg fiel ...

  • Intel 253666-024US - page 653

    Vol. 2A 3-607 INSTRUCTION SE T REF ERENCE, A-M MOV—Move to/from Control Registers If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1 wh en the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1). If an attempt is made to write a 1 to any reserved bit in CR4. If any of the re ...

  • Intel 253666-024US - page 654

    3-608 Vol. 2A MOV—Move to/from Debug Registers INSTRUCTION SE T REF ERENCE, A-M MO V—Mov e to/fr om Debug Regis ters Descripti on Moves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose register or vice versa. The operand size for these instruc- tions is always 32 bits in non-64-bit modes, regardl ...

  • Intel 253666-024US - page 655

    Vol. 2A 3-609 INSTRUCTION SE T REF ERENCE, A-M MOV—Move to/from Debug Registers Flags A ffected The OF , SF , ZF , AF , PF , and CF flag s are undefined. Pr otected Mode Ex ceptions #GP(0) If the current privilege level is not 0. #UD If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or DR5. If the LOCK prefix ...

  • Intel 253666-024US - page 656

    3-610 Vol. 2A MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M MO V APD—Mov e Aligned Pack ed Double-Precision Floating-Poin t Va l u e s Descripti on Moves a double quadword containing two packed double-precision floating-point values from the source operand (second op er and) to the destinatio ...

  • Intel 253666-024US - page 657

    Vol. 2A 3-611 INSTRUCTION SE T REF ERENCE, A-M MOVAPD—Move Aligned Packed Double-Prec ision Floating-Point Values Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #SS(0) For an illegal address i ...

  • Intel 253666-024US - page 658

    3-612 Vol. 2A MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #UD I f CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 659

    Vol. 2A 3-613 INSTRUCTION SE T REF ERENCE, A-M MOVAPS—Move Aligned Packed Single-Precision Floating-Point Valu es MO V APS—Mov e Aligned Pack ed Single-Precision Floating-Poin t V alues Description Moves a double quadword containing f our packed single-precision floating-point values from the source oper and (second operand) to the destination ...

  • Intel 253666-024US - page 660

    3-614 Vol. 2A MOVAPS—Move Aligned Packed Single-Precision Floating-P oint Values INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) For an illegal memory oper and effective address in the CS, DS, ES, FS or GS segm ents. If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #SS(0) For an illegal address ...

  • Intel 253666-024US - page 661

    Vol. 2A 3-615 INSTRUCTION SE T REF ERENCE, A-M MOVAPS—Move Aligned Packed Single-Precision Floating-Point Valu es #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0 . If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 662

    3-616 Vol. 2A MOVD/MOVQ—Move Doubleword/Move Quadword INSTRUCTION SE T REF ERENCE, A-M MO VD/MOV Q—Mo ve Doublew ord/Mo ve Quadw ord Descripti on Copies a doubleword from the source oper and (second operand) to the destination operand (first oper and). The source and destination operands can be general- purpose registers, MMX technology registe ...

  • Intel 253666-024US - page 663

    Vol. 2A 3-617 INSTRUCTION SE T REF ERENCE, A-M MOVD/MOVQ—Move Doubl eword/Move Quadword Operation MOVD instruction when destination oper and is MMX technology r egister: DEST[31: 0] ← SRC; DEST[63:32] ← 00000000H; MOVD instruction when destination oper and is XMM register: DEST[31: 0] ← SRC; DEST[127:32] ← 00000000000000000000 0000H; MOVD ...

  • Intel 253666-024US - page 664

    3-618 Vol. 2A MOVD/MOVQ—Move Doubleword/Move Quadword INSTRUCTION SE T REF ERENCE, A-M #UD If CR0 .EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-S SE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, ...

  • Intel 253666-024US - page 665

    Vol. 2A 3-619 INSTRUCTION SE T REF ERENCE, A-M MOVD/MOVQ—Move Doubl eword/Move Quadword #UD If CR0.EM[bit 2] = 1. (XMM register operations only ) if CR4.OSFXSR[bit 9] = 0. (XMM register operations only) if CPUID.01H:EDX.S SE2[bit 26] = 0. If the LOCK prefix is used. #NM If CR0.TS[bit 3] = 1. #MF (MMX register operations only) If there is a pendin ...

  • Intel 253666-024US - page 666

    3-620 Vol. 2A MOVDDUP—Move One Double-FP and Duplicate INSTRUCTION SE T REF ERENCE, A-M MO VDDUP—Mov e One Double-FP and Duplicate Descripti on The linear address corresponds to the addre ss of the least-significant byte of the referenced memory data. When a memory a ddress is indicated, the 8 bytes of data at memory location m64 are loaded. Wh ...

  • Intel 253666-024US - page 667

    Vol. 2A 3-621 INSTRUCTION SE T REF ERENCE, A-M MOVDDUP—Move One Double-FP and Duplicate xmm1[127:6 4] = m64; ELSE (* Move in struction *) xmm1[63:0] = xmm2[63:0]; xmm1[127:64] = xmm2[63:0]; FI; Intel C/C + + Compiler Intrinsi c Equivalent MOVDDUP __m128d _mm_movedup_pd(__m128d a) __m128d _mm_loadd up_pd(double const * dp) Exc eptions None Numeric ...

  • Intel 253666-024US - page 668

    3-622 Vol. 2A MOVDDUP—Move One Double-FP and Duplicate INSTRUCTION SE T REF ERENCE, A-M Virtual 8086 Mode Ex ceptions GP(0) If any part of the operand would lie outside of the effe ctive address space from 0 to 0FFFFH. #NM If CR0.TS[bit 3] = 1. #UD I f CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK pr ...

  • Intel 253666-024US - page 669

    Vol. 2A 3-623 INSTRUCTION SE T REF ERENCE, A-M MOVDQA—Move Aligned Double Quadword MO VDQA—Mo ve Aligned Double Quadwor d Description Moves a double quadword from the source oper and (second operand) to the destina- tion operand (first operan d). This instruct ion can be used to load an XMM register from a 128-bit memory location, to store the ...

  • Intel 253666-024US - page 670

    3-624 Vol. 2A MOVDQA—Move Aligned Double Quadwo rd INSTRUCTION SE T REF ERENCE, A-M #SS(0) If a memory oper and effective add ress is outside the S S segment limit. #NM If CR0.TS[bit 3] = 1. #UD If CR0 .EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Addr ess Mode Exc eptions #GP(0) I ...

  • Intel 253666-024US - page 671

    Vol. 2A 3-625 INSTRUCTION SE T REF ERENCE, A-M MOVDQU—Move Unaligned Double Quadword MO VDQU—Mov e Unaligned Double Quadwor d Description Moves a double quadword from the source oper and (second operand) to the destina- tion operand (first operan d). This instruct ion can be used to load an XMM register from a 128-bit memory location, to store ...

  • Intel 253666-024US - page 672

    3-626 Vol. 2A MOVDQU—Move Unaligned Double Quadword INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #GP(0) If a memory operand effe ctive address is outside the CS, DS , ES, FS, or GS segment limit. #SS(0) If a memory oper and effective add ress is out ...

  • Intel 253666-024US - page 673

    Vol. 2A 3-627 INSTRUCTION SE T REF ERENCE, A-M MOVDQU—Move Unaligned Double Quadword #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 674

    3-628 Vol. 2A MOVDQ2Q—Move Quadword from XMM to MMX Technology Register INSTRUCTION SE T REF ERENCE, A-M MO VDQ2Q—Mov e Quadwor d fro m XMM to MMX T echnology R egister Descripti on Moves the low quadword from the source oper and (second operand) to the destina- tion operand (first oper and). The source op erand is an XMM register and the desti ...

  • Intel 253666-024US - page 675

    Vol. 2A 3-629 INSTRUCTION SE T REF ERENCE, A-M MOVDQ2Q—Move Quadword from XMM to MMX Technology Register Virtual-8086 Mode Excep tions Same exceptions as in protected mode. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 676

    3-630 Vol. 2A MOVHLPS— Move Packed Single-Precision Floating-Po int Values High to Low INSTRUCTION SE T REF ERENCE, A-M MO VHLPS— Mov e Pack ed Single-Precision Floating-Poin t V alues High to Low Descripti on Moves two pack ed single-precision floating-p oint values from the high quadword of the source operand (second oper and) to the low quad ...

  • Intel 253666-024US - page 677

    Vol. 2A 3-631 INSTRUCTION SE T REF ERENCE, A-M MOVHLPS— Move Packed Single-Precision Floating-Point Values High to Low Virtual 8086 M ode Ex ceptions Same exceptions as in protected mode. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 678

    3-632 Vol. 2A MOVHPD—Move High Packed Double-P recision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M MO VHPD—Mov e High Pack ed Double-Precision Floating-Poin t V alue Descripti on Moves a double-precision floating-point value from the source operand (second operand) to the destination operand (first oper and). The source and destinati ...

  • Intel 253666-024US - page 679

    Vol. 2A 3-633 INSTRUCTION SE T REF ERENCE, A-M MOVHPD—Move High Packed Double-P recision Floating-Point Value Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault -code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If ...

  • Intel 253666-024US - page 680

    3-634 Vol. 2A MOVHPD—Move High Packed Double-P recision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. ...

  • Intel 253666-024US - page 681

    Vol. 2A 3-635 INSTRUCTION SE T REF ERENCE, A-M MOVHPS—Move High Packed Single-Precision Floating-Point Values MO VHPS—Mov e High Pack ed Single-Precision Floating-Poin t V alues Description Moves two packed single-precision floating -point v alues from the source oper and (second operand) to the destination operan d (first operand). The source ...

  • Intel 253666-024US - page 682

    3-636 Vol. 2A MOVHPS—Move High Packed Single-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) F or a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0 .EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If a ...

  • Intel 253666-024US - page 683

    Vol. 2A 3-637 INSTRUCTION SE T REF ERENCE, A-M MOVHPS—Move High Packed Single-Precision Floating-Point Values #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. ...

  • Intel 253666-024US - page 684

    3-638 Vol. 2A MOVLHPS—Move Packed Si ngle-Precision Floating-Point Values Low to High INSTRUCTION SE T REF ERENCE, A-M MO VLHPS—Mov e Pack ed Single-Precision Floating-P oint V alues Lo w to High Descripti on Moves two pack ed single-precision floating -point values from the low quadword of the source operand (second oper and) to the high quadw ...

  • Intel 253666-024US - page 685

    Vol. 2A 3-639 INSTRUCTION SE T REF ERENCE, A-M MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 686

    3-640 Vol. 2A MOVLPD—Move Low Packed Double-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M MO VLPD—Mov e Lo w Pack ed Double-Precision Floating-Point V alue Descripti on Moves a double-precision floating-point value from the source operand (second operand) to the destination operand (first oper and). The source and destination ...

  • Intel 253666-024US - page 687

    Vol. 2A 3-641 INSTRUCTION SE T REF ERENCE, A-M MOVLPD—Move Low Packed Double-P recision Floating-Point Value #SS(0) For an illegal address in the SS segment. #PF(fault -code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If ali ...

  • Intel 253666-024US - page 688

    3-642 Vol. 2A MOVLPS—Move Low Packed Single-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M MO VLPS—Mov e Lo w Pack ed Single-Precision Floating-Poin t V alues Descripti on Moves two pack ed single-precision floating-point values from the source operand (second operand) and the de stination operan d (first operand). Th e source ...

  • Intel 253666-024US - page 689

    Vol. 2A 3-643 INSTRUCTION SE T REF ERENCE, A-M MOVLPS—Move Low Packed Single-Precision Floating-Point Values #SS(0) For an illegal address in the SS segment. #PF(fault -code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alig ...

  • Intel 253666-024US - page 690

    3-644 Vol. 2A MOVLPS—Move Low Packed Single-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. ...

  • Intel 253666-024US - page 691

    Vol. 2A 3-645 INSTRUCTION SE T REF ERENCE, A-M MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask MO VMSKPD—Extr act Pa ck ed Double-Precision Floating-P oint Sign Mask Description Extracts the sign bits from the packed double-precision floating-point v alues in the source operand (second oper and), formats them into a 2-bit mask ...

  • Intel 253666-024US - page 692

    3-646 Vol. 2A MOVMSKPD—Extract Packed Double -Precision Floating-Point Sign Mask INSTRUCTION SE T REF ERENCE, A-M #UD I f CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. Real-Addr ess Mode Exc eptions Same exceptions as in protected mode. Virtual-8086 Mode E xc eptions Same exceptio ...

  • Intel 253666-024US - page 693

    Vol. 2A 3-647 INSTRUCTION SE T REF ERENCE, A-M MOVMSKPS—Extract Packed Single-Pre cision Floating-Point Sign Mask MO VMSKPS—Extr act Pa cked Single-Pr ecision Floating-Poin t Sign Mask Description Extracts the sign bits from the packed sing le-precision floating-point v alues in the source operand (second oper and), formats them into a 4-bit ma ...

  • Intel 253666-024US - page 694

    3-648 Vol. 2A MOVMSKPS—Extract Packed Single-Pre cision Floating-P oint Sign Mask INSTRUCTION SE T REF ERENCE, A-M #UD I f CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Real-Addr ess Mode Exc eptions Same exceptions as in protected mode. Virtual 8086 Mode Ex ceptions Same exceptions a ...

  • Intel 253666-024US - page 695

    Vol. 2A 3-649 INSTRUCTION SE T REF ERENCE, A-M MOVNTDQ—Store Double Quadword Using Non-Temporal Hint MO VNTDQ—S tore Double Quadw ord Using Non-T em poral Hin t Description Moves the double quadword in the source operand (second oper and) to the destina- tion operand (first oper and) using a non-temporal hint to prevent caching of the data duri ...

  • Intel 253666-024US - page 696

    3-650 Vol. 2A MOVNTDQ—Store Double Quadword Using Non-Temporal H int INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) For an illegal memory oper and effective address in the CS, DS, ES, FS or GS segm ents. If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #SS(0) For an illegal address in the SS s ...

  • Intel 253666-024US - page 697

    Vol. 2A 3-651 INSTRUCTION SE T REF ERENCE, A-M MOVNTDQ—Store Double Quadword Using Non-Temporal Hint #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 698

    3-652 Vol. 2A MOVNTI—Store Doublewor d Using Non-Temporal Hint INSTRUCTION SE T REF ERENCE, A-M MO VNTI—S tore Doublew ord Using Non-T emporal Hin t Descripti on Moves the doubleword integer in the source operand (second operand) to the desti- nation operand (first oper and) using a non-tempor al hint to minimize cache pollution during the writ ...

  • Intel 253666-024US - page 699

    Vol. 2A 3-653 INSTRUCTION SE T REF ERENCE, A-M MOVNTI—Store Doubleword Using Non-Temporal Hint Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault -code) For a page fault. #UD If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LO ...

  • Intel 253666-024US - page 700

    3-654 Vol. 2A MOVNTPD—Store Packed Double -Precision Fl oating-Point Values Using Non-Temporal Hint INSTRUCTION SE T REF ERENCE, A-M MO VNTPD—S tore P ack ed Double-Precision Floating-P oint V alues Using Non-T empor al Hint Descripti on Moves the double quadword in the source op er and (second operand) to the d estina- tion operand (first oper ...

  • Intel 253666-024US - page 701

    Vol. 2A 3-655 INSTRUCTION SE T REF ERENCE, A-M MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #SS(0) For an ...

  • Intel 253666-024US - page 702

    3-656 Vol. 2A MOVNTPD—Store Packed Double -Precision Fl oating-Point Values Using Non-Temporal Hint INSTRUCTION SE T REF ERENCE, A-M #UD If CR0 .EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 703

    Vol. 2A 3-657 INSTRUCTION SE T REF ERENCE, A-M MOVNTPS—Store Packed Single -Precision Fl oating-Point Values Using Non-Temporal Hint MO VNTPS—S tore P ack ed Single-Precision Floating-P oint V alues Using Non-T empor al Hint Description Moves the double quadword in the source operand (second oper and) to the destina- tion operand (first operan ...

  • Intel 253666-024US - page 704

    3-658 Vol. 2A MOVNTPS—Store Packed Single-Precisio n Fl oating-Point Values Using Non-Temporal Hint INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) For an illegal memory oper and effective address in the CS, DS, ES, FS or GS segm ents. If a memory operand is not aligned on a 16-byte boundary , regardless of segment. #SS(0) For ...

  • Intel 253666-024US - page 705

    Vol. 2A 3-659 INSTRUCTION SE T REF ERENCE, A-M MOVNTPS—Store Packed Single -Precision Fl oating-Point Values Using Non-Temporal Hint #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 706

    3-660 Vol. 2A MOVNTQ—Store of Quadword Using Non-Temporal Hint INSTRUCTION SE T REF ERENCE, A-M MO VNT Q—S tore o f Quadwor d Using Non-T emporal Hin t Descripti on Moves the quadword in the source oper an d (second operand) to the destination operand (first oper and) using a non-temporal hint to minimize cache pollution during the write to mem ...

  • Intel 253666-024US - page 707

    Vol. 2A 3-661 INSTRUCTION SE T REF ERENCE, A-M MOVNTQ—Store of Quadword Using Non-Temporal Hint #SS(0) For an illegal address in the SS segment. #PF(fault -code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If CR0.EM[bit 2] = 1. If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) I ...

  • Intel 253666-024US - page 708

    3-662 Vol. 2A MOVNTQ—Store of Quadword Using Non-Temporal Hint INSTRUCTION SE T REF ERENCE, A-M #UD If CR0 .EM[bit 2] = 1. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. ...

  • Intel 253666-024US - page 709

    Vol. 2A 3-663 INSTRUCTION SE T REF ERENCE, A-M MOVQ—Move Quadword MO VQ—Mo ve Quadw ord Description Copies a quadword from the source oper and (second operand) to the destination operand (first oper and). The source and destination operands can be MMX tech- nology registers, XMM registers, or 64-bit memory locations. This instruction can be use ...

  • Intel 253666-024US - page 710

    3-664 Vol. 2A MOVQ—Move Quadwo rd INSTRUCTION SE T REF ERENCE, A-M DEST[127:64] ← 0000000000000000H; Flags A ffected None. SIMD Floating-Poin t Ex ceptions None. Pro tected Mode Ex ceptions #GP(0) If the destination operand is in a non-writable segment. If a memory oper and effective address is outside the CS , DS, ES, FS, or GS segment limit. ...

  • Intel 253666-024US - page 711

    Vol. 2A 3-665 INSTRUCTION SE T REF ERENCE, A-M MOVQ—Move Quadword Virtual-8086 Mode Excep tions Same exceptions as in real address mode. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory referen ce is made. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc e ...

  • Intel 253666-024US - page 712

    3-666 Vol. 2A MOVQ2DQ—Move Quadword from MMX Technology to XMM Register INSTRUCTION SE T REF ERENCE, A-M MO VQ2DQ—Mo ve Quadwor d from MMX T echnology t o XMM Register Descripti on Moves the quadword from the source oper and (second operand) to the low quadword of the destination operand (first operand). The source operand is an MMX technology ...

  • Intel 253666-024US - page 713

    Vol. 2A 3-667 INSTRUCTION SE T REF ERENCE, A-M MOVQ2DQ—Move Quadword from MMX Technology to XMM Register Virtual-8086 Mode Excep tions Same exceptions as in protected mode. Compatibility Mode Ex ceptions Same exceptions as in protected mode. 64-Bit Mode Exc eptions Same exceptions as in protected mode. ...

  • Intel 253666-024US - page 714

    3-668 Vol. 2A MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String INSTRUCTION SE T REF ERENCE, A-M M OVS /M OVS B / MOV SW /M OV SD / MOV S Q— M ove D a t a f ro m S tring to S tring Descripti on Moves the byte, word, or doubleword spec ified with the seco nd operand (so urce operand) to the location specified with th e first operand ...

  • Intel 253666-024US - page 715

    Vol. 2A 3-669 INSTRUCTION SE T REF ERENCE, A-M MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from Stri ng to String At the assembly -code level, two forms of th is instruction are allowed: the “explicit- operands” form and the “no-oper ands” form . The explicit-oper ands form (specified with the MOVS mnemonic) allows the source and destination o ...

  • Intel 253666-024US - page 716

    3-670 Vol. 2A MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String INSTRUCTION SE T REF ERENCE, A-M (E)SI ← (E)SI – 1; (E)DI ← (E)DI – 1; FI; ELSE IF (Word move) THEN IF DF = 0 (E)SI ← (E)SI + 2; (E)DI ← (E)DI + 2; FI; ELSE (E)SI ← (E)SI – 2; (E)DI ← (E)DI – 2; FI; ELSE IF (Doubleword move) THEN IF DF = 0 (E)SI ← (E) ...

  • Intel 253666-024US - page 717

    Vol. 2A 3-671 INSTRUCTION SE T REF ERENCE, A-M MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from Stri ng to String (R|E)SI ← (R|E)SI + 4; (R|E)DI ← (R|E)DI + 4; FI; ELSE (R|E)SI ← (R|E)SI – 4; (R|E)DI ← (R|E)DI – 4; FI; ELSE IF (Quadword m ove) THEN IF DF = 0 (R|E)SI ← (R|E)SI + 8; (R|E)DI ← (R|E)DI + 8; FI; ELSE (R|E)SI ← (R|E)SI – ...

  • Intel 253666-024US - page 718

    3-672 Vol. 2A MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String INSTRUCTION SE T REF ERENCE, A-M Virtual-8086 Mode E xc eptions #GP(0) If a memory operand effe ctive address is outside the CS, DS , ES, FS, or GS segment limit. #SS(0) If a memory oper and effective add ress is outside the S S segment limit. #PF(fault-code) If a page fau ...

  • Intel 253666-024US - page 719

    Vol. 2A 3-673 INSTRUCTION SE T REF ERENCE, A-M MOVSD—Move Scalar Double-Precision Floating-Point Value MO VSD—Mo ve Scalar Double-Pr ecision Floating-Poin t V alue Description Moves a scalar double-precision floating-point value from the source operand (second operand) to the destination operan d (first operand). The source and destina- tion op ...

  • Intel 253666-024US - page 720

    3-674 Vol. 2A MOVSD—Move Scalar Double-Precision Floating-Point Value INSTRUCTION SE T REF ERENCE, A-M MOVSD voi d _mm_store_sd (d ouble *p, __m128d a) MOVSD __m128d _mm_store_sd (__m128d a, __m1 28d b) SIMD Floating-Poin t Ex ceptions None. Pro tected Mode Ex ceptions #GP(0) For an illegal memory oper and effective address in the CS, DS, ES, FS ...

  • Intel 253666-024US - page 721

    Vol. 2A 3-675 INSTRUCTION SE T REF ERENCE, A-M MOVSD—Move Scalar Double-Precision Floating-Point Value 64-Bit Mode Exc eptions #SS(0) If a memory a ddress referenc ing the SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault -code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit ...

  • Intel 253666-024US - page 722

    3-676 Vol. 2A MOVSHDUP—Move Packed Single-FP High and Duplicate INSTRUCTION SE T REF ERENCE, A-M MO VSHDUP—Mo ve P ack ed Single-FP High and Duplicate Descripti on The linear address corresponds to the addre ss of the least-significant byte of the referenced memory data. When a memory addr ess is indicated, the 16 bytes of data at memory locati ...

  • Intel 253666-024US - page 723

    Vol. 2A 3-677 INSTRUCTION SE T REF ERENCE, A-M MOVSHDUP—Move Packed Single-FP High and Duplicate Operation IF (Source == m128) THEN ( * Load instruction *) xmm1[31:0] = m128[63:32]; xmm1[63:32] = m128[63:32 ]; xmm1[95:64] = m128[127 :96]; xmm1[127:9 6] = m128[127:96]; ELSE (* Move instruction *) xmm1[31:0] = xmm2[63:32]; xmm1[63:32] = xmm2[63:32 ...

  • Intel 253666-024US - page 724

    3-678 Vol. 2A MOVSHDUP—Move Packed Single-FP High and Duplicate INSTRUCTION SE T REF ERENCE, A-M Real Add ress Mode Ex cep tions GP(0) If any part of the operand would lie outside of the effe ctive address space from 0 to 0FFFFH. If memory oper and is not aligned on a 16-byte boundary , regardless of segment. #NM If CR0.TS[bit 3] = 1. #UD I f CR0 ...

  • Intel 253666-024US - page 725

    Vol. 2A 3-679 INSTRUCTION SE T REF ERENCE, A-M MOVSLDUP—Move Packed Single-FP Low and Duplicate MO VSLDUP—Mo ve P ack ed Single-FP Lo w and Duplicate Description The linear address corresponds to the addre ss of the least-significant byte of the referenced memory data. When a memory ad dress is indicated, the 16 bytes of data at memory location ...

  • Intel 253666-024US - page 726

    3-680 Vol. 2A MOVSLDUP—Move Packed Single-FP Low and Duplicate INSTRUCTION SE T REF ERENCE, A-M Operat ion IF (Source == m128) THEN (* Load instruction *) xmm1[31:0] = m128[31:0]; xmm1[63:32] = m128[31:0]; xmm1[95:64] = m128[95:64]; xmm1[127:96] = m1 28[95::64]; ELSE (* Move instruction *) xmm1[31:0] = xmm2[31:0]; xmm1[63:32] = xmm2[31:0]; xmm1[9 ...

  • Intel 253666-024US - page 727

    Vol. 2A 3-681 INSTRUCTION SE T REF ERENCE, A-M MOVSLDUP—Move Packed Single-FP Low and Duplicate Real Addr ess Mode Exc eptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If memory operand is not aligned on a 16-byte boundary , regardless of segment. #NM If CR0.TS[bit 3] = 1.If CR0. TS[bit 3 ...

  • Intel 253666-024US - page 728

    3-682 Vol. 2A MOVSS—Move Scalar Single-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M MO VSS—Mo ve Scalar Single-Pr ecision Floating-Point V alues Descripti on Moves a scalar single-precision floating-poi nt value from the source operand (second operand) to the destination operand (first oper and). The source and destination o ...

  • Intel 253666-024US - page 729

    Vol. 2A 3-683 INSTRUCTION SE T REF ERENCE, A-M MOVSS—Move Scalar Single-Precision Floating-Point Values MOVSS void _mm_store_ss(float * p, __m128 a) MOVSS __m128 _mm_move_ss (__m128 a, __m128 b) SIMD Floating-Point Ex ceptions None. Pr otected Mode Ex ceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segm ...

  • Intel 253666-024US - page 730

    3-684 Vol. 2A MOVSS—Move Scalar Single-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M 64-Bit Mode Exc eptions #SS(0) If a memory address referencing t he SS segment is in a non- canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) F or a page fault. #NM If CR0.TS[bit 3] = 1. #UD I f CR0.EM[bit ...

  • Intel 253666-024US - page 731

    Vol. 2A 3-685 INSTRUCTION SE T REF ERENCE, A-M MOVSX/MOVSXD—Move with Sign-Extension MO VSX/MO VSXD—Mo ve with Sign-Ex tension Description Copies the contents of the source operand (register or memory location) to the desti- nation operand (register) and sign extends the value to 16 or 32 bits (see Fig ure 7-6 in the Intel® 64 and IA-32 Archit ...

  • Intel 253666-024US - page 732

    3-686 Vol. 2A MOVSX/MOVSXD—Move with Sign-Extension INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #GP(0) If a memory operand effe ctive address is outside the CS, DS , ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector . #SS(0) If a memory oper and effective add ress is outside the S S s ...

  • Intel 253666-024US - page 733

    Vol. 2A 3-687 INSTRUCTION SE T REF ERENCE, A-M MOVUPD—Move Unaligned Packed Double -Precision Floating-Point Values MO VUPD—Mov e Unaligned Pa ck ed Double-Precision Floating-P oint Va l u e s Description Moves a double quadword containing tw o packed double-precision floating-point values from the source oper and (second operand) to the destin ...

  • Intel 253666-024US - page 734

    3-688 Vol. 2A MOVUPD—Move Unaligned Packed Double-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M Pro tected Mode Ex ceptions #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #GP(0) For an illegal memory oper and effective address in the CS, DS, ES, FS or GS segm ents. #SS(0) For an illegal addr ...

  • Intel 253666-024US - page 735

    Vol. 2A 3-689 INSTRUCTION SE T REF ERENCE, A-M MOVUPD—Move Unaligned Packed Double -Precision Floating-Point Values #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 736

    3-690 Vol. 2A MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Value s INSTRUCTION SE T REF ERENCE, A-M MO VUPS—Mov e Unaligned Pack ed Single-Precision Floating-P oint Va l u e s Descripti on Moves a double quadword containing four packed single-precision floating-point values from the source operand (second op er and) to the desti ...

  • Intel 253666-024US - page 737

    Vol. 2A 3-691 INSTRUCTION SE T REF ERENCE, A-M MOVUPS—Move Unaligned Packed Si ngle -Precision Floating-Point Values Pr otected Mode Ex ceptions #AC(0) If alignment checking is enabled and an unaligned memory referen ce is made. #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal addr ...

  • Intel 253666-024US - page 738

    3-692 Vol. 2A MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Value s INSTRUCTION SE T REF ERENCE, A-M #UD I f CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 739

    Vol. 2A 3-693 INSTRUCTION SE T REF ERENCE, A-M MOVZX—Move with Zero-Ex tend MO VZX —Mov e with Zer o-Extend Description Copies the contents of the source operand (register or memory location) to the desti- nation operand (register) and zero extends the value. The size of the converted value depends on the operand-size attribute. In 64-bit mode, ...

  • Intel 253666-024US - page 740

    3-694 Vol. 2A MOVZX—Move with Zero-Extend INSTRUCTION SE T REF ERENCE, A-M #SS(0) If a memory oper and effective add ress is outside the S S segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used ...

  • Intel 253666-024US - page 741

    Vol. 2A 3-695 INSTRUCTION SE T REF ERENCE, A-M MUL—Unsigned Multipl y MUL —Unsigned Multiply Description Performs an unsigned multiplication of the first operand (destination oper and) and the second operand (source operand) and stores the result in the destination operand. The destination operand is an imp lied oper and located in register AL, ...

  • Intel 253666-024US - page 742

    3-696 Vol. 2A MUL—Unsigned Mu ltiply INSTRUCTION SE T REF ERENCE, A-M Operat ion IF (Byte operation) THEN AX ← AL ∗ SRC; ELSE (* Word or doub leword operation *) IF OperandSize = 16 THEN DX:AX ← AX ∗ SRC; ELSE IF Operan dSize = 32 THEN EDX:EA X ← EAX ∗ SRC; F I; ELSE (* Operan dSize = 64 *) RDX:RAX ← RAX ∗ SRC; FI; FI; Flags A ffe ...

  • Intel 253666-024US - page 743

    Vol. 2A 3-697 INSTRUCTION SE T REF ERENCE, A-M MUL—Unsigned Multipl y #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault -code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory referen ce is made. #UD If the LOCK prefix is used. Compatibility Mode Ex ceptions Same excepti ...

  • Intel 253666-024US - page 744

    3-698 Vol. 2A MULPD—Multiply Packed Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M MULPD—Multiply Pack ed Double-Precision Floating-P oint V alues Descripti on Performs a SIMD multiply of the two packed double-precision floating-point values from the source oper and (second operan d) and the destination oper and (first ...

  • Intel 253666-024US - page 745

    Vol. 2A 3-699 INSTRUCTION SE T REF ERENCE, A-M MULPD—Multiply Packed Double -P recision Floating-Point Values #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Ex ceptions #GP(0) If a ...

  • Intel 253666-024US - page 746

    3-700 Vol. 2A MULPD—Multiply Packed Double-Precision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. ...

  • Intel 253666-024US - page 747

    Vol. 2A 3-701 INSTRUCTION SE T REF ERENCE, A-M MULPS—Multiply Packed Single-Precision Floating-Point Val ues MULPS—Multiply Pack ed Single-Precision Floating-Poin t V alues Description Performs a SIMD multiply of the four pack ed single-precision floating-point values from the source operand (second oper and) and the destination operand (first ...

  • Intel 253666-024US - page 748

    3-702 Vol. 2A MULPS—Multiply Packed Single-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE[bi ...

  • Intel 253666-024US - page 749

    Vol. 2A 3-703 INSTRUCTION SE T REF ERENCE, A-M MULPS—Multiply Packed Single-Precision Floating-Point Val ues #XM If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE[b ...

  • Intel 253666-024US - page 750

    3-704 Vol. 2A MULSD—Multiply Scalar Double-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M MULSD—Multiply Scalar Double-Pr ecision Floating-Poin t V alues Descripti on Multiplies the low double-precision floati ng-point value in the source operand (second oper and) by the low double-precision floating-point v alue in the desti ...

  • Intel 253666-024US - page 751

    Vol. 2A 3-705 INSTRUCTION SE T REF ERENCE, A-M MULSD—Multiply Scalar Double-Precision Floating-Point Values #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and ...

  • Intel 253666-024US - page 752

    3-706 Vol. 2A MULSD—Multiply Scalar Double-Prec ision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID .01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled ...

  • Intel 253666-024US - page 753

    Vol. 2A 3-707 INSTRUCTION SE T REF ERENCE, A-M MULSS—Multiply Scalar Single-P reci sion Floating-Point Values MULSS—Multiply Scalar Single-Pr ecision Floating-Poin t V alues Description Multiplies the low single-precision floating-point value from the source operand (second operand) by the low single-precision floating-point value in the destin ...

  • Intel 253666-024US - page 754

    3-708 Vol. 2A MULSS—Multiply Scalar S ingle-P recision Floating-Point Values INSTRUCTION SE T REF ERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4. OSFXSR[bi t 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and ...

  • Intel 253666-024US - page 755

    Vol. 2A 3-709 INSTRUCTION SE T REF ERENCE, A-M MULSS—Multiply Scalar Single-P reci sion Floating-Point Values #UD If an unmasked SIMD floating -point exception and CR4.OSXM- MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID .01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and ...

  • Intel 253666-024US - page 756

    3-710 Vol. 2A MWAIT—Monitor Wait INSTRUCTION SE T REF ERENCE, A-M MW AIT—Monitor W ait Descripti on MW AIT instruction provides hints to allow the processor to enter an implementation- dependent optimized state. There are two principal targe ted usages: address-range monitor and advanced power managemen t. Bo th usages of MW AIT require the u s ...

  • Intel 253666-024US - page 757

    Vol. 2A 3-711 INSTRUCTION SE T REF ERENCE, A-M MWAIT—Monitor Wait processor will exit the state and handle the interrupt. If an SMI caused the processor to exit the implementation-dependent-optimized state, execution will resume at the instruction following MWAIT after handling of the SMI. Unlike the HL T instruction, the MWAIT instruction does n ...

  • Intel 253666-024US - page 758

    3-712 Vol. 2A MWAIT—Monitor Wait INSTRUCTION SE T REF ERENCE, A-M Note that if MWAIT is used to enter any of the C -states that are numerically higher than C1, a store to the address range armed by the MONITOR instruction will cause the processor to exit MWAIT only if the store was originated by other processor agents. A store from non-processor ...

  • Intel 253666-024US - page 759

    Vol. 2A 3-713 INSTRUCTION SE T REF ERENCE, A-M MWAIT—Monitor Wait EDX = 0 (* Hints *) IF ( !trigger_store_happen ed) { MONITOR EAX, ECX, EDX IF ( !trigger_store_happene d ) { MWAIT EAX, ECX } } The above code sequence mak es sure that a triggering store does not happen between the first check of the trigger and th e execution of the monitor instr ...

  • Intel 253666-024US - page 760

    3-714 Vol. 2A MWAIT—Monitor Wait INSTRUCTION SE T REF ERENCE, A-M Compatibility Mode Exc e p tions Same exceptions as in protected mode. 64-Bit Mode Exc eptions #GP(0) If the linear address of the operand in the CS, DS, ES, FS , or GS segment is in a non-canonical form. If RCX ≠ 0. #SS(0) If the linear address of the operand in the SS segment i ...

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Полная инструкция обслуживания устройства Intel 253666-024US, как должна выглядеть?
Инструкция обслуживания, определяемая также как пособие пользователя, или просто "руководство" - это технический документ, цель которого заключается в использовании Intel 253666-024US пользователями. Инструкции пишет, как правило технический писатель, языком, доступным для всех пользователей Intel 253666-024US.

Полная инструкция обслуживания Intel, должна заключать несколько основных элементов. Часть из них менее важная, как например: обложка / титульный лист или авторские страницы. Однако остальная часть, должна дать нам важную с точки зрения пользователя информацию.

1. Вступление и рекомендации, как пользоваться инструкцией Intel 253666-024US - В начале каждой инструкции, необходимо найти указания, как пользоваться данным пособием. Здесь должна находится информация, касающаяся местонахождения содержания Intel 253666-024US, FAQ и самых распространенных проблем - то есть мест, которые чаще всего ищут пользователи в каждой инструкции обслуживания
2. Содержание - индекс всех советов, касающихся Intel 253666-024US, которое найдем в данном документе
3. Советы по использованию основных функций устройства Intel 253666-024US - которые должны облегчить нам первые шаги во время использования Intel 253666-024US
4. Troubleshooting - систематизированный ряд действия, который поможет нам диагностировать а в дальнейшем очередность решения важнейших проблем Intel 253666-024US
5. FAQ - чаще всего задаваемые вопросы
6. Контактные данные Информация о том, где искать контактные данные производителя / сервисного центра Intel 253666-024US в данной стране, если самостоятельно не получится решить проблему.

У вас вопрос, касающийся Intel 253666-024US?

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Если с помощью найденной инструкции Вы не решили свою проблему с Intel 253666-024US, задайте вопрос, заполнив следующий формуляр. Если у какого то из пользователей была похожая проблема с Intel 253666-024US со всей вероятностью он захочет поделиться методом ее решения.

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