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Cypress CY7B992 - page 1
CY7B991 CY7B992 Programmable Skew Clock Buf fer Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-07138 Rev . *B Revised June 22, 2007 Features ■ All output pair skew <100 ps typical (250 maximum) ■ 3.75 to 80 MHz output operation ■ User select able output fu nctions ...
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Cypress CY7B992 - page 2
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 2 of 19 Pin Configuration Pin Definitions Signal Name IO Description REF I Reference frequency input. Th is input supplies the freque ncy and timing against which all functional variations are measured. FB I PLL feedback input (typically connec ted to one of the eight outputs). FS I Three lev ...
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Cypress CY7B992 - page 3
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 3 of 19 Block Diagram Description Phase Frequency Detect or an d Filter The Phase Frequency Detector and Filter blocks accept inputs from the reference frequency (REF) input and the fe edback (FB) input and generate correction info rmation to control the frequency of the V olt age Contro lled ...
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Cypress CY7B992 - page 4
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 4 of 19 T est Mode The TEST input is a three level inp ut. In normal system operation, this pin is connecte d to ground, enabling the CY7B991 or CY7B992 to operate as expl ained in “Skew Select Matrix” on page 3 . F or testing purposes, any of the three level inputs can have a removable j ...
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Cypress CY7B992 - page 5
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 5 of 19 Maximum Ratin gs Operating outside these boundaries affects the performance and life of the device. These user guidel ines are not tested. S torage T emperature .... ... ... ... ... ................ . –65 ° C to +150 ° C Ambient T emperature with Power Applied ............ ... ... ...
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Cypress CY7B992 - page 6
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 6 of 19 Electrical Characteristics Over the Operating Range [6] CY7B991 CY7B992 Parameter Description T est Conditions Min Max Min Max Unit V OH Output HIGH V oltage V CC = Min I OH = – 16 mA 2.4 V V CC = Min, I OH =– 40 mA V CC –0 . 7 5 V OL Output LOW V oltage V CC = Min, I OL = 46 mA ...
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Cypress CY7B992 - page 7
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 7 of 19 Cap acita nce CMOS output buffer current and power d issipa tion specified at 50 MHz re ference frequency . Parameter Description T est Cond ition s Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V CC = 5.0V 10 pF AC T est Loads and W aveforms TTL AC Test Load (CY7B991) TTL ...
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Cypress CY7B992 - page 8
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 8 of 19 Switching Characteristics Over the Operating Range [2, 13] CY7B991–2 [14] CY7B992–2 [14] Parameter Description Min Ty p Max Min Ty p Max Unit f NOM Operating Clock Frequency in MHz FS = LOW [1, 2] 15 30 15 30 MHz FS = MID [1, 2] 25 50 25 50 FS = HIGH [1, 2 , 3] 40 80 40 80 [15] t ...
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Cypress CY7B992 - page 9
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 9 of 19 Switching Characteristics Over the Operating Range [2, 13] (continued) CY7B991–5 CY7B992–5 Parameter Description Min Ty p Max Min Ty p Max Unit f NOM Operating Clock Frequency in MHz FS = LOW [1 , 2] 15 30 15 30 MHz FS = MID [1, 2 ] 25 50 25 50 FS = HIGH [1, 2 , 3] 40 80 40 80 [15 ...
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Cypress CY7B992 - page 10
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 10 of 19 Switching Characteristics Over the Operating Range [2, 13] (continued) CY7B991–7 CY7B992–7 Parameter Descr iption Min Ty p Ma x Min Ty p Max Unit f NOM Operating Clock Frequency in MHz FS = LOW [1, 2] 15 30 15 30 MHz FS = MID [1, 2] 25 50 25 50 FS = HIGH [1, 2] 40 80 40 80 [15] t ...
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Cypress CY7B992 - page 11
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 1 1 of 19 AC Timing Diagrams t ODCV t ODCV t REF REF FB Q OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 t RPWH t RPWL t PD t SKEWPR, t SKEW0, 1 t SKEWPR, t SKEW0, 1 t SKEW2 t SKEW2 t SKEW3, 4 t SKEW3, 4 t SKEW3, 4 t SKEW1, 3, 4 t SKEW2, 4 t JR [+] Feedback ...
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Cypress CY7B992 - page 12
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 12 of 19 Operational M ode Descriptions Figure 2 shows the PSCB configure d as a zero skew clock buffer . In this mode the 7B991/992 is us ed as th e basis for a low-skew clock distribution tree. When all of the func tion select inpu ts (xF0, xF1) are left open, the outputs are aligned an d e ...
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Cypress CY7B992 - page 13
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 13 of 19 the FB and REF inputs and ali gns their rising edges to ensure that all outputs have precise phase alignment. Clock skews are advanced by ±6 time units (tU) when using an output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB ...
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Cypress CY7B992 - page 14
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 14 of 19 range since the highest frequency output i s running at 20 MHz. Figure 7 shows some of the fu nctions that are se lectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that offer divide-by-2 and d ivide-by-4 timing. An inverted output enables the system desi ...
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Cypress CY7B992 - page 15
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 15 of 19 Figure 8 shows the CY7B991 and 992 connected in se ries to construct a zero skew clock distribution tree between boards. Delays of the downstream clock buffers are programmed to compensate for the wire length (that is, sele ct negative skew e qual to the wi re delay) necessary to con ...
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Cypress CY7B992 - page 16
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 16 of 19 Ordering Information Accuracy (p s) Ordering Co de Package T ype Operating Range 250 CY7B991–2JC 32-Pb Pl astic Leaded Chip Carrier Commercial CY7B991–2JCT 32-Pb Plastic Le aded Chip Carri er - T ape and Reel Commercial 500 CY7B991–5JC 32-Pb Plasti c Leaded Chip Ca rrier Commer ...
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Cypress CY7B992 - page 17
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 17 of 19 Milit ary Specifications Group A Subgroup T esting DC Characteristics Parameter Subgroups V OH 1, 2, 3 V OL 1, 2, 3 V IH 1, 2, 3 V IL 1, 2, 3 V IHH 1, 2, 3 V IMM 1, 2, 3 V ILL 1, 2, 3 I IH 1, 2, 3 I IL 1, 2, 3 I IHH 1, 2, 3 I IMM 1, 2, 3 I ILL 1, 2, 3 I CCQ 1, 2, 3 I CCN 1, 2, 3 Pack ...
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Cypress CY7B992 - page 18
CY7B991 CY7B992 Document Number: 38-0713 8 Rev . *B Page 18 of 19 Figure 10. 32-Pin Rectang ular Leadless Chip Carrier Package Diagrams (continued) MIL-STD-1835 C-12 51-85002-*B [+] Feedback ...
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Cypress CY7B992 - page 19
Document Number: 38-07138 Rev . *B Revise d June 22, 2007 Page 19 of 19 PSoC Designer™, Programmable System-on-Chip ™, an d PS oC Exp re ss™ are tra demarks a nd PSo C® is a registe red t rade mark of Cypress S emi con ductor Corp. All o the r tr a dem a rks o r re gi ster e d trademar ks refere nced herei n are prop erty of the respe ctive ...
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