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Инструкция обслуживания Arm Enterprises IM-AD1

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  • Arm Enterprises IM-AD1 - page 1

    Copyright © 2001-2003. All rights reserved. ARM DUI 0163B Integ r ator/IM-AD1 User Guide ...

  • Arm Enterprises IM-AD1 - page 2

    ii Copyright © 2001-2003. All rights reserved. ARM DUI 0163B Integrator/IM-AD1 User Guide Copyright © 2001-20 03. All rights reserved. Release Information Proprietary Notice W ords and logos mark ed with ® or ™ are re gistered trademarks or trad emarks owned by ARM Limited, e xcept as otherwise stated below in this proprietary notice. Other br ...

  • Arm Enterprises IM-AD1 - page 3

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. iii Conformance Notices This section con tains conforma nce notices. Federal Communications Commission Notice This device is test equipment and consequently is ex em pt from part 1 5 of the FCC Rules unde r section 15.1 03 (c). CE Declaration of Conformity The system should be po wered down ...

  • Arm Enterprises IM-AD1 - page 4

    iv Copyright © 2001-2003. All rights reserved. ARM DUI 0163B ...

  • Arm Enterprises IM-AD1 - page 5

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. v Contents Integrator/IM-AD1 User Guide Preface About this book ............. .............. ........... .............. .............. ........... ............... viii Feedback ........... .............. ........... .............. ........... .............. ........... ............... .. xi ...

  • Arm Enterprises IM-AD1 - page 6

    Contents vi Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 3.7 CAN interface .................... .............. ........... .............. .............. ........... ....... 3-14 3.8 ADC and DAC interfaces .............. .............. .............. .............. .............. .... 3-18 Chapter 4 Reference Design Example 4.1 About t ...

  • Arm Enterprises IM-AD1 - page 7

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. vii Preface This preface introduces the Integrator /IM-AD1 interface module and its user documentation. It contains the follo wing sections: • About this book on page viii • F eedback on page xi. ...

  • Arm Enterprises IM-AD1 - page 8

    Preface viii Copyright © 2001-2003. All rights reserved. ARM DUI 0163B About this book This book provides user information for the ARM Integrator/IM-AD1 interface module. It describes the major features and ho w to use the interf ace module with an Inte grator dev elopment platform. Intended audienc e This book is written for all dev elopers who a ...

  • Arm Enterprises IM-AD1 - page 9

    Preface ARM DUI 0163B Copyright © 2001-2003. All rights reserved. ix T ypographical con ventions The following typographical con v entions are used in this book: italic Highlights important notes, introduces special terminol ogy , denotes internal cross-references, and citations. bold Highlights interface elements, such as menu names. Denotes ARM ...

  • Arm Enterprises IM-AD1 - page 10

    Preface x Copyright © 2001-2003. All rights reserved. ARM DUI 0163B The following publications provide information abou t ARM PrimeC ell devices that can be used to control some of the in terfaces described in this manua l: • ARM PrimeCell UART (PL011) T ech nical Refer ence Manual (ARM DDI 0183) • ARM PrimeCell Synchr ono us Serial P ort Mast ...

  • Arm Enterprises IM-AD1 - page 11

    Preface ARM DUI 0163B Copyright © 2001-2003. All rights reserved. xi Feedback ARM Limited welcomes feedb ack on both the Integrator/IM-AD1 and its documentation. Feedbac k on this document If you hav e any comments on this book, please send emai l to errata@arm.com gi ving: • the document title • the document number • the page number(s) to w ...

  • Arm Enterprises IM-AD1 - page 12

    Preface xii Copyright © 2001-2003. All rights reserved. ARM DUI 0163B ...

  • Arm Enterprises IM-AD1 - page 13

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 1-1 Chapter 1 Intr oduction This chapter introduces the Integrator/IM-AD1. It contai ns the following sections: • About the Inte grator/IM-AD1 on page 1-2 • Interface module featu r es and ar chitectur e on page 1-4 • Links and LEDs on page 1-6 • Car e of modules on page 1-7. ...

  • Arm Enterprises IM-AD1 - page 14

    Introduction 1-2 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 1.1 About the In tegrator/IM-AD1 The Integrator/IM-AD1 is an interface module that is desi gned to be used in conjunction with the Integrator/LM-XCV600E+ or LM-E P20K600E+ and future compatible logic modules. It provides se veral standard automo ti ve and industrial interfa ...

  • Arm Enterprises IM-AD1 - page 15

    Introduction ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 1-3 Figure 1-1 Integrator/IM-AD1 la y out CONFIG LED Serial por t (J18) Logic analyzer (J7) GPIO A (J17) GPIO B (J16) A/D Inputs (J1) D/A Outputs (J2) SPI1 (J11) SPI2 (J13) Stepper motor control (J19 and J20) Stepper motor control (J21 and J22) PWM (J14 and J10) CAN (J3A and J3 ...

  • Arm Enterprises IM-AD1 - page 16

    Introduction 1-4 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 1.2 Interface module feat ures and ar chitecture This section describes the main features of the interface module and its architecture. 1.2.1 Features The main features of the in terface module are as follo ws: • two Bosch CC770 Contr oll er Ar ea Network (CAN) controller ...

  • Arm Enterprises IM-AD1 - page 17

    Introduction ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 1-5 1.2.2 Ar chi tecture Figure 1-2 shows the architecture of the inte rface module. For more detail on signal routing between the expansi on connectors and the interf ace circuits, see Chapter 3 H a rd w a re R e f e re n c e . Figure 1-2 I ntegrator/I M-AD1 block diagram J3A ...

  • Arm Enterprises IM-AD1 - page 18

    Introduction 1-6 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 1.3 Links and LEDs The interface module pro vides one link an d one LED. These are the CONFIG link and CONFIG LED. Fitting the CONFIG link places all of the modules in the stack on which the interf ace module is mounted into CONFIG m ode. This mode enables you to reprogram ...

  • Arm Enterprises IM-AD1 - page 19

    Introduction ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 1-7 1.4 Care of modules This section contains advice about how to prev ent damage to your Integrator modules. Caution T o prev ent damage to your Integrator system, observ e the following precautions: • When removing a core or logic module from a m otherboard, or when separat ...

  • Arm Enterprises IM-AD1 - page 20

    Introduction 1-8 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B ...

  • Arm Enterprises IM-AD1 - page 21

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 2-1 Chapter 2 Getting Star ted This chapter describes how to set up and start using the logic module. It contains the following sections: • F itting the interface module o n page 2-2 • Setting up the logic module on page 2-3 • Running the test software on page 2-4 ...

  • Arm Enterprises IM-AD1 - page 22

    Getting Started 2-2 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 2.1 Fitting the interface module The interface module is installed at the top of a stack of up to four logic modules. Howe ver , it only provides interface conn ections for the logic module immediately beneath it. Figure 2-1 shows an e xample system comprising a core mod ...

  • Arm Enterprises IM-AD1 - page 23

    Getting Started ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 2-3 2.2 Setting up t he logic module Y ou must load the required peripheral contro llers into the logic module F PGA to drive the interfaces. The interface module is supp lied with example c onfigurations that provide PrimeCell peripherals for supported logic modules. The lo ...

  • Arm Enterprises IM-AD1 - page 24

    Getting Started 2-4 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 2.3 Running the test software The supplied test program tests each of the interf aces on the IM-AD1. The e xample logic module configuration mu st be prog rammed into th e logic modu le before the test program can be run. Note The test software requires v arious cables t ...

  • Arm Enterprises IM-AD1 - page 25

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-1 Chapter 3 Har dware Ref erence This chapter describes the hardware interfaces and controllers on the interface module. This chapter contains the following sections: • Differ ences in signal r outing between supported logic modules on p age 3-2 • U ART interface on page 3-3 • SPI o ...

  • Arm Enterprises IM-AD1 - page 26

    Hardware Referenc e 3-2 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 3.1 Differences in signal r outi ng between suppor ted logic modules The Integrator/LM-XCV600E+ and LM-EP20K600E+ logic module types route the signals from the interface module dif ferently as follows: The • LM-XCV600E+ is fitted with a Xilin x FPGA and routes the ...

  • Arm Enterprises IM-AD1 - page 27

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-3 3.2 U ART interface The interface module pro vides one serial tran scei ver suitable for use with the PrimeCell U AR T (PL011) or other similar peripheral. Figure 3-1 shows the architecture of the U AR T interface. Figure 3-1 Ser ial interfac e The signals associated ...

  • Arm Enterprises IM-AD1 - page 28

    Hardware Referenc e 3-4 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B The serial interface uses a 9-pin D-type male connector for which the pin numbering is shown in Figure 3-2. Figure 3-2 Serial conn ector pinout T able 3-2 shows the signal assignment for the connector . Note The serial interfaces signals operate at RS232 signal le ve ...

  • Arm Enterprises IM-AD1 - page 29

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-5 3.3 SPI This interface module provides two connect ors for SPI ports. They are connected directly to the logi c module FPGA and are used by th e SSP PrimeCell (PL022) in the example configuration. T able 3-3 sho ws the assignment of the SPI signals to the logic module ...

  • Arm Enterprises IM-AD1 - page 30

    Hardware Referenc e 3-6 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 3.4 PWM interface The interface module is fitted with a dual MOSFET switch. This pro vides two outputs that can be conf igured as Pulse W idth Mo dulated (PWM) outputs or used as DC switches to switch external loads. The MOSFET can switch loads at up to 30V . Althoug ...

  • Arm Enterprises IM-AD1 - page 31

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-7 T able 3-5 sho ws the signal assignment. T able 3-5 PWM co nnector sign als Pin J14 J10 Description 1 PWM1_+V PWM2_+V PWM supply v oltage 2 PWM1_SWI TCH PWM2_S WITCH PWM switched load connection 3 PWM1_FB PWM2_FB PWM feedback signal 4 PWM_GND PWM_GND PWM ground ...

  • Arm Enterprises IM-AD1 - page 32

    Hardware Referenc e 3-8 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 3.5 Stepper motor interface The IM-AD1 provides four st epper motor interf aces. T wo of these, Step 1 and Step 2, are provided with on-board motor driv ers fo r bipolar motors. The remai ning two, Step 3 and Step 4, provide logic-le v el signals that are connected t ...

  • Arm Enterprises IM-AD1 - page 33

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-9 The current limit is set by the reference voltage and sense resistor according to the equation: Therefore, with a 0.1 Ω sen se resist or fitted: The reference v oltage, and therefore the curren t limit, can be adjusted by altering the values of the di vider resistors ...

  • Arm Enterprises IM-AD1 - page 34

    Hardware Referenc e 3-10 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 3.5.3 Stepper motor connector s Figure 3-6 shows the pin numbering of the stepper motor connectors. Figure 3-6 Stepper moto r connector (J 19/J23) STEP2_PH1 F8 Step2 phase 1 driv e signal STEP2_PH2 F9 Step2 phase 2 driv e signal STEP2_PH3 F10 Step2 phase 3 dri ve si ...

  • Arm Enterprises IM-AD1 - page 35

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-11 T able 3-7 sho ws the signal assignment. T able 3-7 Stepper moto r connec tor signals Pin J19 J23 Description 1 STEP1_VSS STEP2_VSS Stepper motor supply 2 STEP1_O1 STEP2_O1 Stepper motor dri ve output 1 3 STEP1_O2 STEP2_O2 Stepper motor dri ve output 2 4 STEP1_O3 STE ...

  • Arm Enterprises IM-AD1 - page 36

    Hardware Referenc e 3-12 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 3.6 GPIO The interface module prov ides two connect ors for GPIO interf aces. Each connector provides 32 GPIO lines connected directly to the logic mod ule FPGA. The connectors are shown in Figure 3-7. Figure 3-7 GPIO connectors J16 and J17 +5V GPIOA1 GND GPIOA4 GPI ...

  • Arm Enterprises IM-AD1 - page 37

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-13 The example conf iguration includes two simple 32-bit GPIO controllers. GP IO A[31:0] connect to the EXPIM signals IM_AB ANK[3 1:0] and GPIOB[31:0] connects to the EXP A signal s B[31:0] . The B[31:0] signals can be monitored on the logic analyzer connector J7. ...

  • Arm Enterprises IM-AD1 - page 38

    Hardware Referenc e 3-14 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 3.7 CAN interface The IM-AD1 has two CAN interfaces pro vided by Bosch CC770 serial communications controllers. The network interfaces are pro v ided by Philips TJ A1050 transceiv ers, each capable of 1Mb/s data transfer . Figure 3-8 sho ws the architect ure of the ...

  • Arm Enterprises IM-AD1 - page 39

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-15 All interface signals are routed to the logi c module . The CAN cont rollers are supported by an AHB interface instantiated into the logic module code example supplied with the IM-AD1. The transmit and recei ve data signals, CANx_TXD and CANx_RXD , at the EXPIM conne ...

  • Arm Enterprises IM-AD1 - page 40

    Hardware Referenc e 3-16 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B Y ou connect the CAN interfaces through th e 9-pin D-type plugs J3A (top) and J3B (bottom), with CAN1 connecting to J3A. Figure 3-9 shows the pin locations for this type of connector . Figure 3-9 CAN connector pin locations CAN2_nINT IM_BB ANK28 CAN2 interrupt CAN1_ ...

  • Arm Enterprises IM-AD1 - page 41

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-17 T able 3-9 sho ws the signal assignment. T able 3-9 CAN connector signal assignments Pin J3A J3B 1 Not connected Not connected 2 CAN1_L CAN2_L 3 GND GND 4 Not connected Not connected 5 GND GND 6 GND GND 7 CAN1_H CAN2_H 8 Not connected Not connected 9 Not connected No ...

  • Arm Enterprises IM-AD1 - page 42

    Hardware Referenc e 3-18 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 3.8 ADC and D A C interfaces The interface module prov ides two A to D Con verters (ADC) and a D to A Con verter (D A C). The two ADCs each provide eight analog inputs with b uf fered 0-5V inputs, an internal multiplex er , and a 12-bit con verte r . The ADCs provid ...

  • Arm Enterprises IM-AD1 - page 43

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-19 T able 3-10 sho ws the assignment of the AD C and D A C interface signals to the logic module signals on the EXPIM co nnector . The ADCs are clocked from a 4MHz oscillator . This also supplies the IM _CLK signal routed to the logic m odule FPGA. This is us ed in the ...

  • Arm Enterprises IM-AD1 - page 44

    Hardware Referenc e 3-20 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B The analog inputs to the ADCs are buf fered by LM V324 operat ional ampl ifiers (op-amps). The op-amps are conf igured to gi ve unity gain but the inputs have a resistiv e divider that di vides the input voltage by 2. A 0-5V input signal range at the buffer inputs p ...

  • Arm Enterprises IM-AD1 - page 45

    Hardware Reference ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 3-21 Figure 3-12 shows the pinout of th e D A C interface connector (J2). Figure 3-12 D A C connector pinout 5V VOUTA VOUTB 5V GND GND GND GND 12 91 0 J2 ...

  • Arm Enterprises IM-AD1 - page 46

    Hardware Referenc e 3-22 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B ...

  • Arm Enterprises IM-AD1 - page 47

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-1 Chapter 4 Reference Design Example This chapter describes how to set up and start using the supplied example design. It contains the follo wing sections: • About the de sign e xample on pa ge 4-2 • Example APB r e gist er peripheral on page 4-8 • U ART on page 4-13 • SPI chip s ...

  • Arm Enterprises IM-AD1 - page 48

    Reference Design Example 4-2 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.1 About the design example This chapter describes the reference design e xample supplied with the interf ace module. The interface module is not f itted with an y programmable de vices because it is intended to provide interfaces for peripherals instantiated i ...

  • Arm Enterprises IM-AD1 - page 49

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-3 Figure 4-1 Design example ar chitecture T able 4-1 provides a summary description of the supplied VHDL files. A more detailed description of each VHDL block is included wi thin the f iles in the form of comments. AHB to APB bridge UART PIB AHB SSP GPIO A Stepper ...

  • Arm Enterprises IM-AD1 - page 50

    Reference Design Example 4-4 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.1.3 Example memory map The supplied ex amples set up the memory map for the logic module as shown in Figure 4-2 on page 4-5. This shows the locations to which logic modules are assigned by the main address decoder on an Integr ator/AP motherboard when the logi ...

  • Arm Enterprises IM-AD1 - page 51

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-5 Figure 4-2 Integrator system memory map Note The Integrator system implements a distrib uted addre ss decoding scheme in which each core or logic mo dule is responsible for decoding its own address space. It is important when implementing a logic modu le design, ...

  • Arm Enterprises IM-AD1 - page 52

    Reference Design Example 4-6 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B page 4-6 shows the v alues of address bits [3 1:28] on logic modules fitted to an Integrator/AP in the EXP A/EXPB conn ector position (see the Integr ator/AP User Guide for more information). 4.1.5 Integrator /IM -AD1 memory map The memory model for the design i ...

  • Arm Enterprises IM-AD1 - page 53

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-7 STEPPERB 0xC0C00000 GPIO A 0xC0D00000 GPIOB 0xC0E00000 Reserved 0xC1000000 SSRAM 0xC2000000 VIC 0xC3000000 CAN 0xC4000000 ADC/D A C 0xC5000000 PIB 0xCFFFFF00 T able 4-3 Integrator/IM-AD1 memory map (continued) Device Address ...

  • Arm Enterprises IM-AD1 - page 54

    Reference Design Example 4-8 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.2 Example APB r egister peripheral T abl e 4-4 shows the mapping of the logic module registers. The addresses sho wn are of fsets from the base addresses shown in Figure 4-2 on page 4-5. T able 4-4 Logic module regi sters Offset address Name T ype Function 0x0 ...

  • Arm Enterprises IM-AD1 - page 55

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-9 4.2.1 Oscillator divi sor register s The oscillator registers contro l the frequenc y of the clocks genera ted b y the tw o clock generators on the logic modu le. Before writing to the oscillator registers, you must unlock them by writing the value 0x0000A05F to ...

  • Arm Enterprises IM-AD1 - page 56

    Reference Design Example 4-10 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B Y ou must also observe the operating range limits: Note The def ault values for these registers set CLK1 to 25MHz and CLK2 to 12MHz. T able 4-5 LM_OSCx register s Bits Name Access Functi on 18:16 OD Read/write Output di vider: 000 = divide b y 10 001 = divide b ...

  • Arm Enterprises IM-AD1 - page 57

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-11 4.2.2 Oscillator lo ck register The lock register is used to control access to the oscillator registers, allo wing them to be locked and unlocked. This mechanism pre v ents the oscillator registers from being ov erwritten accidently . T able 4-6 de scribes the ...

  • Arm Enterprises IM-AD1 - page 58

    Reference Design Example 4-12 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.2.5 Switc hes register This register is used to r ead the setting of the 8-way DIP switch on the lo gic module. A 0 indicates that the associated switch element is closed (ON). ...

  • Arm Enterprises IM-AD1 - page 59

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-13 4.3 U ART The U AR T used in the design e xample is the PrimeCell PL011. Refer to the ARM PrimeCell U ART (PL011) T echnical Refer ence Manual for more in formation. The U AR T is clocked b y the signal CLK2 from the l ogic module. CLK2 is set to 12MHz by defau ...

  • Arm Enterprises IM-AD1 - page 60

    Reference Design Example 4-14 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.4 SPI chip select register This is a 3-bit read/write register that co ntrols the three chip select signals on the connectors J11 and J13. Writing a 1 causes the associated SPI chip select signal to go LO W . T able 4-8 SPI ch ip select register bit assignmen ...

  • Arm Enterprises IM-AD1 - page 61

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-15 4.5 Synchr onous serial port The synchronous serial port PrimeCell is used to implement the SPI interface. Refer to the ARM PrimeCell Synchr onous Se rial P ort Master and Slave (PL022) T echnical Refer ence Manual for information about this device. The SSP is ...

  • Arm Enterprises IM-AD1 - page 62

    Reference Design Example 4-16 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.6 PWM controller The PWM control function is implemente d by the DC-DC con verter PrimeCell (PL160). Refer to the ARM PrimeCell DC-DC Converter Interface (PL160) T echnical Refer ence Manual f or information about th is de vice. The DC-DC PrimeCell uses the 4 ...

  • Arm Enterprises IM-AD1 - page 63

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-17 4.7 Stepper motor peripheral The example design instantiat es tw o stepper controller blo cks, each of which has two stepper motor cont rollers. Stepper A contro ls the Step 1 and 2 interfaces which are connected to the L298 stepper motor drivers. Stepper B con ...

  • Arm Enterprises IM-AD1 - page 64

    Reference Design Example 4-18 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.7.1 Stepper x contr ol register The stepper controller control register defines the operating mode of the stepper . Note Y ou must consider the maxim um speed of the stepper motor when prog ramming the step speed register or issuing consecuti v e si ngle step ...

  • Arm Enterprises IM-AD1 - page 65

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-19 Figure 4-3 Full-step two-phase output waveforms Figure 4-4 Full-step sing le-phase output wa veforms 2 DOCOUNT Read/write Write a 1 to this bit t o transfer the conte nts of the buf fer register to the count and speed registers. This causes the corresponding nu ...

  • Arm Enterprises IM-AD1 - page 66

    Reference Design Example 4-20 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B Figure 4-5 Half-step output waveforms 4.7.2 Stepx count register This is a 9-bit re gister that is used to speci fy the number of steps to adv ance. When the required number of steps are complete, the count stops and th e register is loaded with the next v alue ...

  • Arm Enterprises IM-AD1 - page 67

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-21 4.8 GPIO There are two 32-bit GPIO blocks instantia ted in the example design. Each GPIO provides 32 general-purpose i nput and output signals that are con nected to the connectors J16 and J17. GPIOB is also connecte d to the 38-way Mictor connector J7 for easy ...

  • Arm Enterprises IM-AD1 - page 68

    Reference Design Example 4-22 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.8.5 Data direction The GPIO_DIRN location is used to set th e direction of each GP IO pin as follo ws: 1 = pin is an output 0 = pin is an input (default). Figure 4-6 shows the data direction control for one GPIO bit. Figure 4-6 GPIO direction contr ol (1 bit) ...

  • Arm Enterprises IM-AD1 - page 69

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-23 4.9 SSRAM interface The SSRAM interface pro vides read and write access to the 1MB ZBT SSRAM on the logic module. Accesses take two system cloc k cycles for reads and writes. The interf ace supports word, halfw ord, and byte accesses to the SSRAM. ...

  • Arm Enterprises IM-AD1 - page 70

    Reference Design Example 4-24 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.10 V ectored interrupt controller The interrupt controller used in the example design is the V ector ed Interrupt Co ntr oller (VIC) PrimeCell (PL1 90). Refer to the ARM PrimeCell V ector ed Interrupt Contr oller (PL190) T echnical Refer ence Manual for infor ...

  • Arm Enterprises IM-AD1 - page 71

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-25 The SSP interrupt is the combined inter rupt from the SSP Prim eCell. Refer to ARM PrimeCell Synchr ono us Serial P ort (PL022) T echnical Reference Manual for details of the interrupt sources. The STEP1, STEP2, STEP3, and STEP4 inte rrupts are set acti ve when ...

  • Arm Enterprises IM-AD1 - page 72

    Reference Design Example 4-26 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.11 CAN contr oller interface The CAN controller interface gi ves you access to the internal registers and reset signals of the Bosch C C770 CAN controll ers. The offset addresses of CAN controller interfaces are sho wn in T able 4-14. 4.11.1 CANxBase Y ou use ...

  • Arm Enterprises IM-AD1 - page 73

    Reference Design Example ARM DUI 0163B Copyright © 2001-2003. All rights reserved. 4-27 4.12 ADC and D A C interface This interface gi ves you access to the ADCs and D A C. The interface also contains a status and control register . The of fset addresses of the ADC and D AC interf ace are shown in T able 4-16. The ADCs each appear as one 16-bit lo ...

  • Arm Enterprises IM-AD1 - page 74

    Reference Design Example 4-28 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B 4.13 P eripheral information b loc k The P eripheral Information Block (PIB) is a block of 32 words in R OM that provides you with information about the peripherals used in the design. The PIB is located at the top of the address space for the logic module. Eac ...

  • Arm Enterprises IM-AD1 - page 75

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. A-1 Appendix A Signal Descriptions This appendix describ es the Integrator/IM-AD1 interface connectors and signal connections. It contains the following sections: • EXP A on p age A-2 • EXPB on page A-4 • EXPIM on page A-6 • Logic analyzer connector on page A-8 • Multi-ICE (JT A G ...

  • Arm Enterprises IM-AD1 - page 76

    Signal Descriptions A-2 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B A.1 EXP A Figure A-1 shows the pin numbers of the EXP A socket. The socket is vie wed as if looking down through the stack. Figure A-1 EXP A socket pin numbering ...

  • Arm Enterprises IM-AD1 - page 77

    Signal Descriptions ARM DUI 0163B Copyright © 2001-2003. All rights reserved. A-3 The signals present on the EXP A c onnector are described in T able A-1. T able A-1 AHB signal assignment Pin label Signal Description A[31:0] Not used - B[31:0] B[31:0] These signals connect to the FPGA on the logic module. The y are used to carry the GIPOB[31:0] si ...

  • Arm Enterprises IM-AD1 - page 78

    Signal Descriptions A-4 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B A.2 EXPB Figure A-2 shows the pin numbers of the sock et EXPB on the underside of the interface module. Figure A-2 EXPB socket pin n umbering 61 H2 GND GND F0 F1 F2 GND GND F3 H5 F4 F5 GND GND F6 H8 F7 F8 GND GND F9 H11 F10 F11 H14 GND GND F12 F13 F14 GND GND F15 H17 ...

  • Arm Enterprises IM-AD1 - page 79

    Signal Descriptions ARM DUI 0163B Copyright © 2001-2003. All rights reserved. A-5 T able A-2 describes the signals on the pins labeled F[3 1:0], H[31:0], and J[16:0]. T able A-2 EXPB signal description Pin label Name Desc ription F[31:24] Not used - F[23:0] F[23:0] Stepper motor co ntroller signals. H[31:29] Not used - H28 SYSCLK System clock from ...

  • Arm Enterprises IM-AD1 - page 80

    Signal Descriptions A-6 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B A.3 EXPIM This connector is the same type of as that used for EX P A. Figure A-3 shows the pin numbers for EXPIM. Figure A-3 EXPIM connector s pin numbering 101 IM_A1 GND GND GND IM_B0 IM_B1 GND IM_B2 GND IM_A4 IM_B3 IM_B4 GND IM_B5 GND IM_A7 IM_B6 IM_B7 GND IM_B8 GN ...

  • Arm Enterprises IM-AD1 - page 81

    Signal Descriptions ARM DUI 0163B Copyright © 2001-2003. All rights reserved. A-7 T able A-3 shows the signals for the inte rf ace module for Integrator/LM-XCV2000E or LM-EP20K1000E logic module types. Caution F or correct operation of the interface module, VCCO_A and VCCO_B must be set to 3.3V . Ensure that the VCCO links ar e set correctly on th ...

  • Arm Enterprises IM-AD1 - page 82

    Signal Descriptions A-8 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B A.4 Logic analyzer connector A Mictor-type logic analyzer connector is provided. It co nnects to the B[31:0] signals used for GPIO B. If particular sign als must be connected to a logic analyzer , the FPGA configuration can be changed to reassign the signal connectio ...

  • Arm Enterprises IM-AD1 - page 83

    Signal Descriptions ARM DUI 0163B Copyright © 2001-2003. All rights reserved. A-9 T able A-4 sho ws the pinout of the logic analyzer connector . T able A-4 J7 connector pinout Signal Pin Pin Signal No connect 1 2 No connect GND 3 4 No connect SYSCLK 56C L K _ 1 B31 78 B15 B30 91 0 B14 B29 11 12 B13 B28 13 14 B12 B27 15 16 B11 B26 17 18 B10 B25 19 ...

  • Arm Enterprises IM-AD1 - page 84

    Signal Descriptions A-10 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B A.5 Multi-ICE (JT A G) Figure A-5 shows the pinout of the Multi-ICE connector J21. For a description of the JT A G signals, see the user gu ide for your logic mod ule. Figure A-5 Mult i-ICE connector pi nout 3V3 nTRST TDI TMS TCK RTCK TDO nSRST 3V3 GND GND GND GND G ...

  • Arm Enterprises IM-AD1 - page 85

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. B-1 Appendix B Mechanical Specification This appendix contains the m echanical specif ication for Inte grator/IM-AD1. It contains the follo wing section: • Mechanical information on page B-2 • Connector refer ence on page B-4. ...

  • Arm Enterprises IM-AD1 - page 86

    Mechanical Specification B-2 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B B.1 Mechanical inf ormation Figure B-1 sho ws the dimensions for the connectors on the top side of the board. See T abl e B-1 o n page B-4 for d etails on connect or ty pe, part numbers, and manufacturers. Figure B-1 Board dimensions (top vi ew) The Integrator/I ...

  • Arm Enterprises IM-AD1 - page 87

    Mechanical Specification ARM DUI 0163B Copyright © 2001-2003. All rights reserved. B-3 Figure B-2 Bottom board dimensions (viewed from top side) 171.96 109.98 99.95 138.00 99.95 26.16 9.98 J4 J5 J6 90.23 ...

  • Arm Enterprises IM-AD1 - page 88

    Mechanical Specification B-4 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B B.2 Connector reference T abl e B-1 list s the connectors on the IM-AD1. T wo W eidmuller BL3.5/6 SN OR plugs and two BL3.5/4 SN OR plugs are supplied in a separate plastic bag. These mate with J10, J14, J19, and J23. T able B-1 connector reference Reference T y ...

  • Arm Enterprises IM-AD1 - page 89

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. Glossary-1 Glossary This glossary lists al l the abbreviations used in the Integrator/IM-AD1 User Guide. ADC Analog to Digital Con verter . A device that co n verts an analog signal into digital data. AHB Advanced High Performance Bus. The AR M open standard fo r high-performance on-chip b ...

  • Arm Enterprises IM-AD1 - page 90

    Glossary Glossary-2 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B SSP Sy nchronous Serial Port. UA R T Uni versal Asynchronous Recei ver/T ransmitter . USB Uni versal Serial Bus. VCO V oltage Contr olled Oscillator . VIC V ectored Interru pt Controller . ZBT SSRAM Zero Bus T urnaround Synchronous Static Random Access Memory . ...

  • Arm Enterprises IM-AD1 - page 91

    ARM DUI 0163B Copyright © 2001-2003. All rights reserved. Index-1 Inde x The items in this inde x are listed in alphabetical order , with symbols and numerics appearing at the end. The references giv en are to page numbers. A ADC and DAC interface a rchitecture 3-18 ADC and DAC interface registers 4-27 ADC connector 3-20 ADC, sampling rate 1-4 APB ...

  • Arm Enterprises IM-AD1 - page 92

    Index Index-2 Copyright © 2001-2003. All rights reserve d. ARM DUI 0163B G GPIO 4-21 GPIO connector 3-12 GPIO interface 3-12 GPIO registers GPIO_DATACLR 4-21 GPIO_DATAIN 4-21 GPIO_DATAOUT 4-21 GPIO_DATASET 4-21 GPIO_DIRN 4-22 I Identifying the connectors 1-2 IMCLK signal 3-19, 4-16, 4-17 Integrator memory map 4-5 Interrupt assignment 4-24 L Logic ...

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